ST STM32MP25x
The ST STM32MP25 are the second generation of STM32 application processors offering higher performances with a 64-bit platform, specifically designed for industrial applications. It includes up 2x Cortex-A35 cores, Cortex-M33 and Cortex-M0+.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| External QSPI flash [1] | 0x60000000 | 
|
CLK@PD0_nCS@PD3_D0@PD4_D1@PD5_D2@PD6_D3@PD7_D42NA_D5@NA_D6@NA_D7@NA | 256 MB |
- ↑
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for this Device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
Watchdog Handling
- The device has 5 watchdogs IWDG1 - IWDG4, WWDG.
- The watchdogs are fed during flash programming.
- The watchdogs can be configured in normal or window mode.
- If IWDGx are configured in normal mode the watchdog is fed during flash programming.
- If IWDGx are configured in window mode the watchdog is not fed.
- If WWDG1 is configured in normal mode the watchdog is fed during flash programming.
- If WWDG1 is configured in window mode the watchdog is fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The STM32MP25 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| ARM Cortex-A35_0 |
|
| ARM Cortex-A35_1 |
|
| ARM Cortex-M33 |
|
| ARM Cortex-M0+ |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
ARM Cortex-A35 0 core
Init/Setup
- If it is the main boot core, is responsible for enabling debugging access.
Reset
- Reset is not implemented, as device uses bootloader and can restrinct access to system resources.
- If security resource isolation is used, reset may not be generated, but instead synchronos abort event.
Attach
- Attach is supported.
ARM Cortex-A35 1 core
Init/Setup
- The main core is responsible for releasing core 1 from reset.
Reset
- The same rules apply as for core 0.
Attach
- Attach is supported.
ARM Cortex-M33 core
Init/Setup
- If it is the main boot core, is responsible for enabling debugging access.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Attach
- Attach is supported.
ARM Cortex-M0 core
Init/Setup
- The Cortex-M0 is switched off by default. If it is not enabled during boot, it will be released from reset.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Attach
- Attach is supported.
Limitations
ARM Cortex-M0 DAP Access
The J-Link software accesses the Cortex-M0 core via SWJ-DP pins, not its dedicated SWD port.