/*
** ###################################################################
**     Processor:           MIMXRT595SFFOA_dsp
**     Compiler:            XCC Compiler
**     Reference manual:    RT500 Reference Manual. Rev.0,09/2019
**     Version:             rev. 2.0, 2019-07-22
**     Build:               b190918
**
**     Abstract:
**         CMSIS Peripheral Access Layer for MIMXRT595S_dsp
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2019 NXP
**     All rights reserved.
**
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2019-04-19)
**         Initial version.
**     - rev. 2.0 (2019-07-22)
**         Base on rev 0.7 RM.
**
** ###################################################################
*/

/*!
 * @file MIMXRT595S_dsp.h
 * @version 2.0
 * @date 2019-07-22
 * @brief CMSIS Peripheral Access Layer for MIMXRT595S_dsp
 *
 * CMSIS Peripheral Access Layer for MIMXRT595S_dsp
 */

#ifndef _MIMXRT595S_DSP_H_
#define _MIMXRT595S_DSP_H_                       /**< Symbol preventing repeated inclusion */

/** Memory map major version (memory maps with equal major version number are
 * compatible) */
#define MCU_MEM_MAP_VERSION 0x0200U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U


/* ----------------------------------------------------------------------------
   -- Interrupt vector numbers
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 46                 /**< Number of interrupts in the Vector table */

typedef enum IRQn {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = -5,               /**< SysIRQ, Non Maskable Interrupt */
  Software_IRQn                = -4,               /**< Software triggered Interrupt */
  RtosTimer0_IRQn              = -3,               /**< Internal RTOS Timer0 Interrupt */
  RtosTimer1_IRQn              = -2,               /**< Internal RTOS Timer1 Interrupt */
  Profiling_IRQn               = -1,               /**< Profiling Interrupt */

  /* Device specific interrupts */
  FLEXCOMM0_IRQn               = 0,                /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S) */
  FLEXCOMM1_IRQn               = 1,                /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S) */
  FLEXCOMM2_IRQn               = 2,                /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S) */
  FLEXCOMM3_IRQn               = 3,                /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S) */
  FLEXCOMM4_IRQn               = 4,                /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S) */
  FLEXCOMM5_IRQn               = 5,                /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S) */
  FLEXCOMM6_IRQn               = 6,                /**< Flexcomm Interface 6 (USART, SPI, I2C, I3S) */
  FLEXCOMM7_IRQn               = 7,                /**< Flexcomm Interface 7 (USART, SPI, I2C, I4S) */
  FLEXCOMM14_IRQn              = 8,                /**< Flexcomm Interface 14 (USART, SPI, I2C, I5S) */
  FLEXCOMM16_IRQn              = 9,                /**< Flexcomm Interface 16 (USART, SPI, I2C, I6S) */
  PIN_INT0_IRQn                = 10,               /**< Pin interrupt 0 or pattern match engine slice 0 int */
  PIN_INT1_IRQn                = 11,               /**< Pin interrupt 1 or pattern match engine slice 1 int */
  PIN_INT2_IRQn                = 12,               /**< Pin interrupt 2 or pattern match engine slice 2 int */
  PIN_INT3_IRQn                = 13,               /**< Pin interrupt 3 or pattern match engine slice 3 int */
  PIN_INT4_IRQn                = 14,               /**< Pin interrupt 4 or pattern match engine slice 4 int */
  PIN_INT5_IRQn                = 15,               /**< Pin interrupt 5 or pattern match engine slice 5 int */
  PIN_INT6_IRQn                = 16,               /**< Pin interrupt 6 or pattern match engine slice 6 int */
  PIN_INT7_IRQn                = 17,               /**< Pin interrupt 7 or pattern match engine slice 7 int */
  GPIO_INTA_IRQn               = 18,               /**< GPIO interrupt A */
  GPIO_INTB_IRQn               = 19,               /**< GPIO interrupt B */
  WDT1_IRQn                    = 20,               /**< Windowed watchdog timer 1 */
  DMA0_IRQn                    = 21,               /**< DMA controller 0 (secure or CM33 DMA) */
  DMA1_IRQn                    = 22,               /**< DMA controller 1 (non-secure or DSP DMA) */
  MU_B_IRQn                    = 23,               /**< Messaging Unit interrupt */
  UTICK0_IRQn                  = 24,               /**< Micro-tick Timer */
  MRT0_IRQn                    = 25,               /**< Multi-Rate Timer */
  OS_EVENT_IRQn                = 26,               /**< OS event timer */
  CTIMER0_IRQn                 = 27,               /**< Standard counter/timer CTIMER0 */
  CTIMER1_IRQn                 = 28,               /**< Standard counter/timer CTIMER1 */
  CTIMER2_IRQn                 = 29,               /**< Standard counter/timer CTIMER2 */
  CTIMER3_IRQn                 = 30,               /**< Standard counter/timer CTIMER3 */
  CTIMER4_IRQn                 = 31,               /**< Standard counter/timer CTIMER4 */
  RTC_IRQn                     = 32,               /**< RTC alarm and wake-up */
  I3C0_IRQn                    = 33,               /**< I3C interface 0 */
  I3C1_IRQn                    = 34,               /**< I3C interface 1 */
  DMIC0_IRQn                   = 35,               /**< Digital microphone and DMIC subsystem */
  HWVAD_IRQn                   = 36,               /**< Hardware Voice Activity Detector */
  LCDIF_IRQn                   = 37,               /**< Liquid Crystal Display Interface interrupt */
  GPU_IRQn                     = 38,               /**< Graphics Processor Unit interrupt */
  SMARTDMA_IRQn                = 39,               /**< Smart DMA Controller interrupt */
  FLEXIO_IRQn                  = 40                /**< Flexible IO interrupt */
} IRQn_Type;

/*!
 * @}
 */ /* end of group Interrupt_vector_numbers */

#include "core_dsp.h"                  /* Core Peripheral Access Layer */
#include "system_MIMXRT595S_dsp.h"     /* Device specific configuration file */

/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__XCC__)
  /* anonymous unions are enabled by default */
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- ADC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 * @{
 */

/** ADC - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[8];
  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
       uint8_t RESERVED_1[12];
  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
  __IO uint32_t TSTAT;                             /**< Trigger Status Register, offset: 0x38 */
       uint8_t RESERVED_2[100];
  __IO uint32_t TCTRL[16];                         /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */
  __IO uint32_t FCTRL[2];                          /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */
       uint8_t RESERVED_3[24];
  struct {                                         /* offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
  } CMD[15];
       uint8_t RESERVED_4[136];
  __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_5[240];
  __I  uint32_t RESFIFO[2];                        /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */
} ADC_Type;

/* ----------------------------------------------------------------------------
   -- ADC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ADC_Register_Masks ADC Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define ADC_VERID_RES_MASK                       (0x1U)
#define ADC_VERID_RES_SHIFT                      (0U)
/*! RES - Resolution
 *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
 *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
 */
#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
#define ADC_VERID_DIFFEN_MASK                    (0x2U)
#define ADC_VERID_DIFFEN_SHIFT                   (1U)
/*! DIFFEN - Differential Supported
 *  0b0..Differential operation not supported.
 *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
 */
#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
#define ADC_VERID_MVI_MASK                       (0x8U)
#define ADC_VERID_MVI_SHIFT                      (3U)
/*! MVI - Multi Vref Implemented
 *  0b0..Single voltage reference high (VREFH) input supported.
 *  0b1..Multiple voltage reference high (VREFH) inputs supported.
 */
#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
#define ADC_VERID_CSW_MASK                       (0x70U)
#define ADC_VERID_CSW_SHIFT                      (4U)
/*! CSW - Channel Scale Width
 *  0b000..Channel scaling not supported.
 *  0b001..Channel scaling supported. 1-bit CSCALE control field.
 *  0b110..Channel scaling supported. 6-bit CSCALE control field.
 */
#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
 *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
 *  0b1..Range control required. CFG[VREF1RNG] is implemented.
 */
#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
#define ADC_VERID_IADCKI_MASK                    (0x200U)
#define ADC_VERID_IADCKI_SHIFT                   (9U)
/*! IADCKI - Internal ADC Clock implemented
 *  0b0..Internal clock source not implemented.
 *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
 */
#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
#define ADC_VERID_CALOFSI_MASK                   (0x400U)
#define ADC_VERID_CALOFSI_SHIFT                  (10U)
/*! CALOFSI - Calibration Function Implemented
 *  0b0..Calibration Not Implemented.
 *  0b1..Calibration Implemented.
 */
#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
#define ADC_VERID_NUM_SEC_MASK                   (0x800U)
#define ADC_VERID_NUM_SEC_SHIFT                  (11U)
/*! NUM_SEC - Number of Single Ended Outputs Supported
 *  0b0..This design supports one single ended conversion at a time.
 *  0b1..This design supports two simultanious single ended conversions.
 */
#define ADC_VERID_NUM_SEC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)
#define ADC_VERID_NUM_FIFO_MASK                  (0x7000U)
#define ADC_VERID_NUM_FIFO_SHIFT                 (12U)
/*! NUM_FIFO - Number of FIFOs
 *  0b000..N/A
 *  0b001..This design supports one result FIFO.
 *  0b010..This design supports two result FIFOs.
 *  0b011..This design supports three result FIFOs.
 *  0b100..This design supports four result FIFOs.
 */
#define ADC_VERID_NUM_FIFO(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)
#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT                    (16U)
/*! MINOR - Minor Version Number
 */
#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT                    (24U)
/*! MAJOR - Major Version Number
 */
#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
/*! TRIG_NUM - Trigger Number
 */
#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
/*! FIFOSIZE - Result FIFO Depth
 *  0b00000001..Result FIFO depth = 1 dataword.
 *  0b00000100..Result FIFO depth = 4 datawords.
 *  0b00001000..Result FIFO depth = 8 datawords.
 *  0b00010000..Result FIFO depth = 16 datawords.
 *  0b00100000..Result FIFO depth = 32 datawords.
 *  0b01000000..Result FIFO depth = 64 datawords.
 */
#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
/*! CV_NUM - Compare Value Number
 */
#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
/*! CMD_NUM - Command Buffer Number
 */
#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */

/*! @name CTRL - ADC Control Register */
/*! @{ */
#define ADC_CTRL_ADCEN_MASK                      (0x1U)
#define ADC_CTRL_ADCEN_SHIFT                     (0U)
/*! ADCEN - ADC Enable
 *  0b0..ADC is disabled.
 *  0b1..ADC is enabled.
 */
#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
#define ADC_CTRL_RST_MASK                        (0x2U)
#define ADC_CTRL_RST_SHIFT                       (1U)
/*! RST - Software Reset
 *  0b0..ADC logic is not reset.
 *  0b1..ADC logic is reset.
 */
#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
#define ADC_CTRL_DOZEN_MASK                      (0x4U)
#define ADC_CTRL_DOZEN_SHIFT                     (2U)
/*! DOZEN - Doze Enable
 *  0b0..ADC is enabled in Doze mode.
 *  0b1..ADC is disabled in Doze mode.
 */
#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
#define ADC_CTRL_RSTFIFO0_MASK                   (0x100U)
#define ADC_CTRL_RSTFIFO0_SHIFT                  (8U)
/*! RSTFIFO0 - Reset FIFO 0
 *  0b0..No effect.
 *  0b1..FIFO 0 is reset.
 */
#define ADC_CTRL_RSTFIFO0(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)
#define ADC_CTRL_RSTFIFO1_MASK                   (0x200U)
#define ADC_CTRL_RSTFIFO1_SHIFT                  (9U)
/*! RSTFIFO1 - Reset FIFO 1
 *  0b0..No effect.
 *  0b1..FIFO 1 is reset.
 */
#define ADC_CTRL_RSTFIFO1(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)
/*! @} */

/*! @name STAT - ADC Status Register */
/*! @{ */
#define ADC_STAT_RDY0_MASK                       (0x1U)
#define ADC_STAT_RDY0_SHIFT                      (0U)
/*! RDY0 - Result FIFO 0 Ready Flag
 *  0b0..Result FIFO 0 data level not above watermark level.
 *  0b1..Result FIFO 0 holding data above watermark level.
 */
#define ADC_STAT_RDY0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)
#define ADC_STAT_FOF0_MASK                       (0x2U)
#define ADC_STAT_FOF0_SHIFT                      (1U)
/*! FOF0 - Result FIFO 0 Overflow Flag
 *  0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)
#define ADC_STAT_RDY1_MASK                       (0x4U)
#define ADC_STAT_RDY1_SHIFT                      (2U)
/*! RDY1 - Result FIFO1 Ready Flag
 *  0b0..Result FIFO1 data level not above watermark level.
 *  0b1..Result FIFO1 holding data above watermark level.
 */
#define ADC_STAT_RDY1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)
#define ADC_STAT_FOF1_MASK                       (0x8U)
#define ADC_STAT_FOF1_SHIFT                      (3U)
/*! FOF1 - Result FIFO1 Overflow Flag
 *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_STAT_FOF1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)
#define ADC_STAT_TEXC_INT_MASK                   (0x100U)
#define ADC_STAT_TEXC_INT_SHIFT                  (8U)
/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception
 *  0b0..No trigger exceptions have occurred.
 *  0b1..A trigger exception has occurred and is pending acknowledgement.
 */
#define ADC_STAT_TEXC_INT(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)
#define ADC_STAT_TCOMP_INT_MASK                  (0x200U)
#define ADC_STAT_TCOMP_INT_SHIFT                 (9U)
/*! TCOMP_INT - Interrupt Flag For Trigger Completion
 *  0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.
 *  0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.
 */
#define ADC_STAT_TCOMP_INT(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)
#define ADC_STAT_ADC_ACTIVE_MASK                 (0x800U)
#define ADC_STAT_ADC_ACTIVE_SHIFT                (11U)
/*! ADC_ACTIVE - ADC Active
 *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
 *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
 */
#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
#define ADC_STAT_TRGACT_MASK                     (0xF0000U)
#define ADC_STAT_TRGACT_SHIFT                    (16U)
/*! TRGACT - Trigger Active
 *  0b0000..Command (sequence) associated with Trigger 0 currently being executed.
 *  0b0001..Command (sequence) associated with Trigger 1 currently being executed.
 *  0b0010..Command (sequence) associated with Trigger 2 currently being executed.
 *  0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.
 */
#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT                    (24U)
/*! CMDACT - Command Active
 *  0b0000..No command is currently in progress.
 *  0b0001..Command 1 currently being executed.
 *  0b0010..Command 2 currently being executed.
 *  0b0011-0b1111..Associated command number is currently being executed.
 */
#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */

/*! @name IE - Interrupt Enable Register */
/*! @{ */
#define ADC_IE_FWMIE0_MASK                       (0x1U)
#define ADC_IE_FWMIE0_SHIFT                      (0U)
/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
 *  0b0..FIFO 0 watermark interrupts are not enabled.
 *  0b1..FIFO 0 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)
#define ADC_IE_FOFIE0_MASK                       (0x2U)
#define ADC_IE_FOFIE0_SHIFT                      (1U)
/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
 *  0b0..FIFO 0 overflow interrupts are not enabled.
 *  0b1..FIFO 0 overflow interrupts are enabled.
 */
#define ADC_IE_FOFIE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)
#define ADC_IE_FWMIE1_MASK                       (0x4U)
#define ADC_IE_FWMIE1_SHIFT                      (2U)
/*! FWMIE1 - FIFO1 Watermark Interrupt Enable
 *  0b0..FIFO1 watermark interrupts are not enabled.
 *  0b1..FIFO1 watermark interrupts are enabled.
 */
#define ADC_IE_FWMIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)
#define ADC_IE_FOFIE1_MASK                       (0x8U)
#define ADC_IE_FOFIE1_SHIFT                      (3U)
/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
 *  0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.
 *  0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.
 */
#define ADC_IE_FOFIE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)
#define ADC_IE_TEXC_IE_MASK                      (0x100U)
#define ADC_IE_TEXC_IE_SHIFT                     (8U)
/*! TEXC_IE - Trigger Exception Interrupt Enable
 *  0b0..Trigger exception interrupts are disabled.
 *  0b1..Trigger exception interrupts are enabled.
 */
#define ADC_IE_TEXC_IE(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)
#define ADC_IE_TCOMP_IE_MASK                     (0xFFFF0000U)
#define ADC_IE_TCOMP_IE_SHIFT                    (16U)
/*! TCOMP_IE - Trigger Completion Interrupt Enable
 *  0b0000000000000000..Trigger completion interrupts are disabled.
 *  0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.
 *  0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.
 *  0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.
 *  0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.
 */
#define ADC_IE_TCOMP_IE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)
/*! @} */

/*! @name DE - DMA Enable Register */
/*! @{ */
#define ADC_DE_FWMDE0_MASK                       (0x1U)
#define ADC_DE_FWMDE0_SHIFT                      (0U)
/*! FWMDE0 - FIFO 0 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)
#define ADC_DE_FWMDE1_MASK                       (0x2U)
#define ADC_DE_FWMDE1_SHIFT                      (1U)
/*! FWMDE1 - FIFO1 Watermark DMA Enable
 *  0b0..DMA request disabled.
 *  0b1..DMA request enabled.
 */
#define ADC_DE_FWMDE1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)
/*! @} */

/*! @name CFG - ADC Configuration Register */
/*! @{ */
#define ADC_CFG_TPRICTRL_MASK                    (0x3U)
#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
/*! TPRICTRL - ADC trigger priority control
 *  0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted
 *        and the new command specified by the trigger is started.
 *  0b01..If a higher priority trigger is received during command processing, the current command is stopped after
 *        after completing the current conversion. If averaging is enabled, the averaging loop will be completed.
 *        However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.
 *  0b10..If a higher priority trigger is received during command processing, the current command will be
 *        completed (averaging, looping, compare) before servicing the higher priority trigger.
 *  0b11..RESERVED
 */
#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
#define ADC_CFG_PWRSEL_MASK                      (0x30U)
#define ADC_CFG_PWRSEL_SHIFT                     (4U)
/*! PWRSEL - Power Configuration Select
 *  0b00..Lowest power setting.
 *  0b01..Higher power setting than 0b0.
 *  0b10..Higher power setting than 0b1.
 *  0b11..Highest power setting.
 */
#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
#define ADC_CFG_REFSEL_MASK                      (0xC0U)
#define ADC_CFG_REFSEL_SHIFT                     (6U)
/*! REFSEL - Voltage Reference Selection
 *  0b00..(Default) Option 1 setting.
 *  0b01..Option 2 setting.
 *  0b10..Option 3 setting.
 *  0b11..Reserved
 */
#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define ADC_CFG_TRES_MASK                        (0x100U)
#define ADC_CFG_TRES_SHIFT                       (8U)
/*! TRES - Trigger Resume Enable
 *  0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
 */
#define ADC_CFG_TRES(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)
#define ADC_CFG_TCMDRES_MASK                     (0x200U)
#define ADC_CFG_TCMDRES_SHIFT                    (9U)
/*! TCMDRES - Trigger Command Resume
 *  0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted.
 *  0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
 */
#define ADC_CFG_TCMDRES(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)
#define ADC_CFG_HPT_EXDI_MASK                    (0x400U)
#define ADC_CFG_HPT_EXDI_SHIFT                   (10U)
/*! HPT_EXDI - High Priority Trigger Exception Disable
 *  0b0..High priority trigger exceptions are enabled.
 *  0b1..High priority trigger exceptions are disabled.
 */
#define ADC_CFG_HPT_EXDI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)
#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT                      (16U)
/*! PUDLY - Power Up Delay
 */
#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
#define ADC_CFG_PWREN_MASK                       (0x10000000U)
#define ADC_CFG_PWREN_SHIFT                      (28U)
/*! PWREN - ADC Analog Pre-Enable
 *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
 *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
 *       of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN
 *       is set, and any detected trigger does not begin ADC operation until the power up delay time has passed.
 *       After this initial delay expires the analog will remain pre-enabled, and no additional delays will be
 *       executed.
 */
#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */

/*! @name PAUSE - ADC Pause Register */
/*! @{ */
#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
/*! PAUSEDLY - Pause Delay
 */
#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
/*! PAUSEEN - PAUSE Option Enable
 *  0b0..Pause operation disabled
 *  0b1..Pause operation enabled
 */
#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */

/*! @name SWTRIG - Software Trigger Register */
/*! @{ */
#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
/*! SWT0 - Software trigger 0 event
 *  0b0..No trigger 0 event generated.
 *  0b1..Trigger 0 event generated.
 */
#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
/*! SWT1 - Software trigger 1 event
 *  0b0..No trigger 1 event generated.
 *  0b1..Trigger 1 event generated.
 */
#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
/*! SWT2 - Software trigger 2 event
 *  0b0..No trigger 2 event generated.
 *  0b1..Trigger 2 event generated.
 */
#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
/*! SWT3 - Software trigger 3 event
 *  0b0..No trigger 3 event generated.
 *  0b1..Trigger 3 event generated.
 */
#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
#define ADC_SWTRIG_SWT4_MASK                     (0x10U)
#define ADC_SWTRIG_SWT4_SHIFT                    (4U)
/*! SWT4 - Software trigger 4 event
 *  0b0..No trigger 4 event generated.
 *  0b1..Trigger 4 event generated.
 */
#define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
#define ADC_SWTRIG_SWT5_MASK                     (0x20U)
#define ADC_SWTRIG_SWT5_SHIFT                    (5U)
/*! SWT5 - Software trigger 5 event
 *  0b0..No trigger 5 event generated.
 *  0b1..Trigger 5 event generated.
 */
#define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
#define ADC_SWTRIG_SWT6_MASK                     (0x40U)
#define ADC_SWTRIG_SWT6_SHIFT                    (6U)
/*! SWT6 - Software trigger 6 event
 *  0b0..No trigger 6 event generated.
 *  0b1..Trigger 6 event generated.
 */
#define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
#define ADC_SWTRIG_SWT7_MASK                     (0x80U)
#define ADC_SWTRIG_SWT7_SHIFT                    (7U)
/*! SWT7 - Software trigger 7 event
 *  0b0..No trigger 7 event generated.
 *  0b1..Trigger 7 event generated.
 */
#define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
#define ADC_SWTRIG_SWT8_MASK                     (0x100U)
#define ADC_SWTRIG_SWT8_SHIFT                    (8U)
/*! SWT8 - Software trigger 8 event
 *  0b0..No trigger 8 event generated.
 *  0b1..Trigger 8 event generated.
 */
#define ADC_SWTRIG_SWT8(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)
#define ADC_SWTRIG_SWT9_MASK                     (0x200U)
#define ADC_SWTRIG_SWT9_SHIFT                    (9U)
/*! SWT9 - Software trigger 9 event
 *  0b0..No trigger 9 event generated.
 *  0b1..Trigger 9 event generated.
 */
#define ADC_SWTRIG_SWT9(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)
#define ADC_SWTRIG_SWT10_MASK                    (0x400U)
#define ADC_SWTRIG_SWT10_SHIFT                   (10U)
/*! SWT10 - Software trigger 10 event
 *  0b0..No trigger 10 event generated.
 *  0b1..Trigger 10 event generated.
 */
#define ADC_SWTRIG_SWT10(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)
#define ADC_SWTRIG_SWT11_MASK                    (0x800U)
#define ADC_SWTRIG_SWT11_SHIFT                   (11U)
/*! SWT11 - Software trigger 11 event
 *  0b0..No trigger 11 event generated.
 *  0b1..Trigger 11 event generated.
 */
#define ADC_SWTRIG_SWT11(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)
#define ADC_SWTRIG_SWT12_MASK                    (0x1000U)
#define ADC_SWTRIG_SWT12_SHIFT                   (12U)
/*! SWT12 - Software trigger 12 event
 *  0b0..No trigger 12 event generated.
 *  0b1..Trigger 12 event generated.
 */
#define ADC_SWTRIG_SWT12(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)
#define ADC_SWTRIG_SWT13_MASK                    (0x2000U)
#define ADC_SWTRIG_SWT13_SHIFT                   (13U)
/*! SWT13 - Software trigger 13 event
 *  0b0..No trigger 13 event generated.
 *  0b1..Trigger 13 event generated.
 */
#define ADC_SWTRIG_SWT13(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)
#define ADC_SWTRIG_SWT14_MASK                    (0x4000U)
#define ADC_SWTRIG_SWT14_SHIFT                   (14U)
/*! SWT14 - Software trigger 14 event
 *  0b0..No trigger 14 event generated.
 *  0b1..Trigger 14 event generated.
 */
#define ADC_SWTRIG_SWT14(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)
#define ADC_SWTRIG_SWT15_MASK                    (0x8000U)
#define ADC_SWTRIG_SWT15_SHIFT                   (15U)
/*! SWT15 - Software trigger 15 event
 *  0b0..No trigger 15 event generated.
 *  0b1..Trigger 15 event generated.
 */
#define ADC_SWTRIG_SWT15(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)
/*! @} */

/*! @name TSTAT - Trigger Status Register */
/*! @{ */
#define ADC_TSTAT_TEXC_NUM_MASK                  (0xFFFFU)
#define ADC_TSTAT_TEXC_NUM_SHIFT                 (0U)
/*! TEXC_NUM - Trigger Exception Number
 *  0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.
 *  0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.
 *  0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.
 *  0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.
 *  0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.
 */
#define ADC_TSTAT_TEXC_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)
#define ADC_TSTAT_TCOMP_FLAG_MASK                (0xFFFF0000U)
#define ADC_TSTAT_TCOMP_FLAG_SHIFT               (16U)
/*! TCOMP_FLAG - Trigger Completion Flag
 *  0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.
 *  0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.
 *  0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.
 *  0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.
 *  0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.
 */
#define ADC_TSTAT_TCOMP_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)
/*! @} */

/*! @name TCTRL - Trigger Control Register */
/*! @{ */
#define ADC_TCTRL_HTEN_MASK                      (0x1U)
#define ADC_TCTRL_HTEN_SHIFT                     (0U)
/*! HTEN - Trigger enable
 *  0b0..Hardware trigger source disabled
 *  0b1..Hardware trigger source enabled
 */
#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
#define ADC_TCTRL_FIFO_SEL_A_MASK                (0x2U)
#define ADC_TCTRL_FIFO_SEL_A_SHIFT               (1U)
/*! FIFO_SEL_A - SAR Result Destination For Channel A
 *  0b0..Result written to FIFO 0
 *  0b1..Result written to FIFO 1
 */
#define ADC_TCTRL_FIFO_SEL_A(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)
#define ADC_TCTRL_TPRI_MASK                      (0xF00U)
#define ADC_TCTRL_TPRI_SHIFT                     (8U)
/*! TPRI - Trigger priority setting
 *  0b0000..Set to highest priority, Level 1
 *  0b0001-0b1110..Set to corresponding priority level
 *  0b1111..Set to lowest priority, Level 16
 */
#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
#define ADC_TCTRL_RSYNC_MASK                     (0x8000U)
#define ADC_TCTRL_RSYNC_SHIFT                    (15U)
/*! RSYNC - Trigger Resync
 */
#define ADC_TCTRL_RSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)
#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT                     (16U)
/*! TDLY - Trigger delay select
 */
#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT                     (24U)
/*! TCMD - Trigger command select
 *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
 *  0b0001..CMD1 is executed
 *  0b0010-0b1110..Corresponding CMD is executed
 *  0b1111..CMD15 is executed
 */
#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */

/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT                          (16U)

/*! @name FCTRL - FIFO Control Register */
/*! @{ */
#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
/*! FCOUNT - Result FIFO counter
 */
#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
/*! FWMARK - Watermark level selection
 */
#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */

/* The count of ADC_FCTRL */
#define ADC_FCTRL_COUNT                          (2U)

/*! @name CMDL - ADC Command Low Buffer Register */
/*! @{ */
#define ADC_CMDL_ADCH_MASK                       (0x1FU)
#define ADC_CMDL_ADCH_SHIFT                      (0U)
/*! ADCH - Input channel select
 *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
 *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
 *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
 *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
 *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
 *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
 *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
 */
#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
#define ADC_CMDL_ABSEL_MASK                      (0x20U)
#define ADC_CMDL_ABSEL_SHIFT                     (5U)
/*! ABSEL - A-side vs. B-side Select
 *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
 *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
 */
#define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
#define ADC_CMDL_DIFF_MASK                       (0x40U)
#define ADC_CMDL_DIFF_SHIFT                      (6U)
/*! DIFF - Differential Mode Enable
 *  0b0..Single-ended mode.
 *  0b1..Differential mode.
 */
#define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
#define ADC_CMDL_CSCALE_MASK                     (0x2000U)
#define ADC_CMDL_CSCALE_SHIFT                    (13U)
/*! CSCALE - Channel Scale
 *  0b0..Scale selected analog channel (Factor of 30/64)
 *  0b1..(Default) Full scale (Factor of 1)
 */
#define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
/*! @} */

/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT                           (15U)

/*! @name CMDH - ADC Command High Buffer Register */
/*! @{ */
#define ADC_CMDH_CMPEN_MASK                      (0x3U)
#define ADC_CMDH_CMPEN_SHIFT                     (0U)
/*! CMPEN - Compare Function Enable
 *  0b00..Compare disabled.
 *  0b01..Reserved
 *  0b10..Compare enabled. Store on true.
 *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
 */
#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
#define ADC_CMDH_WAIT_TRIG_MASK                  (0x4U)
#define ADC_CMDH_WAIT_TRIG_SHIFT                 (2U)
/*! WAIT_TRIG - Wait for trigger assertion before execution.
 *  0b0..This command will be automatically executed.
 *  0b1..The active trigger must be asserted again before executing this command.
 */
#define ADC_CMDH_WAIT_TRIG(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)
#define ADC_CMDH_LWI_MASK                        (0x80U)
#define ADC_CMDH_LWI_SHIFT                       (7U)
/*! LWI - Loop with Increment
 *  0b0..Auto channel increment disabled
 *  0b1..Auto channel increment enabled
 */
#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
#define ADC_CMDH_STS_MASK                        (0x700U)
#define ADC_CMDH_STS_SHIFT                       (8U)
/*! STS - Sample Time Select
 *  0b000..Minimum sample time of 3 ADCK cycles.
 *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
 *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
 *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
 *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
 *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
 *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
 *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
 */
#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
#define ADC_CMDH_AVGS_MASK                       (0x7000U)
#define ADC_CMDH_AVGS_SHIFT                      (12U)
/*! AVGS - Hardware Average Select
 *  0b000..Single conversion.
 *  0b001..2 conversions averaged.
 *  0b010..4 conversions averaged.
 *  0b011..8 conversions averaged.
 *  0b100..16 conversions averaged.
 *  0b101..32 conversions averaged.
 *  0b110..64 conversions averaged.
 *  0b111..128 conversions averaged.
 */
#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT                      (16U)
/*! LOOP - Loop Count Select
 *  0b0000..Looping not enabled. Command executes 1 time.
 *  0b0001..Loop 1 time. Command executes 2 times.
 *  0b0010..Loop 2 times. Command executes 3 times.
 *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
 *  0b1111..Loop 15 times. Command executes 16 times.
 */
#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT                      (24U)
/*! NEXT - Next Command Select
 *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
 *          trigger pending, begin command associated with lower priority trigger.
 *  0b0001..Select CMD1 command buffer register as next command.
 *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
 *  0b1111..Select CMD15 command buffer register as next command.
 */
#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */

/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT                           (15U)

/*! @name CV - Compare Value Register */
/*! @{ */
#define ADC_CV_CVL_MASK                          (0xFFFFU)
#define ADC_CV_CVL_SHIFT                         (0U)
/*! CVL - Compare Value Low.
 */
#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT                         (16U)
/*! CVH - Compare Value High.
 */
#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */

/* The count of ADC_CV */
#define ADC_CV_COUNT                             (4U)

/*! @name RESFIFO - ADC Data Result FIFO Register */
/*! @{ */
#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT                      (0U)
/*! D - Data result
 */
#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
#define ADC_RESFIFO_TSRC_MASK                    (0xF0000U)
#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
/*! TSRC - Trigger Source
 *  0b0000..Trigger source 0 initiated this conversion.
 *  0b0001..Trigger source 1 initiated this conversion.
 *  0b0010-0b1110..Corresponding trigger source initiated this conversion.
 *  0b1111..Trigger source 15 initiated this conversion.
 */
#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
/*! LOOPCNT - Loop count value
 *  0b0000..Result is from initial conversion in command.
 *  0b0001..Result is from second conversion in command.
 *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
 *  0b1111..Result is from 16th conversion in command.
 */
#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
/*! CMDSRC - Command Buffer Source
 *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
 *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
 *  0b0001..CMD1 buffer used as control settings for this conversion.
 *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
 *  0b1111..CMD15 buffer used as control settings for this conversion.
 */
#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT                  (31U)
/*! VALID - FIFO entry is valid
 *  0b0..FIFO is empty. Discard any read from RESFIFO.
 *  0b1..FIFO record read from RESFIFO is valid.
 */
#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */

/* The count of ADC_RESFIFO */
#define ADC_RESFIFO_COUNT                        (2U)


/*!
 * @}
 */ /* end of group ADC_Register_Masks */


/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE                                (0x4013A000u)
/** Peripheral ADC0 base pointer */
#define ADC0                                     ((ADC_Type *)ADC0_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS                           { ADC0_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS                            { ADC0 }

/*!
 * @}
 */ /* end of group ADC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AIPS Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
 * @{
 */

/** AIPS - Register Layout Typedef */
typedef struct {
  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
       uint8_t RESERVED_0[60];
  __IO uint32_t OPACRA;                            /**< Off-Platform Peripheral Access Control Register, offset: 0x40 */
  __IO uint32_t OPACRB;                            /**< Off-Platform Peripheral Access Control Register, offset: 0x44 */
} AIPS_Type;

/* ----------------------------------------------------------------------------
   -- AIPS Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AIPS_Register_Masks AIPS Register Masks
 * @{
 */

/*! @name MPRA - Master Privilege Register A */
/*! @{ */
#define AIPS_MPRA_MPL7_MASK                      (0x1U)
#define AIPS_MPRA_MPL7_SHIFT                     (0U)
/*! MPL7 - Master 7 Privilege Level
 *  0b0..Accesses from this master are forced to user-mode.
 *  0b1..Accesses from this master are not forced to user-mode.
 */
#define AIPS_MPRA_MPL7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL7_SHIFT)) & AIPS_MPRA_MPL7_MASK)
#define AIPS_MPRA_MTW7_MASK                      (0x2U)
#define AIPS_MPRA_MTW7_SHIFT                     (1U)
/*! MTW7 - Master 7 Trusted for Writes
 *  0b0..This master is not trusted for write accesses.
 *  0b1..This master is trusted for write accesses.
 */
#define AIPS_MPRA_MTW7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW7_SHIFT)) & AIPS_MPRA_MTW7_MASK)
#define AIPS_MPRA_MTR7_MASK                      (0x4U)
#define AIPS_MPRA_MTR7_SHIFT                     (2U)
/*! MTR7 - Master 7 Trusted for Read
 *  0b0..This master is not trusted for read accesses.
 *  0b1..This master is trusted for read accesses.
 */
#define AIPS_MPRA_MTR7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR7_SHIFT)) & AIPS_MPRA_MTR7_MASK)
#define AIPS_MPRA_MPL5_MASK                      (0x100U)
#define AIPS_MPRA_MPL5_SHIFT                     (8U)
/*! MPL5 - Master 5 Privilege Level
 *  0b0..Accesses from this master are forced to user-mode.
 *  0b1..Accesses from this master are not forced to user-mode.
 */
#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
#define AIPS_MPRA_MTW5_MASK                      (0x200U)
#define AIPS_MPRA_MTW5_SHIFT                     (9U)
/*! MTW5 - Master 5 Trusted For Writes
 *  0b0..This master is not trusted for write accesses.
 *  0b1..This master is trusted for write accesses.
 */
#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
#define AIPS_MPRA_MTR5_MASK                      (0x400U)
#define AIPS_MPRA_MTR5_SHIFT                     (10U)
/*! MTR5 - Master 5 Trusted For Read
 *  0b0..This master is not trusted for read accesses.
 *  0b1..This master is trusted for read accesses.
 */
#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
#define AIPS_MPRA_MPL4_MASK                      (0x1000U)
#define AIPS_MPRA_MPL4_SHIFT                     (12U)
/*! MPL4 - Master 4 Privilege Level
 *  0b0..Accesses from this master are forced to user-mode.
 *  0b1..Accesses from this master are not forced to user-mode.
 */
#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
#define AIPS_MPRA_MTW4_MASK                      (0x2000U)
#define AIPS_MPRA_MTW4_SHIFT                     (13U)
/*! MTW4 - Master 4 Trusted For Writes
 *  0b0..This master is not trusted for write accesses.
 *  0b1..This master is trusted for write accesses.
 */
#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
#define AIPS_MPRA_MTR4_MASK                      (0x4000U)
#define AIPS_MPRA_MTR4_SHIFT                     (14U)
/*! MTR4 - Master 4 Trusted For Read
 *  0b0..This master is not trusted for read accesses.
 *  0b1..This master is trusted for read accesses.
 */
#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
#define AIPS_MPRA_MPL3_MASK                      (0x10000U)
#define AIPS_MPRA_MPL3_SHIFT                     (16U)
/*! MPL3 - Master 3 Privilege Level
 *  0b0..Accesses from this master are forced to user-mode.
 *  0b1..Accesses from this master are not forced to user-mode.
 */
#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
#define AIPS_MPRA_MTW3_MASK                      (0x20000U)
#define AIPS_MPRA_MTW3_SHIFT                     (17U)
/*! MTW3 - Master 3 Trusted For Writes
 *  0b0..This master is not trusted for write accesses.
 *  0b1..This master is trusted for write accesses.
 */
#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
#define AIPS_MPRA_MTR3_MASK                      (0x40000U)
#define AIPS_MPRA_MTR3_SHIFT                     (18U)
/*! MTR3 - Master 3 Trusted For Read
 *  0b0..This master is not trusted for read accesses.
 *  0b1..This master is trusted for read accesses.
 */
#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
#define AIPS_MPRA_MPL1_MASK                      (0x1000000U)
#define AIPS_MPRA_MPL1_SHIFT                     (24U)
/*! MPL1 - Master 1 Privilege Level
 *  0b0..Accesses from this master are forced to user-mode.
 *  0b1..Accesses from this master are not forced to user-mode.
 */
#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
#define AIPS_MPRA_MTW1_MASK                      (0x2000000U)
#define AIPS_MPRA_MTW1_SHIFT                     (25U)
/*! MTW1 - Master 1 Trusted for Writes
 *  0b0..This master is not trusted for write accesses.
 *  0b1..This master is trusted for write accesses.
 */
#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
#define AIPS_MPRA_MTR1_MASK                      (0x4000000U)
#define AIPS_MPRA_MTR1_SHIFT                     (26U)
/*! MTR1 - Master 1 Trusted for Read
 *  0b0..This master is not trusted for read accesses.
 *  0b1..This master is trusted for read accesses.
 */
#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
/*! @} */

/*! @name OPACRA - Off-Platform Peripheral Access Control Register */
/*! @{ */
#define AIPS_OPACRA_TP7_MASK                     (0x1U)
#define AIPS_OPACRA_TP7_SHIFT                    (0U)
/*! TP7 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP7(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP7_SHIFT)) & AIPS_OPACRA_TP7_MASK)
#define AIPS_OPACRA_WP7_MASK                     (0x2U)
#define AIPS_OPACRA_WP7_SHIFT                    (1U)
/*! WP7 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP7(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP7_SHIFT)) & AIPS_OPACRA_WP7_MASK)
#define AIPS_OPACRA_SP7_MASK                     (0x4U)
#define AIPS_OPACRA_SP7_SHIFT                    (2U)
/*! SP7 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP7(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP7_SHIFT)) & AIPS_OPACRA_SP7_MASK)
#define AIPS_OPACRA_TP6_MASK                     (0x10U)
#define AIPS_OPACRA_TP6_SHIFT                    (4U)
/*! TP6 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP6(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP6_SHIFT)) & AIPS_OPACRA_TP6_MASK)
#define AIPS_OPACRA_WP6_MASK                     (0x20U)
#define AIPS_OPACRA_WP6_SHIFT                    (5U)
/*! WP6 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP6(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP6_SHIFT)) & AIPS_OPACRA_WP6_MASK)
#define AIPS_OPACRA_SP6_MASK                     (0x40U)
#define AIPS_OPACRA_SP6_SHIFT                    (6U)
/*! SP6 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP6(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP6_SHIFT)) & AIPS_OPACRA_SP6_MASK)
#define AIPS_OPACRA_TP5_MASK                     (0x100U)
#define AIPS_OPACRA_TP5_SHIFT                    (8U)
/*! TP5 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP5(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP5_SHIFT)) & AIPS_OPACRA_TP5_MASK)
#define AIPS_OPACRA_WP5_MASK                     (0x200U)
#define AIPS_OPACRA_WP5_SHIFT                    (9U)
/*! WP5 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP5(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP5_SHIFT)) & AIPS_OPACRA_WP5_MASK)
#define AIPS_OPACRA_SP5_MASK                     (0x400U)
#define AIPS_OPACRA_SP5_SHIFT                    (10U)
/*! SP5 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP5(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP5_SHIFT)) & AIPS_OPACRA_SP5_MASK)
#define AIPS_OPACRA_TP4_MASK                     (0x1000U)
#define AIPS_OPACRA_TP4_SHIFT                    (12U)
/*! TP4 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP4(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP4_SHIFT)) & AIPS_OPACRA_TP4_MASK)
#define AIPS_OPACRA_WP4_MASK                     (0x2000U)
#define AIPS_OPACRA_WP4_SHIFT                    (13U)
/*! WP4 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP4(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP4_SHIFT)) & AIPS_OPACRA_WP4_MASK)
#define AIPS_OPACRA_SP4_MASK                     (0x4000U)
#define AIPS_OPACRA_SP4_SHIFT                    (14U)
/*! SP4 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP4(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP4_SHIFT)) & AIPS_OPACRA_SP4_MASK)
#define AIPS_OPACRA_TP3_MASK                     (0x10000U)
#define AIPS_OPACRA_TP3_SHIFT                    (16U)
/*! TP3 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP3(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP3_SHIFT)) & AIPS_OPACRA_TP3_MASK)
#define AIPS_OPACRA_WP3_MASK                     (0x20000U)
#define AIPS_OPACRA_WP3_SHIFT                    (17U)
/*! WP3 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP3(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP3_SHIFT)) & AIPS_OPACRA_WP3_MASK)
#define AIPS_OPACRA_SP3_MASK                     (0x40000U)
#define AIPS_OPACRA_SP3_SHIFT                    (18U)
/*! SP3 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP3(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP3_SHIFT)) & AIPS_OPACRA_SP3_MASK)
#define AIPS_OPACRA_TP2_MASK                     (0x100000U)
#define AIPS_OPACRA_TP2_SHIFT                    (20U)
/*! TP2 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP2(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP2_SHIFT)) & AIPS_OPACRA_TP2_MASK)
#define AIPS_OPACRA_WP2_MASK                     (0x200000U)
#define AIPS_OPACRA_WP2_SHIFT                    (21U)
/*! WP2 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP2(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP2_SHIFT)) & AIPS_OPACRA_WP2_MASK)
#define AIPS_OPACRA_SP2_MASK                     (0x400000U)
#define AIPS_OPACRA_SP2_SHIFT                    (22U)
/*! SP2 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP2(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP2_SHIFT)) & AIPS_OPACRA_SP2_MASK)
#define AIPS_OPACRA_TP1_MASK                     (0x1000000U)
#define AIPS_OPACRA_TP1_SHIFT                    (24U)
/*! TP1 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP1(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP1_SHIFT)) & AIPS_OPACRA_TP1_MASK)
#define AIPS_OPACRA_WP1_MASK                     (0x2000000U)
#define AIPS_OPACRA_WP1_SHIFT                    (25U)
/*! WP1 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP1(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP1_SHIFT)) & AIPS_OPACRA_WP1_MASK)
#define AIPS_OPACRA_SP1_MASK                     (0x4000000U)
#define AIPS_OPACRA_SP1_SHIFT                    (26U)
/*! SP1 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP1(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP1_SHIFT)) & AIPS_OPACRA_SP1_MASK)
#define AIPS_OPACRA_TP0_MASK                     (0x10000000U)
#define AIPS_OPACRA_TP0_SHIFT                    (28U)
/*! TP0 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRA_TP0(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_TP0_SHIFT)) & AIPS_OPACRA_TP0_MASK)
#define AIPS_OPACRA_WP0_MASK                     (0x20000000U)
#define AIPS_OPACRA_WP0_SHIFT                    (29U)
/*! WP0 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRA_WP0(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_WP0_SHIFT)) & AIPS_OPACRA_WP0_MASK)
#define AIPS_OPACRA_SP0_MASK                     (0x40000000U)
#define AIPS_OPACRA_SP0_SHIFT                    (30U)
/*! SP0 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRA_SP0(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRA_SP0_SHIFT)) & AIPS_OPACRA_SP0_MASK)
/*! @} */

/*! @name OPACRB - Off-Platform Peripheral Access Control Register */
/*! @{ */
#define AIPS_OPACRB_TP7_MASK                     (0x1U)
#define AIPS_OPACRB_TP7_SHIFT                    (0U)
/*! TP7 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRB_TP7(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_TP7_SHIFT)) & AIPS_OPACRB_TP7_MASK)
#define AIPS_OPACRB_WP7_MASK                     (0x2U)
#define AIPS_OPACRB_WP7_SHIFT                    (1U)
/*! WP7 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRB_WP7(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_WP7_SHIFT)) & AIPS_OPACRB_WP7_MASK)
#define AIPS_OPACRB_SP7_MASK                     (0x4U)
#define AIPS_OPACRB_SP7_SHIFT                    (2U)
/*! SP7 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRB_SP7(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_SP7_SHIFT)) & AIPS_OPACRB_SP7_MASK)
#define AIPS_OPACRB_TP4_MASK                     (0x1000U)
#define AIPS_OPACRB_TP4_SHIFT                    (12U)
/*! TP4 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRB_TP4(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_TP4_SHIFT)) & AIPS_OPACRB_TP4_MASK)
#define AIPS_OPACRB_WP4_MASK                     (0x2000U)
#define AIPS_OPACRB_WP4_SHIFT                    (13U)
/*! WP4 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRB_WP4(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_WP4_SHIFT)) & AIPS_OPACRB_WP4_MASK)
#define AIPS_OPACRB_SP4_MASK                     (0x4000U)
#define AIPS_OPACRB_SP4_SHIFT                    (14U)
/*! SP4 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRB_SP4(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_SP4_SHIFT)) & AIPS_OPACRB_SP4_MASK)
#define AIPS_OPACRB_TP3_MASK                     (0x10000U)
#define AIPS_OPACRB_TP3_SHIFT                    (16U)
/*! TP3 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRB_TP3(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_TP3_SHIFT)) & AIPS_OPACRB_TP3_MASK)
#define AIPS_OPACRB_WP3_MASK                     (0x20000U)
#define AIPS_OPACRB_WP3_SHIFT                    (17U)
/*! WP3 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRB_WP3(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_WP3_SHIFT)) & AIPS_OPACRB_WP3_MASK)
#define AIPS_OPACRB_SP3_MASK                     (0x40000U)
#define AIPS_OPACRB_SP3_SHIFT                    (18U)
/*! SP3 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRB_SP3(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_SP3_SHIFT)) & AIPS_OPACRB_SP3_MASK)
#define AIPS_OPACRB_TP2_MASK                     (0x100000U)
#define AIPS_OPACRB_TP2_SHIFT                    (20U)
/*! TP2 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRB_TP2(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_TP2_SHIFT)) & AIPS_OPACRB_TP2_MASK)
#define AIPS_OPACRB_WP2_MASK                     (0x200000U)
#define AIPS_OPACRB_WP2_SHIFT                    (21U)
/*! WP2 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRB_WP2(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_WP2_SHIFT)) & AIPS_OPACRB_WP2_MASK)
#define AIPS_OPACRB_SP2_MASK                     (0x400000U)
#define AIPS_OPACRB_SP2_SHIFT                    (22U)
/*! SP2 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRB_SP2(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_SP2_SHIFT)) & AIPS_OPACRB_SP2_MASK)
#define AIPS_OPACRB_TP1_MASK                     (0x1000000U)
#define AIPS_OPACRB_TP1_SHIFT                    (24U)
/*! TP1 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRB_TP1(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_TP1_SHIFT)) & AIPS_OPACRB_TP1_MASK)
#define AIPS_OPACRB_WP1_MASK                     (0x2000000U)
#define AIPS_OPACRB_WP1_SHIFT                    (25U)
/*! WP1 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRB_WP1(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_WP1_SHIFT)) & AIPS_OPACRB_WP1_MASK)
#define AIPS_OPACRB_SP1_MASK                     (0x4000000U)
#define AIPS_OPACRB_SP1_SHIFT                    (26U)
/*! SP1 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRB_SP1(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_SP1_SHIFT)) & AIPS_OPACRB_SP1_MASK)
#define AIPS_OPACRB_TP0_MASK                     (0x10000000U)
#define AIPS_OPACRB_TP0_SHIFT                    (28U)
/*! TP0 - Trusted Protect
 *  0b0..Accesses from an untrusted master are allowed.
 *  0b1..Accesses from an untrusted master are not allowed.
 */
#define AIPS_OPACRB_TP0(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_TP0_SHIFT)) & AIPS_OPACRB_TP0_MASK)
#define AIPS_OPACRB_WP0_MASK                     (0x20000000U)
#define AIPS_OPACRB_WP0_SHIFT                    (29U)
/*! WP0 - Write Protect
 *  0b0..This peripheral allows write accesses.
 *  0b1..This peripheral is write protected.
 */
#define AIPS_OPACRB_WP0(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_WP0_SHIFT)) & AIPS_OPACRB_WP0_MASK)
#define AIPS_OPACRB_SP0_MASK                     (0x40000000U)
#define AIPS_OPACRB_SP0_SHIFT                    (30U)
/*! SP0 - Supervisor Protect
 *  0b0..This peripheral does not require supervisor privilege level for accesses.
 *  0b1..This peripheral requires supervisor privilege level for accesses.
 */
#define AIPS_OPACRB_SP0(x)                       (((uint32_t)(((uint32_t)(x)) << AIPS_OPACRB_SP0_SHIFT)) & AIPS_OPACRB_SP0_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AIPS_Register_Masks */


/* AIPS - Peripheral instance base addresses */
/** Peripheral AIPS0 base address */
#define AIPS0_BASE                               (0x40110000u)
/** Peripheral AIPS0 base pointer */
#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
/** Peripheral AIPS1 base address */
#define AIPS1_BASE                               (0x40130000u)
/** Peripheral AIPS1 base pointer */
#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
/** Array initializer of AIPS peripheral base addresses */
#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
/** Array initializer of AIPS peripheral base pointers */
#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }

/*!
 * @}
 */ /* end of group AIPS_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- AXI_SWITCH Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AXI_SWITCH_Peripheral_Access_Layer AXI_SWITCH Peripheral Access Layer
 * @{
 */

/** AXI_SWITCH - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[8];
  __IO uint32_t FN_MOD_BM_ISS;                     /**< Bus Matrix Issuing Functionality Modification., offset: 0x8 */
       uint8_t RESERVED_1[24];
  __IO uint32_t FN_MOD2;                           /**< Bypass Merge, offset: 0x24 */
       uint8_t RESERVED_2[216];
  __IO uint32_t READ_QOS;                          /**< Read channel QoS value, offset: 0x100 */
  __IO uint32_t WRITE_QOS;                         /**< WRITE channel QoS value, offset: 0x104 */
  __IO uint32_t FN_MOD;                            /**< Issuing Functionality Modification, offset: 0x108 */
} AXI_SWITCH_Type;

/* ----------------------------------------------------------------------------
   -- AXI_SWITCH Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup AXI_SWITCH_Register_Masks AXI_SWITCH Register Masks
 * @{
 */

/*! @name FN_MOD_BM_ISS - Bus Matrix Issuing Functionality Modification. */
/*! @{ */
#define AXI_SWITCH_FN_MOD_BM_ISS_FN_MOD_BM_ISS_MASK (0x3U)
#define AXI_SWITCH_FN_MOD_BM_ISS_FN_MOD_BM_ISS_SHIFT (0U)
/*! FN_MOD_BM_ISS - Read channel QoS value
 */
#define AXI_SWITCH_FN_MOD_BM_ISS_FN_MOD_BM_ISS(x) (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_FN_MOD_BM_ISS_FN_MOD_BM_ISS_SHIFT)) & AXI_SWITCH_FN_MOD_BM_ISS_FN_MOD_BM_ISS_MASK)
/*! @} */

/*! @name FN_MOD2 - Bypass Merge */
/*! @{ */
#define AXI_SWITCH_FN_MOD2_FN_MOD2_MASK          (0x1U)
#define AXI_SWITCH_FN_MOD2_FN_MOD2_SHIFT         (0U)
/*! FN_MOD2 - Bypass Merge
 */
#define AXI_SWITCH_FN_MOD2_FN_MOD2(x)            (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_FN_MOD2_FN_MOD2_SHIFT)) & AXI_SWITCH_FN_MOD2_FN_MOD2_MASK)
/*! @} */

/*! @name READ_QOS - Read channel QoS value */
/*! @{ */
#define AXI_SWITCH_READ_QOS_READ_QOS_MASK        (0xFU)
#define AXI_SWITCH_READ_QOS_READ_QOS_SHIFT       (0U)
/*! READ_QOS - Read channel QoS value
 */
#define AXI_SWITCH_READ_QOS_READ_QOS(x)          (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_READ_QOS_READ_QOS_SHIFT)) & AXI_SWITCH_READ_QOS_READ_QOS_MASK)
/*! @} */

/*! @name WRITE_QOS - WRITE channel QoS value */
/*! @{ */
#define AXI_SWITCH_WRITE_QOS_WRITE_QOS_MASK      (0xFU)
#define AXI_SWITCH_WRITE_QOS_WRITE_QOS_SHIFT     (0U)
/*! WRITE_QOS - Write channel QoS value
 */
#define AXI_SWITCH_WRITE_QOS_WRITE_QOS(x)        (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_WRITE_QOS_WRITE_QOS_SHIFT)) & AXI_SWITCH_WRITE_QOS_WRITE_QOS_MASK)
/*! @} */

/*! @name FN_MOD - Issuing Functionality Modification */
/*! @{ */
#define AXI_SWITCH_FN_MOD_FN_MOD_MASK            (0x3U)
#define AXI_SWITCH_FN_MOD_FN_MOD_SHIFT           (0U)
/*! FN_MOD - Bypass Merge
 */
#define AXI_SWITCH_FN_MOD_FN_MOD(x)              (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_FN_MOD_FN_MOD_SHIFT)) & AXI_SWITCH_FN_MOD_FN_MOD_MASK)
#define AXI_SWITCH_FN_MOD_WRITE_QOS_MASK         (0x3U)
#define AXI_SWITCH_FN_MOD_WRITE_QOS_SHIFT        (0U)
/*! WRITE_QOS - Write channel QoS value
 */
#define AXI_SWITCH_FN_MOD_WRITE_QOS(x)           (((uint32_t)(((uint32_t)(x)) << AXI_SWITCH_FN_MOD_WRITE_QOS_SHIFT)) & AXI_SWITCH_FN_MOD_WRITE_QOS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group AXI_SWITCH_Register_Masks */


/* AXI_SWITCH - Peripheral instance base addresses */
/** Peripheral AXI_SWITCH_AMIB base address */
#define AXI_SWITCH_AMIB_BASE                     (0x428EBFC0u)
/** Peripheral AXI_SWITCH_AMIB base pointer */
#define AXI_SWITCH_AMIB                          ((AXI_SWITCH_Type *)AXI_SWITCH_AMIB_BASE)
/** Peripheral AXI_SWITCH_ASIB base address */
#define AXI_SWITCH_ASIB_BASE                     (0x428E9FC0u)
/** Peripheral AXI_SWITCH_ASIB base pointer */
#define AXI_SWITCH_ASIB                          ((AXI_SWITCH_Type *)AXI_SWITCH_ASIB_BASE)
/** Array initializer of AXI_SWITCH peripheral base addresses */
#define AXI_SWITCH_BASE_ADDRS                    { AXI_SWITCH_AMIB_BASE, AXI_SWITCH_ASIB_BASE }
/** Array initializer of AXI_SWITCH peripheral base pointers */
#define AXI_SWITCH_BASE_PTRS                     { AXI_SWITCH_AMIB, AXI_SWITCH_ASIB }

/*!
 * @}
 */ /* end of group AXI_SWITCH_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Peripheral_Access_Layer CACHE64_CTRL Peripheral Access Layer
 * @{
 */

/** CACHE64_CTRL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __IO uint32_t CCR;                               /**< Cache control register, offset: 0x800 */
  __IO uint32_t CLCR;                              /**< Cache line control register, offset: 0x804 */
  __IO uint32_t CSAR;                              /**< Cache search address register, offset: 0x808 */
  __IO uint32_t CCVR;                              /**< Cache read/write value register, offset: 0x80C */
  __IO uint32_t CSRR;                              /**< Cache soft reset register, offset: 0x810 */
} CACHE64_CTRL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_CTRL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_CTRL_Register_Masks CACHE64_CTRL Register Masks
 * @{
 */

/*! @name CCR - Cache control register */
/*! @{ */
#define CACHE64_CTRL_CCR_ENCACHE_MASK            (0x1U)
#define CACHE64_CTRL_CCR_ENCACHE_SHIFT           (0U)
/*! ENCACHE - Cache enable
 *  0b0..Cache disabled
 *  0b1..Cache enabled
 */
#define CACHE64_CTRL_CCR_ENCACHE(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENCACHE_SHIFT)) & CACHE64_CTRL_CCR_ENCACHE_MASK)
#define CACHE64_CTRL_CCR_ENWRBUF_MASK            (0x2U)
#define CACHE64_CTRL_CCR_ENWRBUF_SHIFT           (1U)
/*! ENWRBUF - Enable Write Buffer
 *  0b0..Write buffer disabled
 *  0b1..Write buffer enabled
 */
#define CACHE64_CTRL_CCR_ENWRBUF(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_ENWRBUF_SHIFT)) & CACHE64_CTRL_CCR_ENWRBUF_MASK)
#define CACHE64_CTRL_CCR_INVW0_MASK              (0x1000000U)
#define CACHE64_CTRL_CCR_INVW0_SHIFT             (24U)
/*! INVW0 - Invalidate Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 0.
 */
#define CACHE64_CTRL_CCR_INVW0(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW0_SHIFT)) & CACHE64_CTRL_CCR_INVW0_MASK)
#define CACHE64_CTRL_CCR_PUSHW0_MASK             (0x2000000U)
#define CACHE64_CTRL_CCR_PUSHW0_SHIFT            (25U)
/*! PUSHW0 - Push Way 0
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 0
 */
#define CACHE64_CTRL_CCR_PUSHW0(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW0_SHIFT)) & CACHE64_CTRL_CCR_PUSHW0_MASK)
#define CACHE64_CTRL_CCR_INVW1_MASK              (0x4000000U)
#define CACHE64_CTRL_CCR_INVW1_SHIFT             (26U)
/*! INVW1 - Invalidate Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, invalidate all lines in way 1
 */
#define CACHE64_CTRL_CCR_INVW1(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
#define CACHE64_CTRL_CCR_PUSHW1_MASK             (0x8000000U)
#define CACHE64_CTRL_CCR_PUSHW1_SHIFT            (27U)
/*! PUSHW1 - Push Way 1
 *  0b0..No operation
 *  0b1..When setting the GO bit, push all modified lines in way 1
 */
#define CACHE64_CTRL_CCR_PUSHW1(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_PUSHW1_SHIFT)) & CACHE64_CTRL_CCR_PUSHW1_MASK)
#define CACHE64_CTRL_CCR_GO_MASK                 (0x80000000U)
#define CACHE64_CTRL_CCR_GO_SHIFT                (31U)
/*! GO - Initiate Cache Command
 *  0b0..Write: no effect. Read: no cache command active.
 *  0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
 */
#define CACHE64_CTRL_CCR_GO(x)                   (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/*! @} */

/*! @name CLCR - Cache line control register */
/*! @{ */
#define CACHE64_CTRL_CLCR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CLCR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
 */
#define CACHE64_CTRL_CLCR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
#define CACHE64_CTRL_CLCR_CACHEADDR_MASK         (0x3FFCU)
#define CACHE64_CTRL_CLCR_CACHEADDR_SHIFT        (2U)
/*! CACHEADDR - Cache address
 */
#define CACHE64_CTRL_CLCR_CACHEADDR(x)           (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_CACHEADDR_SHIFT)) & CACHE64_CTRL_CLCR_CACHEADDR_MASK)
#define CACHE64_CTRL_CLCR_WSEL_MASK              (0x4000U)
#define CACHE64_CTRL_CLCR_WSEL_SHIFT             (14U)
/*! WSEL - Way select
 *  0b0..Way 0
 *  0b1..Way 1
 */
#define CACHE64_CTRL_CLCR_WSEL(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_WSEL_SHIFT)) & CACHE64_CTRL_CLCR_WSEL_MASK)
#define CACHE64_CTRL_CLCR_TDSEL_MASK             (0x10000U)
#define CACHE64_CTRL_CLCR_TDSEL_SHIFT            (16U)
/*! TDSEL - Tag/Data Select
 *  0b0..Data
 *  0b1..Tag
 */
#define CACHE64_CTRL_CLCR_TDSEL(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_TDSEL_SHIFT)) & CACHE64_CTRL_CLCR_TDSEL_MASK)
#define CACHE64_CTRL_CLCR_LCIVB_MASK             (0x100000U)
#define CACHE64_CTRL_CLCR_LCIVB_SHIFT            (20U)
/*! LCIVB - Line Command Initial Valid Bit
 */
#define CACHE64_CTRL_CLCR_LCIVB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIVB_SHIFT)) & CACHE64_CTRL_CLCR_LCIVB_MASK)
#define CACHE64_CTRL_CLCR_LCIMB_MASK             (0x200000U)
#define CACHE64_CTRL_CLCR_LCIMB_SHIFT            (21U)
/*! LCIMB - Line Command Initial Modified Bit
 */
#define CACHE64_CTRL_CLCR_LCIMB(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCIMB_SHIFT)) & CACHE64_CTRL_CLCR_LCIMB_MASK)
#define CACHE64_CTRL_CLCR_LCWAY_MASK             (0x400000U)
#define CACHE64_CTRL_CLCR_LCWAY_SHIFT            (22U)
/*! LCWAY - Line Command Way
 */
#define CACHE64_CTRL_CLCR_LCWAY(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCWAY_SHIFT)) & CACHE64_CTRL_CLCR_LCWAY_MASK)
#define CACHE64_CTRL_CLCR_LCMD_MASK              (0x3000000U)
#define CACHE64_CTRL_CLCR_LCMD_SHIFT             (24U)
/*! LCMD - Line Command
 *  0b00..Search and read or write
 *  0b01..Invalidate
 *  0b10..Push
 *  0b11..Clear
 */
#define CACHE64_CTRL_CLCR_LCMD(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LCMD_SHIFT)) & CACHE64_CTRL_CLCR_LCMD_MASK)
#define CACHE64_CTRL_CLCR_LADSEL_MASK            (0x4000000U)
#define CACHE64_CTRL_CLCR_LADSEL_SHIFT           (26U)
/*! LADSEL - Line Address Select
 *  0b0..Cache address
 *  0b1..Physical address
 */
#define CACHE64_CTRL_CLCR_LADSEL(x)              (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
#define CACHE64_CTRL_CLCR_LACC_MASK              (0x8000000U)
#define CACHE64_CTRL_CLCR_LACC_SHIFT             (27U)
/*! LACC - Line access type
 *  0b0..Read
 *  0b1..Write
 */
#define CACHE64_CTRL_CLCR_LACC(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/*! @} */

/*! @name CSAR - Cache search address register */
/*! @{ */
#define CACHE64_CTRL_CSAR_LGO_MASK               (0x1U)
#define CACHE64_CTRL_CSAR_LGO_SHIFT              (0U)
/*! LGO - Initiate Cache Line Command
 *  0b0..Write: no effect. Read: no line command active.
 *  0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
 */
#define CACHE64_CTRL_CSAR_LGO(x)                 (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_LGO_SHIFT)) & CACHE64_CTRL_CSAR_LGO_MASK)
#define CACHE64_CTRL_CSAR_PHYADDR27_1_MASK       (0xFFFFFFEU)
#define CACHE64_CTRL_CSAR_PHYADDR27_1_SHIFT      (1U)
/*! PHYADDR27_1 - Physical Address
 */
#define CACHE64_CTRL_CSAR_PHYADDR27_1(x)         (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR27_1_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR27_1_MASK)
#define CACHE64_CTRL_CSAR_PHYADDR31_29_MASK      (0xE0000000U)
#define CACHE64_CTRL_CSAR_PHYADDR31_29_SHIFT     (29U)
/*! PHYADDR31_29 - Physical Address
 */
#define CACHE64_CTRL_CSAR_PHYADDR31_29(x)        (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSAR_PHYADDR31_29_SHIFT)) & CACHE64_CTRL_CSAR_PHYADDR31_29_MASK)
/*! @} */

/*! @name CCVR - Cache read/write value register */
/*! @{ */
#define CACHE64_CTRL_CCVR_DATA_MASK              (0xFFFFFFFFU)
#define CACHE64_CTRL_CCVR_DATA_SHIFT             (0U)
/*! DATA - Cache read/write Data
 */
#define CACHE64_CTRL_CCVR_DATA(x)                (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCVR_DATA_SHIFT)) & CACHE64_CTRL_CCVR_DATA_MASK)
/*! @} */

/*! @name CSRR - Cache soft reset register */
/*! @{ */
#define CACHE64_CTRL_CSRR_RESET_MASK             (0x3U)
#define CACHE64_CTRL_CSRR_RESET_SHIFT            (0U)
/*! RESET - Issue soft reset
 */
#define CACHE64_CTRL_CSRR_RESET(x)               (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CSRR_RESET_SHIFT)) & CACHE64_CTRL_CSRR_RESET_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_CTRL_Register_Masks */


/* CACHE64_CTRL - Peripheral instance base addresses */
/** Peripheral CACHE64_CTRL0 base address */
#define CACHE64_CTRL0_BASE                       (0x40033000u)
/** Peripheral CACHE64_CTRL0 base pointer */
#define CACHE64_CTRL0                            ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE)
/** Peripheral CACHE64_CTRL1 base address */
#define CACHE64_CTRL1_BASE                       (0x40034000u)
/** Peripheral CACHE64_CTRL1 base pointer */
#define CACHE64_CTRL1                            ((CACHE64_CTRL_Type *)CACHE64_CTRL1_BASE)
/** Array initializer of CACHE64_CTRL peripheral base addresses */
#define CACHE64_CTRL_BASE_ADDRS                  { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE }
/** Array initializer of CACHE64_CTRL peripheral base pointers */
#define CACHE64_CTRL_BASE_PTRS                   { CACHE64_CTRL0, CACHE64_CTRL1 }
/* Backward compatibility */
#define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYADDR31_29_MASK)


/*!
 * @}
 */ /* end of group CACHE64_CTRL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CACHE64_POLSEL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_POLSEL_Peripheral_Access_Layer CACHE64_POLSEL Peripheral Access Layer
 * @{
 */

/** CACHE64_POLSEL - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[20];
  __IO uint32_t REG0_TOP;                          /**< Region 0 Top Boundary, offset: 0x14 */
  __IO uint32_t REG1_TOP;                          /**< Region 1 Top Boundary, offset: 0x18 */
  __IO uint32_t POLSEL;                            /**< Policy Select, offset: 0x1C */
} CACHE64_POLSEL_Type;

/* ----------------------------------------------------------------------------
   -- CACHE64_POLSEL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CACHE64_POLSEL_Register_Masks CACHE64_POLSEL Register Masks
 * @{
 */

/*! @name REG0_TOP - Region 0 Top Boundary */
/*! @{ */
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK    (0x7FFFC00U)
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT   (10U)
/*! REG0_TOP - Upper limit of Region 0
 */
#define CACHE64_POLSEL_REG0_TOP_REG0_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) & CACHE64_POLSEL_REG0_TOP_REG0_TOP_MASK)
/*! @} */

/*! @name REG1_TOP - Region 1 Top Boundary */
/*! @{ */
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK    (0x7FFFC00U)
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT   (10U)
/*! REG1_TOP - Upper limit of Region 1
 */
#define CACHE64_POLSEL_REG1_TOP_REG1_TOP(x)      (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG1_TOP_REG1_TOP_SHIFT)) & CACHE64_POLSEL_REG1_TOP_REG1_TOP_MASK)
/*! @} */

/*! @name POLSEL - Policy Select */
/*! @{ */
#define CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK   (0x3U)
#define CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT  (0U)
/*! REG0_POLICY - Policy Select for Region 0
 *  0b00..Non-cache
 *  0b01..Write-thru
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG0_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG0_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG0_POLICY_MASK)
#define CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK   (0xCU)
#define CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT  (2U)
/*! REG1_POLICY - Policy Select for Region 0
 *  0b00..Non-cache
 *  0b01..Write-thru
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG1_POLICY(x)     (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG1_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG1_POLICY_MASK)
#define CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK  (0x30U)
#define CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT (4U)
/*! REG02_POLICY - Policy Select for Region 0
 *  0b00..Non-cache
 *  0b01..Write-thru
 *  0b10..Write-back
 *  0b11..Invalid
 */
#define CACHE64_POLSEL_POLSEL_REG02_POLICY(x)    (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POLSEL_REG02_POLICY_SHIFT)) & CACHE64_POLSEL_POLSEL_REG02_POLICY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CACHE64_POLSEL_Register_Masks */


/* CACHE64_POLSEL - Peripheral instance base addresses */
/** Peripheral CACHE64_POLSEL0 base address */
#define CACHE64_POLSEL0_BASE                     (0x40033000u)
/** Peripheral CACHE64_POLSEL0 base pointer */
#define CACHE64_POLSEL0                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL0_BASE)
/** Peripheral CACHE64_POLSEL1 base address */
#define CACHE64_POLSEL1_BASE                     (0x40034000u)
/** Peripheral CACHE64_POLSEL1 base pointer */
#define CACHE64_POLSEL1                          ((CACHE64_POLSEL_Type *)CACHE64_POLSEL1_BASE)
/** Array initializer of CACHE64_POLSEL peripheral base addresses */
#define CACHE64_POLSEL_BASE_ADDRS                { CACHE64_POLSEL0_BASE, CACHE64_POLSEL1_BASE }
/** Array initializer of CACHE64_POLSEL peripheral base pointers */
#define CACHE64_POLSEL_BASE_PTRS                 { CACHE64_POLSEL0, CACHE64_POLSEL1 }

/*!
 * @}
 */ /* end of group CACHE64_POLSEL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CASPER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer
 * @{
 */

/** CASPER - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL0;                             /**< Control 0, offset: 0x0 */
  __IO uint32_t CTRL1;                             /**< Control 1, offset: 0x4 */
  __IO uint32_t LOADER;                            /**< Loader, offset: 0x8 */
  __IO uint32_t STATUS;                            /**< Status, offset: 0xC */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set, offset: 0x10 */
  __IO uint32_t INTENCLR;                          /**< Interrupt Enable Clear, offset: 0x14 */
  __I  uint32_t INTSTAT;                           /**< Interrupt status, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t AREG;                              /**< A Register, offset: 0x20 */
  __IO uint32_t BREG;                              /**< B Register, offset: 0x24 */
  __IO uint32_t CREG;                              /**< C Register, offset: 0x28 */
  __IO uint32_t DREG;                              /**< D Register, offset: 0x2C */
  __IO uint32_t RES0;                              /**< Result Register 0, offset: 0x30 */
  __IO uint32_t RES1;                              /**< Result Register 1, offset: 0x34 */
  __IO uint32_t RES2;                              /**< Result Register 2, offset: 0x38 */
  __IO uint32_t RES3;                              /**< Result Register 3, offset: 0x3C */
       uint8_t RESERVED_1[32];
  __IO uint32_t MASK;                              /**< Mask, offset: 0x60 */
  __IO uint32_t REMASK;                            /**< Remask, offset: 0x64 */
       uint8_t RESERVED_2[24];
  __IO uint32_t LOCK;                              /**< Lock, offset: 0x80 */
} CASPER_Type;

/* ----------------------------------------------------------------------------
   -- CASPER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CASPER_Register_Masks CASPER Register Masks
 * @{
 */

/*! @name CTRL0 - Control 0 */
/*! @{ */
#define CASPER_CTRL0_ABBPAIR_MASK                (0x1U)
#define CASPER_CTRL0_ABBPAIR_SHIFT               (0U)
/*! ABBPAIR - ABOFF Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_CTRL0_ABBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)
#define CASPER_CTRL0_ABOFF_MASK                  (0x4U)
#define CASPER_CTRL0_ABOFF_SHIFT                 (2U)
/*! ABOFF - AB Offset
 */
#define CASPER_CTRL0_ABOFF(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)
#define CASPER_CTRL0_CDBPAIR_MASK                (0x10000U)
#define CASPER_CTRL0_CDBPAIR_SHIFT               (16U)
/*! CDBPAIR - CDOFF Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_CTRL0_CDBPAIR(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)
#define CASPER_CTRL0_CDOFF_MASK                  (0x1FFC0000U)
#define CASPER_CTRL0_CDOFF_SHIFT                 (18U)
/*! CDOFF - CD Offset
 */
#define CASPER_CTRL0_CDOFF(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)
/*! @} */

/*! @name CTRL1 - Control 1 */
/*! @{ */
#define CASPER_CTRL1_ITER_MASK                   (0xFFU)
#define CASPER_CTRL1_ITER_SHIFT                  (0U)
/*! ITER - Interation Counter
 */
#define CASPER_CTRL1_ITER(x)                     (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)
#define CASPER_CTRL1_MODE_MASK                   (0xFF00U)
#define CASPER_CTRL1_MODE_SHIFT                  (8U)
/*! MODE - Mode
 */
#define CASPER_CTRL1_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
#define CASPER_CTRL1_RESBPAIR_MASK               (0x10000U)
#define CASPER_CTRL1_RESBPAIR_SHIFT              (16U)
/*! RESBPAIR - RESOFF Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_CTRL1_RESBPAIR(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)
#define CASPER_CTRL1_RESOFF_MASK                 (0x1FFC0000U)
#define CASPER_CTRL1_RESOFF_SHIFT                (18U)
/*! RESOFF - Result Offset
 */
#define CASPER_CTRL1_RESOFF(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)
#define CASPER_CTRL1_CSKIP_MASK                  (0xC0000000U)
#define CASPER_CTRL1_CSKIP_SHIFT                 (30U)
/*! CSKIP - Skip Rules on Carry
 *  0b00..No Skip
 *  0b01..Skip if Carry is 1
 *  0b10..Skip if Carry is 0
 *  0b11..Set CTRLOFF to CDOFF and Skip
 */
#define CASPER_CTRL1_CSKIP(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)
/*! @} */

/*! @name LOADER - Loader */
/*! @{ */
#define CASPER_LOADER_COUNT_MASK                 (0xFFU)
#define CASPER_LOADER_COUNT_SHIFT                (0U)
/*! COUNT - Count
 */
#define CASPER_LOADER_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK)
#define CASPER_LOADER_CTRLBPAIR_MASK             (0x10000U)
#define CASPER_LOADER_CTRLBPAIR_SHIFT            (16U)
/*! CTRLBPAIR - Control Bank Pair
 *  0b0..Bank-pair 0 (1st)
 *  0b1..Bank-pair 1 (2nd)
 */
#define CASPER_LOADER_CTRLBPAIR(x)               (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK)
#define CASPER_LOADER_CTRLOFF_MASK               (0x1FFC0000U)
#define CASPER_LOADER_CTRLOFF_SHIFT              (18U)
/*! CTRLOFF - Control Offset
 */
#define CASPER_LOADER_CTRLOFF(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */
#define CASPER_STATUS_DONE_MASK                  (0x1U)
#define CASPER_STATUS_DONE_SHIFT                 (0U)
/*! DONE - Done
 *  0b0..Busy or just cleared
 *  0b1..Completed last operation
 */
#define CASPER_STATUS_DONE(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)
#define CASPER_STATUS_CARRY_MASK                 (0x10U)
#define CASPER_STATUS_CARRY_SHIFT                (4U)
/*! CARRY - Carry
 *  0b0..Carry was 0 or no carry
 *  0b1..Carry was 1
 */
#define CASPER_STATUS_CARRY(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)
#define CASPER_STATUS_BUSY_MASK                  (0x20U)
#define CASPER_STATUS_BUSY_SHIFT                 (5U)
/*! BUSY - Busy
 *  0b0..Not busy - is idle
 *  0b1..Is busy
 */
#define CASPER_STATUS_BUSY(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Set */
/*! @{ */
#define CASPER_INTENSET_DONE_MASK                (0x1U)
#define CASPER_INTENSET_DONE_SHIFT               (0U)
/*! DONE - Done
 *  0b0..Do not interrupt when done
 *  0b1..Interrupt when done
 */
#define CASPER_INTENSET_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear */
/*! @{ */
#define CASPER_INTENCLR_DONE_MASK                (0x1U)
#define CASPER_INTENCLR_DONE_SHIFT               (0U)
/*! DONE - Done
 *  0b0..If written 0, ignored
 *  0b1..If written 1, do not interrupt when done.
 */
#define CASPER_INTENCLR_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt status */
/*! @{ */
#define CASPER_INTSTAT_DONE_MASK                 (0x1U)
#define CASPER_INTSTAT_DONE_SHIFT                (0U)
/*! DONE
 *  0b0..Not caused by accelerator being done
 *  0b1..Caused by accelerator being done
 */
#define CASPER_INTSTAT_DONE(x)                   (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)
/*! @} */

/*! @name AREG - A Register */
/*! @{ */
#define CASPER_AREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_AREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value
 */
#define CASPER_AREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)
/*! @} */

/*! @name BREG - B Register */
/*! @{ */
#define CASPER_BREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_BREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value
 */
#define CASPER_BREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)
/*! @} */

/*! @name CREG - C Register */
/*! @{ */
#define CASPER_CREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_CREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value
 */
#define CASPER_CREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)
/*! @} */

/*! @name DREG - D Register */
/*! @{ */
#define CASPER_DREG_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_DREG_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value
 */
#define CASPER_DREG_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)
/*! @} */

/*! @name RES0 - Result Register 0 */
/*! @{ */
#define CASPER_RES0_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES0_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value
 */
#define CASPER_RES0_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)
/*! @} */

/*! @name RES1 - Result Register 1 */
/*! @{ */
#define CASPER_RES1_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES1_REG_VALUE_SHIFT              (0U)
#define CASPER_RES1_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)
/*! @} */

/*! @name RES2 - Result Register 2 */
/*! @{ */
#define CASPER_RES2_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES2_REG_VALUE_SHIFT              (0U)
/*! REG_VALUE - Register Value
 */
#define CASPER_RES2_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)
/*! @} */

/*! @name RES3 - Result Register 3 */
/*! @{ */
#define CASPER_RES3_REG_VALUE_MASK               (0xFFFFFFFFU)
#define CASPER_RES3_REG_VALUE_SHIFT              (0U)
#define CASPER_RES3_REG_VALUE(x)                 (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)
/*! @} */

/*! @name MASK - Mask */
/*! @{ */
#define CASPER_MASK_MASK_MASK                    (0xFFFFFFFFU)
#define CASPER_MASK_MASK_SHIFT                   (0U)
/*! MASK - Mask
 */
#define CASPER_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)
/*! @} */

/*! @name REMASK - Remask */
/*! @{ */
#define CASPER_REMASK_MASK_MASK                  (0xFFFFFFFFU)
#define CASPER_REMASK_MASK_SHIFT                 (0U)
/*! MASK - Mask
 */
#define CASPER_REMASK_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)
/*! @} */

/*! @name LOCK - Lock */
/*! @{ */
#define CASPER_LOCK_LOCK_MASK                    (0x1U)
#define CASPER_LOCK_LOCK_SHIFT                   (0U)
/*! LOCK - Lock
 *  0b0..Unlock
 *  0b1..Lock to current security level
 */
#define CASPER_LOCK_LOCK(x)                      (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)
#define CASPER_LOCK_KEY_MASK                     (0x1FFF0U)
#define CASPER_LOCK_KEY_SHIFT                    (4U)
/*! KEY - Key
 *  0b0011100111101..Key Value
 */
#define CASPER_LOCK_KEY(x)                       (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CASPER_Register_Masks */


/* CASPER - Peripheral instance base addresses */
/** Peripheral CASPER base address */
#define CASPER_BASE                              (0x40201000u)
/** Peripheral CASPER base pointer */
#define CASPER                                   ((CASPER_Type *)CASPER_BASE)
/** Array initializer of CASPER peripheral base addresses */
#define CASPER_BASE_ADDRS                        { CASPER_BASE }
/** Array initializer of CASPER peripheral base pointers */
#define CASPER_BASE_PTRS                         { CASPER }

/*!
 * @}
 */ /* end of group CASPER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CLKCTL0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL0_Peripheral_Access_Layer CLKCTL0 Peripheral Access Layer
 * @{
 */

/** CLKCTL0 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PSCCTL0;                           /**< Clock Control 0, offset: 0x10 */
  __IO uint32_t PSCCTL1;                           /**< Clock Control 1, offset: 0x14 */
  __IO uint32_t PSCCTL2;                           /**< Clock Control 2, offset: 0x18 */
       uint8_t RESERVED_1[36];
  __O  uint32_t PSCCTL0_SET;                       /**< Clock Control 0 Set, offset: 0x40 */
  __O  uint32_t PSCCTL1_SET;                       /**< Clock Control 1 Set, offset: 0x44 */
  __O  uint32_t PSCCTL2_SET;                       /**< Clock Control 2 Set, offset: 0x48 */
       uint8_t RESERVED_2[36];
  __O  uint32_t PSCCTL0_CLR;                       /**< Clock Control 0 Clear, offset: 0x70 */
  __O  uint32_t PSCCTL1_CLR;                       /**< Clock Control 1 Clear, offset: 0x74 */
  __O  uint32_t PSCCTL2_CLR;                       /**< Clock Control 2 Clear, offset: 0x78 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FRO_CONTROL;                       /**< Free Running Oscillator Control, offset: 0x80 */
  __I  uint32_t FRO_CAPVAL;                        /**< Free Running Oscillator Captured Value, offset: 0x84 */
       uint8_t RESERVED_4[4];
  __IO uint32_t FRO_RDTRIM;                        /**< Free Running Oscillator Trim, offset: 0x8C */
       uint8_t RESERVED_5[120];
  __IO uint32_t FRODIVSEL;                         /**< FRO Clock Divider, offset: 0x108 */
  __I  uint32_t FROCLKSTATUS;                      /**< FRO Clock Status, offset: 0x10C */
  __IO uint32_t FRODIVOEN;                         /**< FRO Enable Register, offset: 0x110 */
       uint8_t RESERVED_6[28];
  __IO uint32_t LOWFREQCLKDIV;                     /**< Low Frequency Clock Divider, offset: 0x130 */
       uint8_t RESERVED_7[44];
  __IO uint32_t SYSOSCCTL0;                        /**< System Oscillator Control 0, offset: 0x160 */
       uint8_t RESERVED_8[4];
  __IO uint32_t SYSOSCBYPASS;                      /**< OSC Clock Source Select, offset: 0x168 */
       uint8_t RESERVED_9[36];
  __IO uint32_t LPOSCCTL0;                         /**< Low Power Oscillator Control 0, offset: 0x190 */
       uint8_t RESERVED_10[44];
  __IO uint32_t OSC32KHZCTL0;                      /**< 32 KHz Oscillator Control 0, offset: 0x1C0 */
       uint8_t RESERVED_11[60];
  __IO uint32_t SYSPLL0CLKSEL;                     /**< System PLL 0 Clock Select, offset: 0x200 */
  __IO uint32_t SYSPLL0CTL0;                       /**< System PLL0 Control 0, offset: 0x204 */
       uint8_t RESERVED_12[4];
  __IO uint32_t SYSPLL0LOCKTIMEDIV2;               /**< System PLL0 Lock Time Div2, offset: 0x20C */
  __IO uint32_t SYSPLL0NUM;                        /**< System PLL0 Numerator, offset: 0x210 */
  __IO uint32_t SYSPLL0DENOM;                      /**< System PLL0 Denominator, offset: 0x214 */
  __IO uint32_t SYSPLL0PFD;                        /**< System PLL0 PFD, offset: 0x218 */
       uint8_t RESERVED_13[484];
  __IO uint32_t SYSCPUAHBCLKDIV;                   /**< System CPU AHB Clock Divider, offset: 0x400 */
       uint8_t RESERVED_14[44];
  __IO uint32_t MAINCLKSELA;                       /**< Main Clock Select A, offset: 0x430 */
  __IO uint32_t MAINCLKSELB;                       /**< Main Clock Select B, offset: 0x434 */
       uint8_t RESERVED_15[200];
  __IO uint32_t PFCDIV[2];                         /**< PFC0DIV..PFC1DIV, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_16[280];
  __IO uint32_t FLEXSPI0FCLKSEL;                   /**< FlexSPI0 Functional Clock Select, offset: 0x620 */
  __IO uint32_t FLEXSPI0FCLKDIV;                   /**< FlexSPI0 Functional Clock Divider, offset: 0x624 */
       uint8_t RESERVED_17[8];
  __IO uint32_t FLEXSPI1FCLKSEL;                   /**< FlexSPI1 Functional Clock Select, offset: 0x630 */
  __IO uint32_t FLEXSPI1FCLKDIV;                   /**< FlexSPI1 Functional Clock Divider, offset: 0x634 */
       uint8_t RESERVED_18[8];
  __IO uint32_t SCTFCLKSEL;                        /**< SCT Functional Clock Select, offset: 0x640 */
  __IO uint32_t SCTIN7CLKDIV;                      /**< SCT Functional Clock Divider, offset: 0x644 */
       uint8_t RESERVED_19[24];
  __IO uint32_t USBHSFCLKSEL;                      /**< High Speed USB Functional Clock Select, offset: 0x660 */
  __IO uint32_t USBHSFCLKDIV;                      /**< High Speed USB Functional Clock Divider, offset: 0x664 */
       uint8_t RESERVED_20[24];
  __IO uint32_t SDIO0FCLKSEL;                      /**< SDIO0 Functional Clock Select, offset: 0x680 */
  __IO uint32_t SDIO0FCLKDIV;                      /**< SDIO0 Functional Clock Divider, offset: 0x684 */
       uint8_t RESERVED_21[8];
  __IO uint32_t SDIO1FCLKSEL;                      /**< SDIO1 Functional Clock Select, offset: 0x690 */
  __IO uint32_t SDIO1FCLKDIV;                      /**< SDIO1 Functional Clock Divider, offset: 0x694 */
       uint8_t RESERVED_22[56];
  __IO uint32_t ADC0FCLKSEL0;                      /**< ADC0 Functional Clock Select 0, offset: 0x6D0 */
  __IO uint32_t ADC0FCLKSEL1;                      /**< ADC0 Functional Clock Select 1, offset: 0x6D4 */
  __IO uint32_t ADC0FCLKDIV;                       /**< ADC0 Functional Clock Divider, offset: 0x6D8 */
       uint8_t RESERVED_23[36];
  __IO uint32_t UTICKFCLKSEL;                      /**< UTICK Functional Clock Select, offset: 0x700 */
       uint8_t RESERVED_24[28];
  __IO uint32_t WDT0FCLKSEL;                       /**< WDT0 Functional Clock Select, offset: 0x720 */
       uint8_t RESERVED_25[12];
  __IO uint32_t A32KHZWAKECLKSEL;                  /**< 32 KHz Wake Clock Source Select, offset: 0x730 */
  __IO uint32_t A32KHZWAKECLKDIV;                  /**< 32 KHz Wake Clock Divider, offset: 0x734 */
       uint8_t RESERVED_26[40];
  __IO uint32_t SYSTICKFCLKSEL;                    /**< SYSTICK Functional Clock Select, offset: 0x760 */
  __IO uint32_t SYSTICKFCLKDIV;                    /**< SYSTICK Functional Clock Divider, offset: 0x764 */
       uint8_t RESERVED_27[8];
  __IO uint32_t DPHYCLKSEL;                        /**< MIPI-DSI PHY Clock Select, offset: 0x770 */
  __IO uint32_t DPHYCLKDIV;                        /**< MIPI-DSI PHY Clock Divider, offset: 0x774 */
  __IO uint32_t DPHYESCCLKSEL;                     /**< MIPI-DSI DPHY Escape Mode Clock Select, offset: 0x778 */
  __IO uint32_t DPHYESCRXCLKDIV;                   /**< MIPI-DSI DPHY Escape Mode Receive Clock Divider, offset: 0x77C */
  __IO uint32_t DPHYESCTXCLKDIV;                   /**< MIPI-DSI DPHY Escape Mode Tramsmit Clock Divider, offset: 0x780 */
       uint8_t RESERVED_28[12];
  __IO uint32_t GPUCLKSEL;                         /**< GPU Clock Select, offset: 0x790 */
  __IO uint32_t GPUCLKDIV;                         /**< GPU Clock Divider, offset: 0x794 */
       uint8_t RESERVED_29[8];
  __IO uint32_t DCPIXELCLKSEL;                     /**< LCDIF Pixel Clock Select, offset: 0x7A0 */
  __IO uint32_t DCPIXELCLKDIV;                     /**< LCDIF Pixel Clock Divider, offset: 0x7A4 */
} CLKCTL0_Type;

/* ----------------------------------------------------------------------------
   -- CLKCTL0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL0_Register_Masks CLKCTL0 Register Masks
 * @{
 */

/*! @name PSCCTL0 - Clock Control 0 */
/*! @{ */
#define CLKCTL0_PSCCTL0_DSP_CLK_MASK             (0x2U)
#define CLKCTL0_PSCCTL0_DSP_CLK_SHIFT            (1U)
/*! DSP_CLK - DSP clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_DSP_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_DSP_CLK_SHIFT)) & CLKCTL0_PSCCTL0_DSP_CLK_MASK)
#define CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_MASK       (0x4U)
#define CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_SHIFT      (2U)
/*! ROM_CTRLR_CLK - 128KB ROM Controller clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_ROM_CTRLR_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_ROM_CTRLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_MASK      (0x8U)
#define CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_SHIFT     (3U)
/*! AXI_SWITCH_CLK - AXI Switch clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_AXI_SWITCH_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_SHIFT)) & CLKCTL0_PSCCTL0_AXI_SWITCH_CLK_MASK)
#define CLKCTL0_PSCCTL0_AXI_CTLR_CLK_MASK        (0x10U)
#define CLKCTL0_PSCCTL0_AXI_CTLR_CLK_SHIFT       (4U)
/*! AXI_CTLR_CLK - AXI Controller clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_AXI_CTLR_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_AXI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_AXI_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_POWERQUAD_CLK_MASK       (0x100U)
#define CLKCTL0_PSCCTL0_POWERQUAD_CLK_SHIFT      (8U)
/*! POWERQUAD_CLK - POWERQUAD clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_POWERQUAD_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_POWERQUAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_POWERQUAD_CLK_MASK)
#define CLKCTL0_PSCCTL0_CASPER_CLK_MASK          (0x200U)
#define CLKCTL0_PSCCTL0_CASPER_CLK_SHIFT         (9U)
/*! CASPER_CLK - CASPER clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_CASPER_CLK(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CASPER_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CASPER_CLK_MASK)
#define CLKCTL0_PSCCTL0_HASHCRYPT_CLK_MASK       (0x400U)
#define CLKCTL0_PSCCTL0_HASHCRYPT_CLK_SHIFT      (10U)
/*! HASHCRYPT_CLK - HASHCRYPT clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_HASHCRYPT_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_HASHCRYPT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_HASHCRYPT_CLK_MASK)
#define CLKCTL0_PSCCTL0_PUF_CLK_MASK             (0x800U)
#define CLKCTL0_PSCCTL0_PUF_CLK_SHIFT            (11U)
/*! PUF_CLK - PUF clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_PUF_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_PUF_CLK_SHIFT)) & CLKCTL0_PSCCTL0_PUF_CLK_MASK)
#define CLKCTL0_PSCCTL0_RNG_CLK_MASK             (0x1000U)
#define CLKCTL0_PSCCTL0_RNG_CLK_SHIFT            (12U)
/*! RNG_CLK - Random Number Generator (RNG) clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_RNG_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_RNG_CLK_SHIFT)) & CLKCTL0_PSCCTL0_RNG_CLK_MASK)
#define CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_MASK  (0x10000U)
#define CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_SHIFT (16U)
/*! FLEXSPI0_OTFAD_CLK - FLEXSPI0 / OTFAD clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_FLEXSPI0_OTFAD_CLK_MASK)
#define CLKCTL0_PSCCTL0_OTP_CTLR_CLK_MASK        (0x20000U)
#define CLKCTL0_PSCCTL0_OTP_CTLR_CLK_SHIFT       (17U)
/*! OTP_CTLR_CLK - OTP Controller clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_OTP_CTLR_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_OTP_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_OTP_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_FLEXSPI1_CLK_MASK        (0x40000U)
#define CLKCTL0_PSCCTL0_FLEXSPI1_CLK_SHIFT       (18U)
/*! FLEXSPI1_CLK - FLEXSPI1 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_FLEXSPI1_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_FLEXSPI1_CLK_SHIFT)) & CLKCTL0_PSCCTL0_FLEXSPI1_CLK_MASK)
#define CLKCTL0_PSCCTL0_USBHS_PHY_CLK_MASK       (0x100000U)
#define CLKCTL0_PSCCTL0_USBHS_PHY_CLK_SHIFT      (20U)
/*! USBHS_PHY_CLK - USB HS PHY clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_USBHS_PHY_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_PHY_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_PHY_CLK_MASK)
#define CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_MASK    (0x200000U)
#define CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_SHIFT   (21U)
/*! USBHS_DEVICE_CLK - USB HS Device clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_DEVICE_CLK_MASK)
#define CLKCTL0_PSCCTL0_USBHS_HOST_CLK_MASK      (0x400000U)
#define CLKCTL0_PSCCTL0_USBHS_HOST_CLK_SHIFT     (22U)
/*! USBHS_HOST_CLK - USB HS Host clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_USBHS_HOST_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_HOST_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_HOST_CLK_MASK)
#define CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_MASK      (0x800000U)
#define CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_SHIFT     (23U)
/*! USBHS_SRAM_CLK - USB HS SRAM clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_USBHS_SRAM_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_SHIFT)) & CLKCTL0_PSCCTL0_USBHS_SRAM_CLK_MASK)
#define CLKCTL0_PSCCTL0_SCT_CLK_MASK             (0x1000000U)
#define CLKCTL0_PSCCTL0_SCT_CLK_SHIFT            (24U)
/*! SCT_CLK - SCT clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_SCT_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SCT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SCT_CLK_MASK)
#define CLKCTL0_PSCCTL0_GPU_CLK_MASK             (0x4000000U)
#define CLKCTL0_PSCCTL0_GPU_CLK_SHIFT            (26U)
/*! GPU_CLK - GPU clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_GPU_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_GPU_CLK_SHIFT)) & CLKCTL0_PSCCTL0_GPU_CLK_MASK)
#define CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_MASK    (0x8000000U)
#define CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_SHIFT   (27U)
/*! DISPLAY_CTLR_CLK - Display Controller clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_DISPLAY_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_MASK   (0x10000000U)
#define CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_SHIFT  (28U)
/*! MIPI_DSI_CTLR_CLK - MIPI-DSI Controller clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_MIPI_DSI_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_SMARTDMA_CLK_MASK        (0x40000000U)
#define CLKCTL0_PSCCTL0_SMARTDMA_CLK_SHIFT       (30U)
/*! SMARTDMA_CLK - Smart DMA clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL0_SMARTDMA_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SMARTDMA_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SMARTDMA_CLK_MASK)
/*! @} */

/*! @name PSCCTL1 - Clock Control 1 */
/*! @{ */
#define CLKCTL0_PSCCTL1_SDIO0_CLK_MASK           (0x4U)
#define CLKCTL0_PSCCTL1_SDIO0_CLK_SHIFT          (2U)
/*! SDIO0_CLK - SDIO0 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL1_SDIO0_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SDIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SDIO0_CLK_MASK)
#define CLKCTL0_PSCCTL1_SDIO1_CLK_MASK           (0x8U)
#define CLKCTL0_PSCCTL1_SDIO1_CLK_SHIFT          (3U)
/*! SDIO1_CLK - SDIO1 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL1_SDIO1_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SDIO1_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SDIO1_CLK_MASK)
#define CLKCTL0_PSCCTL1_ACMP0_CLK_MASK           (0x8000U)
#define CLKCTL0_PSCCTL1_ACMP0_CLK_SHIFT          (15U)
/*! ACMP0_CLK - ACMP0 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL1_ACMP0_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ACMP0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_ACMP0_CLK_MASK)
#define CLKCTL0_PSCCTL1_ADC0_CLK_MASK            (0x10000U)
#define CLKCTL0_PSCCTL1_ADC0_CLK_SHIFT           (16U)
/*! ADC0_CLK - ADC0 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL1_ADC0_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_ADC0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_ADC0_CLK_MASK)
#define CLKCTL0_PSCCTL1_SHSGPIO0_CLK_MASK        (0x1000000U)
#define CLKCTL0_PSCCTL1_SHSGPIO0_CLK_SHIFT       (24U)
/*! SHSGPIO0_CLK - SHSGPIO0 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL1_SHSGPIO0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SHSGPIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SHSGPIO0_CLK_MASK)
/*! @} */

/*! @name PSCCTL2 - Clock Control 2 */
/*! @{ */
#define CLKCTL0_PSCCTL2_UTICK0_CLK_MASK          (0x1U)
#define CLKCTL0_PSCCTL2_UTICK0_CLK_SHIFT         (0U)
/*! UTICK0_CLK - Micro-Tick Timer 0 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL2_UTICK0_CLK(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_UTICK0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_UTICK0_CLK_MASK)
#define CLKCTL0_PSCCTL2_WWDT0_CLK_MASK           (0x2U)
#define CLKCTL0_PSCCTL2_WWDT0_CLK_SHIFT          (1U)
/*! WWDT0_CLK - Watchdog Timer 0 clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL2_WWDT0_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_WWDT0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_WWDT0_CLK_MASK)
#define CLKCTL0_PSCCTL2_PMC_CLK_MASK             (0x20000000U)
#define CLKCTL0_PSCCTL2_PMC_CLK_SHIFT            (29U)
/*! PMC_CLK - Power Management Controller clock control
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_PSCCTL2_PMC_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_PMC_CLK_SHIFT)) & CLKCTL0_PSCCTL2_PMC_CLK_MASK)
/*! @} */

/*! @name PSCCTL0_SET - Clock Control 0 Set */
/*! @{ */
#define CLKCTL0_PSCCTL0_SET_DSP_CLK_MASK         (0x2U)
#define CLKCTL0_PSCCTL0_SET_DSP_CLK_SHIFT        (1U)
/*! DSP_CLK - DSP clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_DSP_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_DSP_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_DSP_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_MASK   (0x4U)
#define CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_SHIFT  (2U)
/*! ROM_CTRLR_CLK - 128KB ROM Controller clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_ROM_CTRLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_MASK  (0x8U)
#define CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_SHIFT (3U)
/*! AXI_SWITCH_CLK - AXI Switch clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_AXI_SWITCH_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_MASK    (0x10U)
#define CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_SHIFT   (4U)
/*! AXI_CTLR_CLK - AXI Controller clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_AXI_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_MASK   (0x100U)
#define CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_SHIFT  (8U)
/*! POWERQUAD_CLK - POWERQUAD clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_POWERQUAD_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_CASPER_CLK_MASK      (0x200U)
#define CLKCTL0_PSCCTL0_SET_CASPER_CLK_SHIFT     (9U)
/*! CASPER_CLK - CASPER clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_CASPER_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_CASPER_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_CASPER_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_MASK   (0x400U)
#define CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_SHIFT  (10U)
/*! HASHCRYPT_CLK - HASHCRYPT clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_HASHCRYPT_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_PUF_CLK_MASK         (0x800U)
#define CLKCTL0_PSCCTL0_SET_PUF_CLK_SHIFT        (11U)
/*! PUF_CLK - PUF clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_PUF_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_PUF_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_PUF_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_RNG_CLK_MASK         (0x1000U)
#define CLKCTL0_PSCCTL0_SET_RNG_CLK_SHIFT        (12U)
/*! RNG_CLK - Random Number Generator (RNG) clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_RNG_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_RNG_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_RNG_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK (0x10000U)
#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_SHIFT (16U)
/*! FLEXSPI0_OTFAD_CLK - FLEXSPI0 / OTFAD clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_MASK    (0x20000U)
#define CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_SHIFT   (17U)
/*! OTP_CTLR_CLK - OTP Controller clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_OTP_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK    (0x40000U)
#define CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_SHIFT   (18U)
/*! FLEXSPI1_CLK - FLEXSPI1 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_MASK   (0x100000U)
#define CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_SHIFT  (20U)
/*! USBHS_PHY_CLK - USB HS PHY clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_PHY_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_MASK (0x200000U)
#define CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_SHIFT (21U)
/*! USBHS_DEVICE_CLK - USB HS Device clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_DEVICE_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_MASK  (0x400000U)
#define CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_SHIFT (22U)
/*! USBHS_HOST_CLK - USB HS Host clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_HOST_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_MASK  (0x800000U)
#define CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_SHIFT (23U)
/*! USBHS_SRAM_CLK - USB HS SRAM clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_USBHS_SRAM_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_SCT_CLK_MASK         (0x1000000U)
#define CLKCTL0_PSCCTL0_SET_SCT_CLK_SHIFT        (24U)
/*! SCT_CLK - SCT clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_SCT_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SCT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_SCT_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_GPU_CLK_MASK         (0x4000000U)
#define CLKCTL0_PSCCTL0_SET_GPU_CLK_SHIFT        (26U)
/*! GPU_CLK - GPU clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_GPU_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_GPU_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_GPU_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_MASK (0x8000000U)
#define CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_SHIFT (27U)
/*! DISPLAY_CTLR_CLK - Display Controller clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_DISPLAY_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_MASK (0x10000000U)
#define CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_SHIFT (28U)
/*! MIPI_DSI_CTLR_CLK - MIPI-DSI Controller clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_MIPI_DSI_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_MASK    (0x40000000U)
#define CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_SHIFT   (30U)
/*! SMARTDMA_CLK - Smart DMA clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_SHIFT)) & CLKCTL0_PSCCTL0_SET_SMARTDMA_CLK_MASK)
/*! @} */

/*! @name PSCCTL1_SET - Clock Control 1 Set */
/*! @{ */
#define CLKCTL0_PSCCTL1_SET_SDIO0_CLK_MASK       (0x4U)
#define CLKCTL0_PSCCTL1_SET_SDIO0_CLK_SHIFT      (2U)
/*! SDIO0_CLK - SDIO0 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_SET_SDIO0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SDIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_SDIO0_CLK_MASK)
#define CLKCTL0_PSCCTL1_SET_SDIO1_CLK_MASK       (0x8U)
#define CLKCTL0_PSCCTL1_SET_SDIO1_CLK_SHIFT      (3U)
/*! SDIO1_CLK - SDIO1 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_SET_SDIO1_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SDIO1_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_SDIO1_CLK_MASK)
#define CLKCTL0_PSCCTL1_SET_ACMP0_CLK_MASK       (0x8000U)
#define CLKCTL0_PSCCTL1_SET_ACMP0_CLK_SHIFT      (15U)
/*! ACMP0_CLK - ACMP0 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_SET_ACMP0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ACMP0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_ACMP0_CLK_MASK)
#define CLKCTL0_PSCCTL1_SET_ADC0_CLK_MASK        (0x10000U)
#define CLKCTL0_PSCCTL1_SET_ADC0_CLK_SHIFT       (16U)
/*! ADC0_CLK - ADC0 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_SET_ADC0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_ADC0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_ADC0_CLK_MASK)
#define CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_MASK    (0x1000000U)
#define CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_SHIFT   (24U)
/*! SHSGPIO0_CLK - SHSGPIO0 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_SET_SHSGPIO0_CLK_MASK)
/*! @} */

/*! @name PSCCTL2_SET - Clock Control 2 Set */
/*! @{ */
#define CLKCTL0_PSCCTL2_SET_UTICK0_CLK_MASK      (0x1U)
#define CLKCTL0_PSCCTL2_SET_UTICK0_CLK_SHIFT     (0U)
/*! UTICK0_CLK - Micro-Tick Timer 0 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL2 register
 */
#define CLKCTL0_PSCCTL2_SET_UTICK0_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_UTICK0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_SET_UTICK0_CLK_MASK)
#define CLKCTL0_PSCCTL2_SET_WWDT0_CLK_MASK       (0x2U)
#define CLKCTL0_PSCCTL2_SET_WWDT0_CLK_SHIFT      (1U)
/*! WWDT0_CLK - Watchdog Timer 0 clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL2 register
 */
#define CLKCTL0_PSCCTL2_SET_WWDT0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_WWDT0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_SET_WWDT0_CLK_MASK)
#define CLKCTL0_PSCCTL2_SET_PMC_MASK             (0x20000000U)
#define CLKCTL0_PSCCTL2_SET_PMC_SHIFT            (29U)
/*! PMC - Power Management Controller clock set
 *  0b0..No effect
 *  0b1..Sets the corresponding bit in PSCCTL2 register
 */
#define CLKCTL0_PSCCTL2_SET_PMC(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_PMC_SHIFT)) & CLKCTL0_PSCCTL2_SET_PMC_MASK)
/*! @} */

/*! @name PSCCTL0_CLR - Clock Control 0 Clear */
/*! @{ */
#define CLKCTL0_PSCCTL0_CLR_DSP_CLK_MASK         (0x2U)
#define CLKCTL0_PSCCTL0_CLR_DSP_CLK_SHIFT        (1U)
/*! DSP_CLK - DSP clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_DSP_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_DSP_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_DSP_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_MASK   (0x4U)
#define CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_SHIFT  (2U)
/*! ROM_CTRLR_CLK - 128KB ROM Controller clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_ROM_CTRLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_MASK  (0x8U)
#define CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_SHIFT (3U)
/*! AXI_SWITCH_CLK - AXI Switch clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_AXI_SWITCH_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_MASK    (0x10U)
#define CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_SHIFT   (4U)
/*! AXI_CTLR_CLK - AXI Controller clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_AXI_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_MASK   (0x100U)
#define CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_SHIFT  (8U)
/*! POWERQUAD_CLK - POWERQUAD clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_POWERQUAD_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_CASPER_CLK_MASK      (0x200U)
#define CLKCTL0_PSCCTL0_CLR_CASPER_CLK_SHIFT     (9U)
/*! CASPER_CLK - CASPER clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_CASPER_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_CASPER_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_CASPER_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_MASK   (0x400U)
#define CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_SHIFT  (10U)
/*! HASHCRYPT_CLK - HASHCRYPT clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_HASHCRYPT_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_PUF_CLK_MASK         (0x800U)
#define CLKCTL0_PSCCTL0_CLR_PUF_CLK_SHIFT        (11U)
/*! PUF_CLK - PUF clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_PUF_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_PUF_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_PUF_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_RNG_CLK_MASK         (0x1000U)
#define CLKCTL0_PSCCTL0_CLR_RNG_CLK_SHIFT        (12U)
/*! RNG_CLK - RNG clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_RNG_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_RNG_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_RNG_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK (0x10000U)
#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_SHIFT (16U)
/*! FLEXSPI0_OTFAD_CLK - FLEXSPI0 / OTFAD clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_MASK    (0x20000U)
#define CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_SHIFT   (17U)
/*! OTP_CTLR_CLK - OTP Controller clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_OTP_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK    (0x40000U)
#define CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_SHIFT   (18U)
/*! FLEXSPI1_CLK - FLEXSPI1 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_MASK   (0x100000U)
#define CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_SHIFT  (20U)
/*! USBHS_PHY_CLK - USB HS PHY clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_PHY_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_MASK (0x200000U)
#define CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_SHIFT (21U)
/*! USBHS_DEVICE_CLK - USB HS Device clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_DEVICE_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_MASK  (0x400000U)
#define CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_SHIFT (22U)
/*! USBHS_HOST_CLK - USB HS Host clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_HOST_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_MASK  (0x800000U)
#define CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_SHIFT (23U)
/*! USBHS_SRAM_CLK - USB HS SRAM clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK(x)    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_USBHS_SRAM_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_SCT_CLK_MASK         (0x1000000U)
#define CLKCTL0_PSCCTL0_CLR_SCT_CLK_SHIFT        (24U)
/*! SCT_CLK - SCT clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_SCT_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SCT_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SCT_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_GPU_CLK_MASK         (0x4000000U)
#define CLKCTL0_PSCCTL0_CLR_GPU_CLK_SHIFT        (26U)
/*! GPU_CLK - GPU clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_GPU_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_GPU_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_GPU_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_MASK (0x8000000U)
#define CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_SHIFT (27U)
/*! DISPLAY_CTLR_CLK - Display Controller clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_DISPLAY_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_MASK (0x10000000U)
#define CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_SHIFT (28U)
/*! MIPI_DSI_CTLR_CLK - MIPI-DSI Controller clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_MIPI_DSI_CTLR_CLK_MASK)
#define CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_MASK    (0x40000000U)
#define CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_SHIFT   (30U)
/*! SMARTDMA_CLK - Smart DMA clock set
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL0 register
 */
#define CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_SHIFT)) & CLKCTL0_PSCCTL0_CLR_SMARTDMA_CLK_MASK)
/*! @} */

/*! @name PSCCTL1_CLR - Clock Control 1 Clear */
/*! @{ */
#define CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_MASK       (0x4U)
#define CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_SHIFT      (2U)
/*! SDIO0_CLK - SDIO0 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_CLR_SDIO0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SDIO0_CLK_MASK)
#define CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_MASK       (0x8U)
#define CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_SHIFT      (3U)
/*! SDIO1_CLK - SDIO1 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_CLR_SDIO1_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SDIO1_CLK_MASK)
#define CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_MASK       (0x8000U)
#define CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_SHIFT      (15U)
/*! ACMP0_CLK - ACMP0 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_CLR_ACMP0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ACMP0_CLK_MASK)
#define CLKCTL0_PSCCTL1_CLR_ADC0_CLK_MASK        (0x10000U)
#define CLKCTL0_PSCCTL1_CLR_ADC0_CLK_SHIFT       (16U)
/*! ADC0_CLK - ADC0 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_CLR_ADC0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_ADC0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_ADC0_CLK_MASK)
#define CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_MASK    (0x1000000U)
#define CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_SHIFT   (24U)
/*! SHSGPIO0_CLK - SHSGPIO0 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL1 register
 */
#define CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_SHIFT)) & CLKCTL0_PSCCTL1_CLR_SHSGPIO0_CLK_MASK)
/*! @} */

/*! @name PSCCTL2_CLR - Clock Control 2 Clear */
/*! @{ */
#define CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_MASK      (0x1U)
#define CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_SHIFT     (0U)
/*! UTICK0_CLK - Micro-Tick Timer 0 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL2 register
 */
#define CLKCTL0_PSCCTL2_CLR_UTICK0_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_UTICK0_CLK_MASK)
#define CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_MASK       (0x2U)
#define CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_SHIFT      (1U)
/*! WWDT0_CLK - Watchdog Timer 0 clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL2 register
 */
#define CLKCTL0_PSCCTL2_CLR_WWDT0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_WWDT0_CLK_MASK)
#define CLKCTL0_PSCCTL2_CLR_PMC_CLK_MASK         (0x20000000U)
#define CLKCTL0_PSCCTL2_CLR_PMC_CLK_SHIFT        (29U)
/*! PMC_CLK - Power Management Controller clock clear
 *  0b0..No effect
 *  0b1..Clears the corresponding bit in PSCCTL2 register
 */
#define CLKCTL0_PSCCTL2_CLR_PMC_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_PMC_CLK_SHIFT)) & CLKCTL0_PSCCTL2_CLR_PMC_CLK_MASK)
/*! @} */

/*! @name FRO_CONTROL - Free Running Oscillator Control */
/*! @{ */
#define CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK       (0xFFFFU)
#define CLKCTL0_FRO_CONTROL_EXP_COUNT_SHIFT      (0U)
/*! EXP_COUNT - Expected Count
 */
#define CLKCTL0_FRO_CONTROL_EXP_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_EXP_COUNT_SHIFT)) & CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK)
#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_MASK (0x1F0000U)
#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_SHIFT (16U)
/*! THRESH_RANGE_UP - Threshold Range Upper Limit
 */
#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP(x)   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_SHIFT)) & CLKCTL0_FRO_CONTROL_THRESH_RANGE_UP_MASK)
#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_MASK (0x3E00000U)
#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_SHIFT (21U)
/*! THRESH_RANGE_LOW - Threshold Range Lower Limit
 */
#define CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW(x)  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_SHIFT)) & CLKCTL0_FRO_CONTROL_THRESH_RANGE_LOW_MASK)
#define CLKCTL0_FRO_CONTROL_ENA_TUNE_MASK        (0x80000000U)
#define CLKCTL0_FRO_CONTROL_ENA_TUNE_SHIFT       (31U)
/*! ENA_TUNE - Enable Tuning
 *  0b0..Stop tuning
 *  0b1..Start tuning
 */
#define CLKCTL0_FRO_CONTROL_ENA_TUNE(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CONTROL_ENA_TUNE_SHIFT)) & CLKCTL0_FRO_CONTROL_ENA_TUNE_MASK)
/*! @} */

/*! @name FRO_CAPVAL - Free Running Oscillator Captured Value */
/*! @{ */
#define CLKCTL0_FRO_CAPVAL_CAPVAL_MASK           (0xFFFFU)
#define CLKCTL0_FRO_CAPVAL_CAPVAL_SHIFT          (0U)
/*! CAPVAL - Captured Value
 */
#define CLKCTL0_FRO_CAPVAL_CAPVAL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CAPVAL_CAPVAL_SHIFT)) & CLKCTL0_FRO_CAPVAL_CAPVAL_MASK)
#define CLKCTL0_FRO_CAPVAL_DATA_VALID_MASK       (0x80000000U)
#define CLKCTL0_FRO_CAPVAL_DATA_VALID_SHIFT      (31U)
/*! DATA_VALID - Data Valid
 *  0b0..CAPVAL data is not valid
 *  0b1..CAPVAL data is valid
 */
#define CLKCTL0_FRO_CAPVAL_DATA_VALID(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_CAPVAL_DATA_VALID_SHIFT)) & CLKCTL0_FRO_CAPVAL_DATA_VALID_MASK)
/*! @} */

/*! @name FRO_RDTRIM - Free Running Oscillator Trim */
/*! @{ */
#define CLKCTL0_FRO_RDTRIM_TRIM_MASK             (0x7FFU)
#define CLKCTL0_FRO_RDTRIM_TRIM_SHIFT            (0U)
/*! TRIM - It is the trim value supplied to the oscillator
 */
#define CLKCTL0_FRO_RDTRIM_TRIM(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRO_RDTRIM_TRIM_SHIFT)) & CLKCTL0_FRO_RDTRIM_TRIM_MASK)
/*! @} */

/*! @name FRODIVSEL - FRO Clock Divider */
/*! @{ */
#define CLKCTL0_FRODIVSEL_SEL_MASK               (0x3U)
#define CLKCTL0_FRODIVSEL_SEL_SHIFT              (0U)
/*! SEL - Select clock
 *  0b00..FRO Clock Divided by 2
 *  0b01..FRO Clock Divided by 4
 *  0b10..FRO Clock Divided by 8
 *  0b11..FRO Clock Divided by 16
 */
#define CLKCTL0_FRODIVSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVSEL_SEL_SHIFT)) & CLKCTL0_FRODIVSEL_SEL_MASK)
/*! @} */

/*! @name FROCLKSTATUS - FRO Clock Status */
/*! @{ */
#define CLKCTL0_FROCLKSTATUS_CLK_OK_MASK         (0x1U)
#define CLKCTL0_FROCLKSTATUS_CLK_OK_SHIFT        (0U)
/*! CLK_OK - FRO Clock OK
 *  0b0..FRO clock has not yet reached its final frequency
 *  0b1..FRO clock has reached its final frequency
 */
#define CLKCTL0_FROCLKSTATUS_CLK_OK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FROCLKSTATUS_CLK_OK_SHIFT)) & CLKCTL0_FROCLKSTATUS_CLK_OK_MASK)
/*! @} */

/*! @name FRODIVOEN - FRO Enable Register */
/*! @{ */
#define CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK     (0x1U)
#define CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_SHIFT    (0U)
/*! FRO_DIV1_O_EN - FRO Divided-by-1 Clock Enable
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV1_O_EN_MASK)
#define CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK     (0x2U)
#define CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_SHIFT    (1U)
/*! FRO_DIV2_O_EN - FRO Divided-by-2 Clock Enable
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV2_O_EN_MASK)
#define CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK     (0x4U)
#define CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_SHIFT    (2U)
/*! FRO_DIV4_O_EN - FRO Divided-by-4 Clock Enable
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV4_O_EN_MASK)
#define CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK     (0x8U)
#define CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_SHIFT    (3U)
/*! FRO_DIV8_O_EN - FRO Divided-by-8 Clock Enable
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV8_O_EN_MASK)
#define CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK    (0x10U)
#define CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_SHIFT   (4U)
/*! FRO_DIV16_O_EN - FRO Divided-by-16 Clock Enable
 *  0b0..Disable clock
 *  0b1..Enable clock
 */
#define CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_SHIFT)) & CLKCTL0_FRODIVOEN_FRO_DIV16_O_EN_MASK)
/*! @} */

/*! @name LOWFREQCLKDIV - Low Frequency Clock Divider */
/*! @{ */
#define CLKCTL0_LOWFREQCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL0_LOWFREQCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Low Frequency Clock Divider Value
 */
#define CLKCTL0_LOWFREQCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_DIV_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_DIV_MASK)
#define CLKCTL0_LOWFREQCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL0_LOWFREQCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_LOWFREQCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_RESET_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_RESET_MASK)
#define CLKCTL0_LOWFREQCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL0_LOWFREQCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_LOWFREQCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_HALT_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_HALT_MASK)
#define CLKCTL0_LOWFREQCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL0_LOWFREQCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished
 *  0b1..The Divider value has changed
 */
#define CLKCTL0_LOWFREQCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LOWFREQCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_LOWFREQCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SYSOSCCTL0 - System Oscillator Control 0 */
/*! @{ */
#define CLKCTL0_SYSOSCCTL0_LP_ENABLE_MASK        (0x1U)
#define CLKCTL0_SYSOSCCTL0_LP_ENABLE_SHIFT       (0U)
/*! LP_ENABLE - Low Power Mode Enable
 *  0b0..Enable High Gain Mode (HP)
 *  0b1..Enable Low Power mode (LP)
 */
#define CLKCTL0_SYSOSCCTL0_LP_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCCTL0_LP_ENABLE_SHIFT)) & CLKCTL0_SYSOSCCTL0_LP_ENABLE_MASK)
#define CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_MASK    (0x2U)
#define CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_SHIFT   (1U)
/*! BYPASS_ENABLE - Bypass Enable
 *  0b0..Enable Normal mode. Oscillation with crystal connected.
 *  0b1..Enable Bypass mode. In this mode a clock can be directly input into the XTALIN pin.
 */
#define CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_SHIFT)) & CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_MASK)
/*! @} */

/*! @name SYSOSCBYPASS - OSC Clock Source Select */
/*! @{ */
#define CLKCTL0_SYSOSCBYPASS_SEL_MASK            (0x7U)
#define CLKCTL0_SYSOSCBYPASS_SEL_SHIFT           (0U)
/*! SEL - Select SYSOSC Bypass
 *  0b000..Select OSC Clock
 *  0b001..Select Clock IN clock
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed
 */
#define CLKCTL0_SYSOSCBYPASS_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSOSCBYPASS_SEL_SHIFT)) & CLKCTL0_SYSOSCBYPASS_SEL_MASK)
/*! @} */

/*! @name LPOSCCTL0 - Low Power Oscillator Control 0 */
/*! @{ */
#define CLKCTL0_LPOSCCTL0_CLKRDY_MASK            (0x80000000U)
#define CLKCTL0_LPOSCCTL0_CLKRDY_SHIFT           (31U)
/*! CLKRDY - LPOSC Clock Ready
 *  0b0..LPOSC clock is not ready
 *  0b1..LPOSC clock is ready
 */
#define CLKCTL0_LPOSCCTL0_CLKRDY(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_LPOSCCTL0_CLKRDY_SHIFT)) & CLKCTL0_LPOSCCTL0_CLKRDY_MASK)
/*! @} */

/*! @name OSC32KHZCTL0 - 32 KHz Oscillator Control 0 */
/*! @{ */
#define CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK       (0x1U)
#define CLKCTL0_OSC32KHZCTL0_ENA32KHZ_SHIFT      (0U)
/*! ENA32KHZ - 32 KHz Oscillator Enable
 *  0b0..Disable oscillator
 *  0b1..Enable oscillator
 */
#define CLKCTL0_OSC32KHZCTL0_ENA32KHZ(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_OSC32KHZCTL0_ENA32KHZ_SHIFT)) & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK)
/*! @} */

/*! @name SYSPLL0CLKSEL - System PLL 0 Clock Select */
/*! @{ */
#define CLKCTL0_SYSPLL0CLKSEL_SEL_MASK           (0x7U)
#define CLKCTL0_SYSPLL0CLKSEL_SEL_SHIFT          (0U)
/*! SEL - System PLL0 Reference Input Clock Source
 *  0b000..FRO Clock (Divided-by-8 selection)
 *  0b001..OSC_CLK clock
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL0_SYSPLL0CLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CLKSEL_SEL_SHIFT)) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
/*! @} */

/*! @name SYSPLL0CTL0 - System PLL0 Control 0 */
/*! @{ */
#define CLKCTL0_SYSPLL0CTL0_BYPASS_MASK          (0x1U)
#define CLKCTL0_SYSPLL0CTL0_BYPASS_SHIFT         (0U)
/*! BYPASS - SYSPLL0 BYPASS Mode
 *  0b0..PFD outputs are PFD-programmed clocks
 *  0b1..Bypass Mode: PFD outputs are sourced directly from rhe reference input clock
 */
#define CLKCTL0_SYSPLL0CTL0_BYPASS(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_BYPASS_SHIFT)) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK)
#define CLKCTL0_SYSPLL0CTL0_RESET_MASK           (0x2U)
#define CLKCTL0_SYSPLL0CTL0_RESET_SHIFT          (1U)
/*! RESET - SYSPLL0 Reset
 *  0b0..SYSPLL0 reset is removed
 *  0b1..SYSPLL0 is placed into reset
 */
#define CLKCTL0_SYSPLL0CTL0_RESET(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_RESET_SHIFT)) & CLKCTL0_SYSPLL0CTL0_RESET_MASK)
#define CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK (0x2000U)
#define CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_SHIFT (13U)
/*! HOLDRINGOFF_ENA - Hold Ring Off Control
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA(x)   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_SHIFT)) & CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK)
#define CLKCTL0_SYSPLL0CTL0_MULT_MASK            (0xFF0000U)
#define CLKCTL0_SYSPLL0CTL0_MULT_SHIFT           (16U)
/*! MULT - Multiplication Factor for FSYSPLL0_OUTPUT
 *  0b00010000..Divide by 16
 *  0b00010001..Divide by 17
 *  0b00010100..Divide by 20
 *  0b00010110..Divide by 22
 *  0b00011011..Divide by 27
 *  0b00100001..Divide by 33
 */
#define CLKCTL0_SYSPLL0CTL0_MULT(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0CTL0_MULT_SHIFT)) & CLKCTL0_SYSPLL0CTL0_MULT_MASK)
/*! @} */

/*! @name SYSPLL0LOCKTIMEDIV2 - System PLL0 Lock Time Div2 */
/*! @{ */
#define CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
#define CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
/*! LOCKTIMEDIV2 - SYSPLL0 Lock Time Divide-by-2
 */
#define CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
/*! @} */

/*! @name SYSPLL0NUM - System PLL0 Numerator */
/*! @{ */
#define CLKCTL0_SYSPLL0NUM_NUM_MASK              (0x3FFFFFFFU)
#define CLKCTL0_SYSPLL0NUM_NUM_SHIFT             (0U)
/*! NUM - Numerator of the SYSPLL0 fractional loop divider
 */
#define CLKCTL0_SYSPLL0NUM_NUM(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0NUM_NUM_SHIFT)) & CLKCTL0_SYSPLL0NUM_NUM_MASK)
/*! @} */

/*! @name SYSPLL0DENOM - System PLL0 Denominator */
/*! @{ */
#define CLKCTL0_SYSPLL0DENOM_DENOM_MASK          (0x3FFFFFFFU)
#define CLKCTL0_SYSPLL0DENOM_DENOM_SHIFT         (0U)
/*! DENOM - Denominator of the SYSPLL0 fractional loop divider
 */
#define CLKCTL0_SYSPLL0DENOM_DENOM(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0DENOM_DENOM_SHIFT)) & CLKCTL0_SYSPLL0DENOM_DENOM_MASK)
/*! @} */

/*! @name SYSPLL0PFD - System PLL0 PFD */
/*! @{ */
#define CLKCTL0_SYSPLL0PFD_PFD0_MASK             (0x3FU)
#define CLKCTL0_SYSPLL0PFD_PFD0_SHIFT            (0U)
/*! PFD0 - PLL Fractional Divider 0
 */
#define CLKCTL0_SYSPLL0PFD_PFD0(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD0_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK      (0x40U)
#define CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_SHIFT     (6U)
/*! PFD0_CLKRDY - PFD0 Clock Ready Status Flag
 *  0b0..PFD0 clock is not ready
 *  0b1..PFD0 clock is ready
 */
#define CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK     (0x80U)
#define CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_SHIFT    (7U)
/*! PFD0_CLKGATE - PFD0 Clock Gate
 *  0b0..PFD0 clock is not gated
 *  0b1..PFD0 clock is gated
 */
#define CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD1_MASK             (0x3F00U)
#define CLKCTL0_SYSPLL0PFD_PFD1_SHIFT            (8U)
/*! PFD1 - PLL Fractional Divider 1
 */
#define CLKCTL0_SYSPLL0PFD_PFD1(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD1_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_MASK      (0x4000U)
#define CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_SHIFT     (14U)
/*! PFD1_CLKRDY - PFD1 Clock Ready Status Flag
 *  0b0..PFD1 clock is not ready
 *  0b1..PFD1 clock is ready
 */
#define CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD1_CLKRDY_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK     (0x8000U)
#define CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_SHIFT    (15U)
/*! PFD1_CLKGATE - PFD1 Clock Gate
 *  0b0..PFD1 clock is not gated
 *  0b1..PFD1 clock is gated
 */
#define CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD2_MASK             (0x3F0000U)
#define CLKCTL0_SYSPLL0PFD_PFD2_SHIFT            (16U)
/*! PFD2 - PLL Fractional Divider 2
 */
#define CLKCTL0_SYSPLL0PFD_PFD2(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD2_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD2_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_MASK      (0x400000U)
#define CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_SHIFT     (22U)
/*! PFD2_CLKRDY - PFD2 Clock Ready Status Flag
 *  0b0..PFD2 clock is not ready
 *  0b1..PFD2 clock is ready
 */
#define CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD2_CLKRDY_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK     (0x800000U)
#define CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_SHIFT    (23U)
/*! PFD2_CLKGATE - PFD2 Clock Gate
 *  0b0..PFD2 clock is not gated
 *  0b1..PFD2 clock is gated
 */
#define CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD3_MASK             (0x3F000000U)
#define CLKCTL0_SYSPLL0PFD_PFD3_SHIFT            (24U)
/*! PFD3 - PLL Fractional Divider 3
 */
#define CLKCTL0_SYSPLL0PFD_PFD3(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD3_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD3_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_MASK      (0x40000000U)
#define CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_SHIFT     (30U)
/*! PFD3_CLKRDY - PFD3 Clock Ready Status Flag
 *  0b0..PFD3 clock is not ready
 *  0b1..PFD3 clock is ready
 */
#define CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD3_CLKRDY_MASK)
#define CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_MASK     (0x80000000U)
#define CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_SHIFT    (31U)
/*! PFD3_CLKGATE - PFD3 Clock Gate
 *  0b0..PFD3 clock is not gated
 *  0b1..PFD3 clock is gated
 */
#define CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_SHIFT)) & CLKCTL0_SYSPLL0PFD_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name SYSCPUAHBCLKDIV - System CPU AHB Clock Divider */
/*! @{ */
#define CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL0_SYSCPUAHBCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_SYSCPUAHBCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSCPUAHBCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK)
#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSCPUAHBCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name MAINCLKSELA - Main Clock Select A */
/*! @{ */
#define CLKCTL0_MAINCLKSELA_SEL_MASK             (0x3U)
#define CLKCTL0_MAINCLKSELA_SEL_SHIFT            (0U)
/*! SEL - Control Main 1st Stage Control Clock Source
 *  0b00..Low Power Oscillator Clock (LPOSC)
 *  0b01..FRODIV which is the output of the FRODIVSEL mux
 *  0b10..OSC_CLK clock
 *  0b11..FRO clock
 */
#define CLKCTL0_MAINCLKSELA_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSELA_SEL_SHIFT)) & CLKCTL0_MAINCLKSELA_SEL_MASK)
/*! @} */

/*! @name MAINCLKSELB - Main Clock Select B */
/*! @{ */
#define CLKCTL0_MAINCLKSELB_SEL_MASK             (0x3U)
#define CLKCTL0_MAINCLKSELB_SEL_SHIFT            (0U)
/*! SEL - Main Clock Source Selection
 *  0b00..MAINCLKSELA 1st Stage Clock
 *  0b01..Main System PLL Clock
 *  0b10..RTC 32 KHz Clock
 *  0b11..Reserved
 */
#define CLKCTL0_MAINCLKSELB_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_MAINCLKSELB_SEL_SHIFT)) & CLKCTL0_MAINCLKSELB_SEL_MASK)
/*! @} */

/*! @name PFCDIV - PFC0DIV..PFC1DIV */
/*! @{ */
#define CLKCTL0_PFCDIV_DIV_MASK                  (0xFFU)
#define CLKCTL0_PFCDIV_DIV_SHIFT                 (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_PFCDIV_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_DIV_SHIFT)) & CLKCTL0_PFCDIV_DIV_MASK)
#define CLKCTL0_PFCDIV_RESET_MASK                (0x20000000U)
#define CLKCTL0_PFCDIV_RESET_SHIFT               (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_PFCDIV_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_RESET_SHIFT)) & CLKCTL0_PFCDIV_RESET_MASK)
#define CLKCTL0_PFCDIV_HALT_MASK                 (0x40000000U)
#define CLKCTL0_PFCDIV_HALT_SHIFT                (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_PFCDIV_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_HALT_SHIFT)) & CLKCTL0_PFCDIV_HALT_MASK)
#define CLKCTL0_PFCDIV_REQFLAG_MASK              (0x80000000U)
#define CLKCTL0_PFCDIV_REQFLAG_SHIFT             (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_PFCDIV_REQFLAG(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PFCDIV_REQFLAG_SHIFT)) & CLKCTL0_PFCDIV_REQFLAG_MASK)
/*! @} */

/* The count of CLKCTL0_PFCDIV */
#define CLKCTL0_PFCDIV_COUNT                     (2U)

/*! @name FLEXSPI0FCLKSEL - FlexSPI0 Functional Clock Select */
/*! @{ */
#define CLKCTL0_FLEXSPI0FCLKSEL_SEL_MASK         (0x7U)
#define CLKCTL0_FLEXSPI0FCLKSEL_SEL_SHIFT        (0U)
/*! SEL - Select Clock Source
 *  0b000..Main Clock
 *  0b001..Main System PLL Clock
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..FRO_192M Clock
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_FLEXSPI0FCLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKSEL_SEL_SHIFT)) & CLKCTL0_FLEXSPI0FCLKSEL_SEL_MASK)
/*! @} */

/*! @name FLEXSPI0FCLKDIV - FlexSPI0 Functional Clock Divider */
/*! @{ */
#define CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL0_FLEXSPI0FCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_FLEXSPI0FCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_DIV_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK)
#define CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK       (0x20000000U)
#define CLKCTL0_FLEXSPI0FCLKDIV_RESET_SHIFT      (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_FLEXSPI0FCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_RESET_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK)
#define CLKCTL0_FLEXSPI0FCLKDIV_HALT_MASK        (0x40000000U)
#define CLKCTL0_FLEXSPI0FCLKDIV_HALT_SHIFT       (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_FLEXSPI0FCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_HALT_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_HALT_MASK)
#define CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name FLEXSPI1FCLKSEL - FlexSPI1 Functional Clock Select */
/*! @{ */
#define CLKCTL0_FLEXSPI1FCLKSEL_SEL_MASK         (0x7U)
#define CLKCTL0_FLEXSPI1FCLKSEL_SEL_SHIFT        (0U)
/*! SEL - Select Clock Source
 *  0b000..Main Clock
 *  0b001..Main System PLL Clock
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..FRO_192M Clock
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_FLEXSPI1FCLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKSEL_SEL_SHIFT)) & CLKCTL0_FLEXSPI1FCLKSEL_SEL_MASK)
/*! @} */

/*! @name FLEXSPI1FCLKDIV - FlexSPI1 Functional Clock Divider */
/*! @{ */
#define CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL0_FLEXSPI1FCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_FLEXSPI1FCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_DIV_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK)
#define CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK       (0x20000000U)
#define CLKCTL0_FLEXSPI1FCLKDIV_RESET_SHIFT      (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_FLEXSPI1FCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_RESET_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK)
#define CLKCTL0_FLEXSPI1FCLKDIV_HALT_MASK        (0x40000000U)
#define CLKCTL0_FLEXSPI1FCLKDIV_HALT_SHIFT       (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_FLEXSPI1FCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_HALT_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_HALT_MASK)
#define CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SCTFCLKSEL - SCT Functional Clock Select */
/*! @{ */
#define CLKCTL0_SCTFCLKSEL_SEL_MASK              (0x7U)
#define CLKCTL0_SCTFCLKSEL_SEL_SHIFT             (0U)
/*! SEL - Select Clock Source
 *  0b000..Main Clock
 *  0b001..Main System PLL Clock
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..FRO Clock
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..AUDIO PLL Clock
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_SCTFCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTFCLKSEL_SEL_SHIFT)) & CLKCTL0_SCTFCLKSEL_SEL_MASK)
/*! @} */

/*! @name SCTIN7CLKDIV - SCT Functional Clock Divider */
/*! @{ */
#define CLKCTL0_SCTIN7CLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_SCTIN7CLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_SCTIN7CLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_DIV_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_DIV_MASK)
#define CLKCTL0_SCTIN7CLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_SCTIN7CLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_SCTIN7CLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_RESET_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_RESET_MASK)
#define CLKCTL0_SCTIN7CLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_SCTIN7CLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_SCTIN7CLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_HALT_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_HALT_MASK)
#define CLKCTL0_SCTIN7CLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_SCTIN7CLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_SCTIN7CLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SCTIN7CLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SCTIN7CLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name USBHSFCLKSEL - High Speed USB Functional Clock Select */
/*! @{ */
#define CLKCTL0_USBHSFCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL0_USBHSFCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b000..OSC_CLK Clock
 *  0b001..Main Clock
 *  0b010..Reserved
 *  0b011..AUX0_PLL_CLOCK
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_USBHSFCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKSEL_SEL_SHIFT)) & CLKCTL0_USBHSFCLKSEL_SEL_MASK)
/*! @} */

/*! @name USBHSFCLKDIV - High Speed USB Functional Clock Divider */
/*! @{ */
#define CLKCTL0_USBHSFCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_USBHSFCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_USBHSFCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_DIV_SHIFT)) & CLKCTL0_USBHSFCLKDIV_DIV_MASK)
#define CLKCTL0_USBHSFCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_USBHSFCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_USBHSFCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_RESET_SHIFT)) & CLKCTL0_USBHSFCLKDIV_RESET_MASK)
#define CLKCTL0_USBHSFCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_USBHSFCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_USBHSFCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_HALT_SHIFT)) & CLKCTL0_USBHSFCLKDIV_HALT_MASK)
#define CLKCTL0_USBHSFCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_USBHSFCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_USBHSFCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_USBHSFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_USBHSFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SDIO0FCLKSEL - SDIO0 Functional Clock Select */
/*! @{ */
#define CLKCTL0_SDIO0FCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL0_SDIO0FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b000..Main Clock
 *  0b001..System PLL Clock
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..FRO Clock Divided by 2
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_SDIO0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKSEL_SEL_SHIFT)) & CLKCTL0_SDIO0FCLKSEL_SEL_MASK)
/*! @} */

/*! @name SDIO0FCLKDIV - SDIO0 Functional Clock Divider */
/*! @{ */
#define CLKCTL0_SDIO0FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_SDIO0FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_SDIO0FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_DIV_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_DIV_MASK)
#define CLKCTL0_SDIO0FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_SDIO0FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_SDIO0FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_RESET_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_RESET_MASK)
#define CLKCTL0_SDIO0FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_SDIO0FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_SDIO0FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_HALT_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_HALT_MASK)
#define CLKCTL0_SDIO0FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_SDIO0FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_SDIO0FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SDIO0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SDIO1FCLKSEL - SDIO1 Functional Clock Select */
/*! @{ */
#define CLKCTL0_SDIO1FCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL0_SDIO1FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b000..Main Clock
 *  0b001..Main System PLL Clock
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..FRO Clock Divided by 2
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_SDIO1FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKSEL_SEL_SHIFT)) & CLKCTL0_SDIO1FCLKSEL_SEL_MASK)
/*! @} */

/*! @name SDIO1FCLKDIV - SDIO1 Functional Clock Divider */
/*! @{ */
#define CLKCTL0_SDIO1FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL0_SDIO1FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_SDIO1FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_DIV_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_DIV_MASK)
#define CLKCTL0_SDIO1FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL0_SDIO1FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_SDIO1FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_RESET_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_RESET_MASK)
#define CLKCTL0_SDIO1FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL0_SDIO1FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_SDIO1FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_HALT_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_HALT_MASK)
#define CLKCTL0_SDIO1FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL0_SDIO1FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_SDIO1FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SDIO1FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SDIO1FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name ADC0FCLKSEL0 - ADC0 Functional Clock Select 0 */
/*! @{ */
#define CLKCTL0_ADC0FCLKSEL0_SEL_MASK            (0x7U)
#define CLKCTL0_ADC0FCLKSEL0_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b000..OSC_CLK Clock
 *  0b001..Low Power Oscillator Clock (LPOSC)
 *  0b010..FRO Clock Divided by 4
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_ADC0FCLKSEL0_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKSEL0_SEL_SHIFT)) & CLKCTL0_ADC0FCLKSEL0_SEL_MASK)
/*! @} */

/*! @name ADC0FCLKSEL1 - ADC0 Functional Clock Select 1 */
/*! @{ */
#define CLKCTL0_ADC0FCLKSEL1_SEL_MASK            (0x7U)
#define CLKCTL0_ADC0FCLKSEL1_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b000..ADC0FCLKSEL0 Multiplexed Output
 *  0b001..SYSPLL0 MAIN_CLK (PFD0 Output)
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..SYSPLL0 AUX1_PLL_Clock
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_ADC0FCLKSEL1_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKSEL1_SEL_SHIFT)) & CLKCTL0_ADC0FCLKSEL1_SEL_MASK)
/*! @} */

/*! @name ADC0FCLKDIV - ADC0 Functional Clock Divider */
/*! @{ */
#define CLKCTL0_ADC0FCLKDIV_DIV_MASK             (0xFFU)
#define CLKCTL0_ADC0FCLKDIV_DIV_SHIFT            (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_ADC0FCLKDIV_DIV(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
#define CLKCTL0_ADC0FCLKDIV_RESET_MASK           (0x20000000U)
#define CLKCTL0_ADC0FCLKDIV_RESET_SHIFT          (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_ADC0FCLKDIV_RESET(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_RESET_SHIFT)) & CLKCTL0_ADC0FCLKDIV_RESET_MASK)
#define CLKCTL0_ADC0FCLKDIV_HALT_MASK            (0x40000000U)
#define CLKCTL0_ADC0FCLKDIV_HALT_SHIFT           (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_ADC0FCLKDIV_HALT(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_HALT_SHIFT)) & CLKCTL0_ADC0FCLKDIV_HALT_MASK)
#define CLKCTL0_ADC0FCLKDIV_REQFLAG_MASK         (0x80000000U)
#define CLKCTL0_ADC0FCLKDIV_REQFLAG_SHIFT        (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_ADC0FCLKDIV_REQFLAG(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_ADC0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name UTICKFCLKSEL - UTICK Functional Clock Select */
/*! @{ */
#define CLKCTL0_UTICKFCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL0_UTICKFCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Select Clock Source
 *  0b000..Low Power Oscillator Clock (LPOSC)
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_UTICKFCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_UTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_UTICKFCLKSEL_SEL_MASK)
/*! @} */

/*! @name WDT0FCLKSEL - WDT0 Functional Clock Select */
/*! @{ */
#define CLKCTL0_WDT0FCLKSEL_SEL_MASK             (0x7U)
#define CLKCTL0_WDT0FCLKSEL_SEL_SHIFT            (0U)
/*! SEL - Select Clock Source
 *  0b000..Low Power Oscillator Clock (LPOSC)
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_WDT0FCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_WDT0FCLKSEL_SEL_SHIFT)) & CLKCTL0_WDT0FCLKSEL_SEL_MASK)
/*! @} */

/*! @name A32KHZWAKECLKSEL - 32 KHz Wake Clock Source Select */
/*! @{ */
#define CLKCTL0_A32KHZWAKECLKSEL_SEL_MASK        (0x7U)
#define CLKCTL0_A32KHZWAKECLKSEL_SEL_SHIFT       (0U)
/*! SEL - Select Clock Source
 *  0b000..32 KHz
 *  0b001..Low Power Oscillator Clock (LPOSC); divided by 32 by default
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_A32KHZWAKECLKSEL_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKSEL_SEL_SHIFT)) & CLKCTL0_A32KHZWAKECLKSEL_SEL_MASK)
/*! @} */

/*! @name A32KHZWAKECLKDIV - 32 KHz Wake Clock Divider */
/*! @{ */
#define CLKCTL0_A32KHZWAKECLKDIV_DIV_MASK        (0xFFU)
#define CLKCTL0_A32KHZWAKECLKDIV_DIV_SHIFT       (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_A32KHZWAKECLKDIV_DIV(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_DIV_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_DIV_MASK)
#define CLKCTL0_A32KHZWAKECLKDIV_RESET_MASK      (0x20000000U)
#define CLKCTL0_A32KHZWAKECLKDIV_RESET_SHIFT     (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_A32KHZWAKECLKDIV_RESET(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_RESET_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_RESET_MASK)
#define CLKCTL0_A32KHZWAKECLKDIV_HALT_MASK       (0x40000000U)
#define CLKCTL0_A32KHZWAKECLKDIV_HALT_SHIFT      (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_A32KHZWAKECLKDIV_HALT(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_HALT_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_HALT_MASK)
#define CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_MASK    (0x80000000U)
#define CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_SHIFT   (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_A32KHZWAKECLKDIV_REQFLAG(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_SHIFT)) & CLKCTL0_A32KHZWAKECLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name SYSTICKFCLKSEL - SYSTICK Functional Clock Select */
/*! @{ */
#define CLKCTL0_SYSTICKFCLKSEL_SEL_MASK          (0x7U)
#define CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT         (0U)
/*! SEL - Select Clock Source
 *  0b000..Systick Divider Output Clock
 *  0b001..Low Power Oscillator Clock (LPOSC)
 *  0b010..32 KHz RTC Clock
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_SYSTICKFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKSEL_SEL_SHIFT)) & CLKCTL0_SYSTICKFCLKSEL_SEL_MASK)
/*! @} */

/*! @name SYSTICKFCLKDIV - SYSTICK Functional Clock Divider */
/*! @{ */
#define CLKCTL0_SYSTICKFCLKDIV_DIV_MASK          (0xFFU)
#define CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT         (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_SYSTICKFCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_DIV_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK)
#define CLKCTL0_SYSTICKFCLKDIV_RESET_MASK        (0x20000000U)
#define CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT       (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_SYSTICKFCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_RESET_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_RESET_MASK)
#define CLKCTL0_SYSTICKFCLKDIV_HALT_MASK         (0x40000000U)
#define CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT        (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_SYSTICKFCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_HALT_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_HALT_MASK)
#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK      (0x80000000U)
#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT     (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_SYSTICKFCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL0_SYSTICKFCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_SYSTICKFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DPHYCLKSEL - MIPI-DSI PHY Clock Select */
/*! @{ */
#define CLKCTL0_DPHYCLKSEL_SEL_MASK              (0x7U)
#define CLKCTL0_DPHYCLKSEL_SEL_SHIFT             (0U)
/*! SEL - Select Clock Source
 *  0b000..FRO Clock (Div1 192 MHz)
 *  0b001..SYSPLL0 MAIN_CLK (PFD0 Output)
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..SYSPLL0 AUX1_PLL_Clock
 *  0b100..MIPI PHY Test Clock (from LVDS pads)
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_DPHYCLKSEL_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKSEL_SEL_SHIFT)) & CLKCTL0_DPHYCLKSEL_SEL_MASK)
/*! @} */

/*! @name DPHYCLKDIV - MIPI-DSI PHY Clock Divider */
/*! @{ */
#define CLKCTL0_DPHYCLKDIV_DIV_MASK              (0xFFU)
#define CLKCTL0_DPHYCLKDIV_DIV_SHIFT             (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_DPHYCLKDIV_DIV(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_DIV_SHIFT)) & CLKCTL0_DPHYCLKDIV_DIV_MASK)
#define CLKCTL0_DPHYCLKDIV_RESET_MASK            (0x20000000U)
#define CLKCTL0_DPHYCLKDIV_RESET_SHIFT           (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_DPHYCLKDIV_RESET(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_RESET_SHIFT)) & CLKCTL0_DPHYCLKDIV_RESET_MASK)
#define CLKCTL0_DPHYCLKDIV_HALT_MASK             (0x40000000U)
#define CLKCTL0_DPHYCLKDIV_HALT_SHIFT            (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_DPHYCLKDIV_HALT(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_HALT_SHIFT)) & CLKCTL0_DPHYCLKDIV_HALT_MASK)
#define CLKCTL0_DPHYCLKDIV_REQFLAG_MASK          (0x80000000U)
#define CLKCTL0_DPHYCLKDIV_REQFLAG_SHIFT         (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_DPHYCLKDIV_REQFLAG(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DPHYCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DPHYESCCLKSEL - MIPI-DSI DPHY Escape Mode Clock Select */
/*! @{ */
#define CLKCTL0_DPHYESCCLKSEL_SEL_MASK           (0x7U)
#define CLKCTL0_DPHYESCCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Select Clock Source
 *  0b000..FRO Clock (Div1 or 192 MHz)
 *  0b001..FRO Clock (Div16 or 12 MHz)
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_DPHYESCCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCCLKSEL_SEL_SHIFT)) & CLKCTL0_DPHYESCCLKSEL_SEL_MASK)
/*! @} */

/*! @name DPHYESCRXCLKDIV - MIPI-DSI DPHY Escape Mode Receive Clock Divider */
/*! @{ */
#define CLKCTL0_DPHYESCRXCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL0_DPHYESCRXCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_DPHYESCRXCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_DIV_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_DIV_MASK)
#define CLKCTL0_DPHYESCRXCLKDIV_RESET_MASK       (0x20000000U)
#define CLKCTL0_DPHYESCRXCLKDIV_RESET_SHIFT      (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_DPHYESCRXCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_RESET_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_RESET_MASK)
#define CLKCTL0_DPHYESCRXCLKDIV_HALT_MASK        (0x40000000U)
#define CLKCTL0_DPHYESCRXCLKDIV_HALT_SHIFT       (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_DPHYESCRXCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_HALT_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_HALT_MASK)
#define CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_DPHYESCRXCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DPHYESCRXCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DPHYESCTXCLKDIV - MIPI-DSI DPHY Escape Mode Tramsmit Clock Divider */
/*! @{ */
#define CLKCTL0_DPHYESCTXCLKDIV_DIV_MASK         (0xFFU)
#define CLKCTL0_DPHYESCTXCLKDIV_DIV_SHIFT        (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_DPHYESCTXCLKDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_DIV_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_DIV_MASK)
#define CLKCTL0_DPHYESCTXCLKDIV_RESET_MASK       (0x20000000U)
#define CLKCTL0_DPHYESCTXCLKDIV_RESET_SHIFT      (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_DPHYESCTXCLKDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_RESET_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_RESET_MASK)
#define CLKCTL0_DPHYESCTXCLKDIV_HALT_MASK        (0x40000000U)
#define CLKCTL0_DPHYESCTXCLKDIV_HALT_SHIFT       (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_DPHYESCTXCLKDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_HALT_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_HALT_MASK)
#define CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_DPHYESCTXCLKDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DPHYESCTXCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name GPUCLKSEL - GPU Clock Select */
/*! @{ */
#define CLKCTL0_GPUCLKSEL_SEL_MASK               (0x7U)
#define CLKCTL0_GPUCLKSEL_SEL_SHIFT              (0U)
/*! SEL - Select Clock Source
 *  0b000..Main Clock
 *  0b001..FRO Clock (Div1 or 192 MHz)
 *  0b010..SYSPLL0 MAIN_CLK (PFD0 Output)
 *  0b011..SYSPLL0 AUX0_PLL_Clock
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_GPUCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKSEL_SEL_SHIFT)) & CLKCTL0_GPUCLKSEL_SEL_MASK)
/*! @} */

/*! @name GPUCLKDIV - GPU Clock Divider */
/*! @{ */
#define CLKCTL0_GPUCLKDIV_DIV_MASK               (0xFFU)
#define CLKCTL0_GPUCLKDIV_DIV_SHIFT              (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_GPUCLKDIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_DIV_SHIFT)) & CLKCTL0_GPUCLKDIV_DIV_MASK)
#define CLKCTL0_GPUCLKDIV_RESET_MASK             (0x20000000U)
#define CLKCTL0_GPUCLKDIV_RESET_SHIFT            (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_GPUCLKDIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_RESET_SHIFT)) & CLKCTL0_GPUCLKDIV_RESET_MASK)
#define CLKCTL0_GPUCLKDIV_HALT_MASK              (0x40000000U)
#define CLKCTL0_GPUCLKDIV_HALT_SHIFT             (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_GPUCLKDIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_HALT_SHIFT)) & CLKCTL0_GPUCLKDIV_HALT_MASK)
#define CLKCTL0_GPUCLKDIV_REQFLAG_MASK           (0x80000000U)
#define CLKCTL0_GPUCLKDIV_REQFLAG_SHIFT          (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_GPUCLKDIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_GPUCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_GPUCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DCPIXELCLKSEL - LCDIF Pixel Clock Select */
/*! @{ */
#define CLKCTL0_DCPIXELCLKSEL_SEL_MASK           (0x7U)
#define CLKCTL0_DCPIXELCLKSEL_SEL_SHIFT          (0U)
/*! SEL - Select Clock Source
 *  0b000..MIPI-DSI PHY Clock
 *  0b001..Main Clock
 *  0b010..FRO Clock (Div1 or 192 MHz)
 *  0b011..SYSPLL0 MAIN_CLK (PFD0 Output)
 *  0b100..SYSPLL0 AUX0_PLL_Clock
 *  0b101..SYSPLL0 AUX1_PLL_Clock
 *  0b110..Reserved
 *  0b111..None; this may be selected to reduce power when no output is needed.
 */
#define CLKCTL0_DCPIXELCLKSEL_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKSEL_SEL_SHIFT)) & CLKCTL0_DCPIXELCLKSEL_SEL_MASK)
/*! @} */

/*! @name DCPIXELCLKDIV - LCDIF Pixel Clock Divider */
/*! @{ */
#define CLKCTL0_DCPIXELCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL0_DCPIXELCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock Divider Value Selection
 */
#define CLKCTL0_DCPIXELCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_DIV_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_DIV_MASK)
#define CLKCTL0_DCPIXELCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL0_DCPIXELCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL0_DCPIXELCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_RESET_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_RESET_MASK)
#define CLKCTL0_DCPIXELCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL0_DCPIXELCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL0_DCPIXELCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_HALT_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_HALT_MASK)
#define CLKCTL0_DCPIXELCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL0_DCPIXELCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Divider status flag
 *  0b0..The change to the divider value has finished
 *  0b1..A change is being made to the divider value
 */
#define CLKCTL0_DCPIXELCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL0_DCPIXELCLKDIV_REQFLAG_SHIFT)) & CLKCTL0_DCPIXELCLKDIV_REQFLAG_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CLKCTL0_Register_Masks */


/* CLKCTL0 - Peripheral instance base addresses */
/** Peripheral CLKCTL0 base address */
#define CLKCTL0_BASE                             (0x40001000u)
/** Peripheral CLKCTL0 base pointer */
#define CLKCTL0                                  ((CLKCTL0_Type *)CLKCTL0_BASE)
/** Array initializer of CLKCTL0 peripheral base addresses */
#define CLKCTL0_BASE_ADDRS                       { CLKCTL0_BASE }
/** Array initializer of CLKCTL0 peripheral base pointers */
#define CLKCTL0_BASE_PTRS                        { CLKCTL0 }

/*!
 * @}
 */ /* end of group CLKCTL0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CLKCTL1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL1_Peripheral_Access_Layer CLKCTL1 Peripheral Access Layer
 * @{
 */

/** CLKCTL1 - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[16];
  __IO uint32_t PSCCTL0;                           /**< Clock Control 0, offset: 0x10 */
  __IO uint32_t PSCCTL1;                           /**< Clock Control 1, offset: 0x14 */
  __IO uint32_t PSCCTL2;                           /**< Clock Control 2, offset: 0x18 */
       uint8_t RESERVED_1[36];
  __IO uint32_t PSCCTL0_SET;                       /**< Clock Set 0, offset: 0x40 */
  __IO uint32_t PSCCTL1_SET;                       /**< Clock Set 1, offset: 0x44 */
  __IO uint32_t PSCCTL2_SET;                       /**< Clock Set 2, offset: 0x48 */
       uint8_t RESERVED_2[36];
  __IO uint32_t PSCCTL0_CLR;                       /**< Clock Clear 0, offset: 0x70 */
  __IO uint32_t PSCCTL1_CLR;                       /**< Clock Clear 1, offset: 0x74 */
  __IO uint32_t PSCCTL2_CLR;                       /**< Clock Clear 2, offset: 0x78 */
       uint8_t RESERVED_3[388];
  __IO uint32_t AUDIOPLL0CLKSEL;                   /**< Audio PLL0 Clock Select, offset: 0x200 */
  __IO uint32_t AUDIOPLL0CTL0;                     /**< Audio PLL0 Control 0, offset: 0x204 */
       uint8_t RESERVED_4[4];
  __IO uint32_t AUDIOPLL0LOCKTIMEDIV2;             /**< Audio PLL0 Lock Time Divide-by-2, offset: 0x20C */
  __IO uint32_t AUDIOPLL0NUM;                      /**< Audio PLL0 Numerator, offset: 0x210 */
  __IO uint32_t AUDIOPLL0DENOM;                    /**< Audio PLL0 Denominator, offset: 0x214 */
  __IO uint32_t AUDIOPLL0PFD;                      /**< Audio PLL0 PFD, offset: 0x218 */
       uint8_t RESERVED_5[36];
  __IO uint32_t AUDIOPLLCLKDIV;                    /**< Audio PLL Clock Divider, offset: 0x240 */
       uint8_t RESERVED_6[444];
  __IO uint32_t DSPCPUCLKDIV;                      /**< DSP CPU Clock Divider, offset: 0x400 */
       uint8_t RESERVED_7[44];
  __IO uint32_t DSPCPUCLKSELA;                     /**< DSP CPU Clock Select A, offset: 0x430 */
  __IO uint32_t DSPCPUCLKSELB;                     /**< DSP CPU Clock Select B, offset: 0x434 */
       uint8_t RESERVED_8[72];
  __IO uint32_t OSEVENTTFCLKSEL;                   /**< OS Event Timer Functional Clock Select, offset: 0x480 */
       uint8_t RESERVED_9[124];
  struct {                                         /* offset: 0x500, array step: 0x20 */
    __IO uint32_t FRGCLKSEL;                         /**< Fractional Rate Generator 0 Clock Select..Fractional Rate Generator 16 Clock Select, array offset: 0x500, array step: 0x20 */
    __IO uint32_t FRGCTL;                            /**< Fractional Rate Generator 0 Control..Fractional Rate Generator 16 Control, array offset: 0x504, array step: 0x20 */
    __IO uint32_t FCFCLKSEL;                         /**< Flexcomm0 Clock Select..Flexcomm16 Clock Select, array offset: 0x508, array step: 0x20 */
         uint8_t RESERVED_0[20];
  } FLEXCOMM[17];
  __IO uint32_t FRG17CLKSEL;                       /**< Fractional Rate Generator 17 Clock Select, offset: 0x720 */
  __IO uint32_t FRG17CTL;                          /**< Fractional Rate Generator 17 Control, offset: 0x724 */
  __IO uint32_t FLEXIOCLKSEL;                      /**< FlexIO Clock Select, offset: 0x728 */
       uint8_t RESERVED_10[20];
  __IO uint32_t FLEXIOCLKDIV;                      /**< FlexIO Clock Divider, offset: 0x740 */
       uint8_t RESERVED_11[28];
  __IO uint32_t FRGPLLCLKDIV;                      /**< Fractional Rate Generator PLL Clock Divider, offset: 0x760 */
       uint8_t RESERVED_12[28];
  __IO uint32_t DMIC0FCLKSEL;                      /**< DMIC0 Functional Clock Select, offset: 0x780 */
  __IO uint32_t DMIC0FCLKDIV;                      /**< DMIC0 Functional Clock Divider, offset: 0x784 */
       uint8_t RESERVED_13[24];
  __IO uint32_t CT32BITFCLKSEL[5];                 /**< CT32BIT 0 Functional Clock Select..CT32BIT 4 Functional Clock Select, array offset: 0x7A0, array step: 0x4 */
       uint8_t RESERVED_14[12];
  __IO uint32_t AUDIOMCLKSEL;                      /**< Audio MCLK Clock Select, offset: 0x7C0 */
  __IO uint32_t AUDIOMCLKDIV;                      /**< Audio MCLK Clock Divider, offset: 0x7C4 */
       uint8_t RESERVED_15[24];
  __IO uint32_t CLKOUTSEL0;                        /**< CLKOUT Clock Select 0, offset: 0x7E0 */
  __IO uint32_t CLKOUTSEL1;                        /**< CLKOUT Clock Select 1, offset: 0x7E4 */
  __IO uint32_t CLKOUTFCLKDIV;                     /**< CLKOUT Functional Clock Divider, offset: 0x7E8 */
       uint8_t RESERVED_16[20];
  __IO uint32_t I3C01FCLKSEL;                      /**< I3C0, I3C1 Functional Clock Select, offset: 0x800 */
  __IO uint32_t I3C01FCLKSTCSEL;                   /**< I3C0, I3C1 Functional Slow Time Control Clock Select, offset: 0x804 */
  __IO uint32_t I3C01FCLKSTCDIV;                   /**< I3C0, I3C1 Functional Slow Time Control Clock Divider, offset: 0x808 */
  __IO uint32_t I3C01FCLKSDIV;                     /**< I3C0, I3C1 Functional Slow Clock Divider, offset: 0x80C */
  __IO uint32_t I3C01FCLKDIV;                      /**< I3C0, I3C1 Functional Clock Divider, offset: 0x810 */
  __IO uint32_t I3C01FCLKSTSTCLKSEL;               /**< I3C01 Functional Clock Select, offset: 0x814 */
       uint8_t RESERVED_17[8];
  __IO uint32_t WDT1FCLKSEL;                       /**< Watchdog Timer 1 Functional Clock Select, offset: 0x820 */
       uint8_t RESERVED_18[12];
  __IO uint32_t ACMP0FCLKSEL;                      /**< Analog Comparator 0 Clock Select, offset: 0x830 */
  __IO uint32_t ACMP0FCLKDIV;                      /**< Analog comparator 0 FCLK divider, offset: 0x834 */
} CLKCTL1_Type;

/* ----------------------------------------------------------------------------
   -- CLKCTL1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CLKCTL1_Register_Masks CLKCTL1 Register Masks
 * @{
 */

/*! @name PSCCTL0 - Clock Control 0 */
/*! @{ */
#define CLKCTL1_PSCCTL0_FC0_CLK_MASK             (0x100U)
#define CLKCTL1_PSCCTL0_FC0_CLK_SHIFT            (8U)
/*! FC0_CLK - Flexcomm Interface 0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC0_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC0_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC0_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC1_CLK_MASK             (0x200U)
#define CLKCTL1_PSCCTL0_FC1_CLK_SHIFT            (9U)
/*! FC1_CLK - Flexcomm Interface 1 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC1_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC2_CLK_MASK             (0x400U)
#define CLKCTL1_PSCCTL0_FC2_CLK_SHIFT            (10U)
/*! FC2_CLK - Flexcomm Interface 2 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC2_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC2_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC2_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC3_CLK_MASK             (0x800U)
#define CLKCTL1_PSCCTL0_FC3_CLK_SHIFT            (11U)
/*! FC3_CLK - Flexcomm Interface 3 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC3_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC3_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC3_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC4_CLK_MASK             (0x1000U)
#define CLKCTL1_PSCCTL0_FC4_CLK_SHIFT            (12U)
/*! FC4_CLK - Flexcomm Interface 4 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC4_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC4_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC4_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC5_CLK_MASK             (0x2000U)
#define CLKCTL1_PSCCTL0_FC5_CLK_SHIFT            (13U)
/*! FC5_CLK - Flexcomm Interface 5 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC5_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC5_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC5_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC6_CLK_MASK             (0x4000U)
#define CLKCTL1_PSCCTL0_FC6_CLK_SHIFT            (14U)
/*! FC6_CLK - Flexcomm Interface 6 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC6_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC6_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC6_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC7_CLK_MASK             (0x8000U)
#define CLKCTL1_PSCCTL0_FC7_CLK_SHIFT            (15U)
/*! FC7_CLK - Flexcomm Interface 7 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC7_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC7_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC7_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC8_CLK_MASK             (0x10000U)
#define CLKCTL1_PSCCTL0_FC8_CLK_SHIFT            (16U)
/*! FC8_CLK - Flexcomm Interface 8 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC8_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC8_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC8_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC9_CLK_MASK             (0x20000U)
#define CLKCTL1_PSCCTL0_FC9_CLK_SHIFT            (17U)
/*! FC9_CLK - Flexcomm Interface 9 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC9_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC9_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC9_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC10_CLK_MASK            (0x40000U)
#define CLKCTL1_PSCCTL0_FC10_CLK_SHIFT           (18U)
/*! FC10_CLK - Flexcomm Interface 10 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC10_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC10_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC10_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC11_CLK_MASK            (0x80000U)
#define CLKCTL1_PSCCTL0_FC11_CLK_SHIFT           (19U)
/*! FC11_CLK - Flexcomm Interface 11 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC11_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC11_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC11_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC12_CLK_MASK            (0x100000U)
#define CLKCTL1_PSCCTL0_FC12_CLK_SHIFT           (20U)
/*! FC12_CLK - Flexcomm Interface 12 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC12_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC12_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC12_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC13_CLK_MASK            (0x200000U)
#define CLKCTL1_PSCCTL0_FC13_CLK_SHIFT           (21U)
/*! FC13_CLK - Flexcomm Interface 13 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC13_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC13_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC13_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC14_SPI_CLK_MASK        (0x400000U)
#define CLKCTL1_PSCCTL0_FC14_SPI_CLK_SHIFT       (22U)
/*! FC14_SPI_CLK - Flexcomm Interface 14 SPI clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC14_SPI_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC14_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC14_SPI_CLK_MASK)
#define CLKCTL1_PSCCTL0_FC15_I2C_CLK_MASK        (0x800000U)
#define CLKCTL1_PSCCTL0_FC15_I2C_CLK_SHIFT       (23U)
/*! FC15_I2C_CLK - Flexcomm Interface 15 I2C clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC15_I2C_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC15_I2C_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC15_I2C_CLK_MASK)
#define CLKCTL1_PSCCTL0_DMIC0_MASK               (0x1000000U)
#define CLKCTL1_PSCCTL0_DMIC0_SHIFT              (24U)
/*! DMIC0 - DMIC0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_DMIC0(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_DMIC0_MASK)
#define CLKCTL1_PSCCTL0_FC16_SPI_CLK_MASK        (0x2000000U)
#define CLKCTL1_PSCCTL0_FC16_SPI_CLK_SHIFT       (25U)
/*! FC16_SPI_CLK - Flexcomm Interface 16 SPI clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FC16_SPI_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC16_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC16_SPI_CLK_MASK)
#define CLKCTL1_PSCCTL0_OSEVENT_TIMER_MASK       (0x8000000U)
#define CLKCTL1_PSCCTL0_OSEVENT_TIMER_SHIFT      (27U)
/*! OSEVENT_TIMER - OS event timer bus clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_OSEVENT_TIMER(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_OSEVENT_TIMER_SHIFT)) & CLKCTL1_PSCCTL0_OSEVENT_TIMER_MASK)
#define CLKCTL1_PSCCTL0_FlexIO_MASK              (0x20000000U)
#define CLKCTL1_PSCCTL0_FlexIO_SHIFT             (29U)
/*! FlexIO - FlexIO clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL0_FlexIO(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FlexIO_SHIFT)) & CLKCTL1_PSCCTL0_FlexIO_MASK)
/*! @} */

/*! @name PSCCTL1 - Clock Control 1 */
/*! @{ */
#define CLKCTL1_PSCCTL1_HSGPIO0_CLK_MASK         (0x1U)
#define CLKCTL1_PSCCTL1_HSGPIO0_CLK_SHIFT        (0U)
/*! HSGPIO0_CLK - Non-secure GPIO0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO0_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO0_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO1_CLK_MASK         (0x2U)
#define CLKCTL1_PSCCTL1_HSGPIO1_CLK_SHIFT        (1U)
/*! HSGPIO1_CLK - Non-secure GPIO1 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO1_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO1_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO2_CLK_MASK         (0x4U)
#define CLKCTL1_PSCCTL1_HSGPIO2_CLK_SHIFT        (2U)
/*! HSGPIO2_CLK - Non-secure GPIO2 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO2_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO2_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO2_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO3_CLK_MASK         (0x8U)
#define CLKCTL1_PSCCTL1_HSGPIO3_CLK_SHIFT        (3U)
/*! HSGPIO3_CLK - Non-secure GPIO3 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO3_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO3_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO3_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO4_CLK_MASK         (0x10U)
#define CLKCTL1_PSCCTL1_HSGPIO4_CLK_SHIFT        (4U)
/*! HSGPIO4_CLK - Non-secure GPIO4 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO4_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO4_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO4_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO5_CLK_MASK         (0x20U)
#define CLKCTL1_PSCCTL1_HSGPIO5_CLK_SHIFT        (5U)
/*! HSGPIO5_CLK - Non-secure GPIO5 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO5_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO5_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO5_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO6_CLK_MASK         (0x40U)
#define CLKCTL1_PSCCTL1_HSGPIO6_CLK_SHIFT        (6U)
/*! HSGPIO6_CLK - Non-secure GPIO6 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO6_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO6_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO6_CLK_MASK)
#define CLKCTL1_PSCCTL1_HSGPIO7_CLK_MASK         (0x80U)
#define CLKCTL1_PSCCTL1_HSGPIO7_CLK_SHIFT        (7U)
/*! HSGPIO7_CLK - Non-secure GPIO7 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_HSGPIO7_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_HSGPIO7_CLK_SHIFT)) & CLKCTL1_PSCCTL1_HSGPIO7_CLK_MASK)
#define CLKCTL1_PSCCTL1_CRC_CLK_MASK             (0x10000U)
#define CLKCTL1_PSCCTL1_CRC_CLK_SHIFT            (16U)
/*! CRC_CLK - CRC clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_CRC_CLK(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CRC_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CRC_CLK_MASK)
#define CLKCTL1_PSCCTL1_DMAC0_CLK_MASK           (0x800000U)
#define CLKCTL1_PSCCTL1_DMAC0_CLK_SHIFT          (23U)
/*! DMAC0_CLK - DMAC0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_DMAC0_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_DMAC0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_DMAC0_CLK_MASK)
#define CLKCTL1_PSCCTL1_DMAC1_CLK_MASK           (0x1000000U)
#define CLKCTL1_PSCCTL1_DMAC1_CLK_SHIFT          (24U)
/*! DMAC1_CLK - DMAC1 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_DMAC1_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_DMAC1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_DMAC1_CLK_MASK)
#define CLKCTL1_PSCCTL1_MU_CLK_MASK              (0x10000000U)
#define CLKCTL1_PSCCTL1_MU_CLK_SHIFT             (28U)
/*! MU_CLK - Messaging Unit clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_MU_CLK(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_MU_CLK_SHIFT)) & CLKCTL1_PSCCTL1_MU_CLK_MASK)
#define CLKCTL1_PSCCTL1_SEMA_CLK_MASK            (0x20000000U)
#define CLKCTL1_PSCCTL1_SEMA_CLK_SHIFT           (29U)
/*! SEMA_CLK - Semaphore clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_SEMA_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SEMA_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SEMA_CLK_MASK)
#define CLKCTL1_PSCCTL1_FREQME_CLK_MASK          (0x80000000U)
#define CLKCTL1_PSCCTL1_FREQME_CLK_SHIFT         (31U)
/*! FREQME_CLK - Frequency Measurement clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL1_FREQME_CLK(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_FREQME_CLK_SHIFT)) & CLKCTL1_PSCCTL1_FREQME_CLK_MASK)
/*! @} */

/*! @name PSCCTL2 - Clock Control 2 */
/*! @{ */
#define CLKCTL1_PSCCTL2_CT32BIT0_CLK_MASK        (0x1U)
#define CLKCTL1_PSCCTL2_CT32BIT0_CLK_SHIFT       (0U)
/*! CT32BIT0_CLK - CT32BIT 0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CT32BIT0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT0_CLK_MASK)
#define CLKCTL1_PSCCTL2_CT32BIT1_CLK_MASK        (0x2U)
#define CLKCTL1_PSCCTL2_CT32BIT1_CLK_SHIFT       (1U)
/*! CT32BIT1_CLK - CT32BIT 1 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CT32BIT1_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT1_CLK_MASK)
#define CLKCTL1_PSCCTL2_CT32BIT2_CLK_MASK        (0x4U)
#define CLKCTL1_PSCCTL2_CT32BIT2_CLK_SHIFT       (2U)
/*! CT32BIT2_CLK - CT32BIT 2 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CT32BIT2_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT2_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT2_CLK_MASK)
#define CLKCTL1_PSCCTL2_CT32BIT3_CLK_MASK        (0x8U)
#define CLKCTL1_PSCCTL2_CT32BIT3_CLK_SHIFT       (3U)
/*! CT32BIT3_CLK - CT32BIT 3 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CT32BIT3_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT3_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT3_CLK_MASK)
#define CLKCTL1_PSCCTL2_CT32BIT4_CLK_MASK        (0x10U)
#define CLKCTL1_PSCCTL2_CT32BIT4_CLK_SHIFT       (4U)
/*! CT32BIT4_CLK - CT32BIT 4 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CT32BIT4_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CT32BIT4_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CT32BIT4_CLK_MASK)
#define CLKCTL1_PSCCTL2_RTCLITE_CLK_MASK         (0x80U)
#define CLKCTL1_PSCCTL2_RTCLITE_CLK_SHIFT        (7U)
/*! RTCLITE_CLK - RTC clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_RTCLITE_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_RTCLITE_CLK_SHIFT)) & CLKCTL1_PSCCTL2_RTCLITE_CLK_MASK)
#define CLKCTL1_PSCCTL2_MRT0_CLK_MASK            (0x100U)
#define CLKCTL1_PSCCTL2_MRT0_CLK_SHIFT           (8U)
/*! MRT0_CLK - Multi-Rate Timer 0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_MRT0_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_MRT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_MRT0_CLK_MASK)
#define CLKCTL1_PSCCTL2_WWDT1_CLK_MASK           (0x400U)
#define CLKCTL1_PSCCTL2_WWDT1_CLK_SHIFT          (10U)
/*! WWDT1_CLK - Watchdog Timer 1 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_WWDT1_CLK(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_WWDT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_WWDT1_CLK_MASK)
#define CLKCTL1_PSCCTL2_I3C0_CLK_MASK            (0x10000U)
#define CLKCTL1_PSCCTL2_I3C0_CLK_SHIFT           (16U)
/*! I3C0_CLK - I3C0 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_I3C0_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_I3C0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_I3C0_CLK_MASK)
#define CLKCTL1_PSCCTL2_I3C1_CLK_MASK            (0x20000U)
#define CLKCTL1_PSCCTL2_I3C1_CLK_SHIFT           (17U)
/*! I3C1_CLK - I3C1 clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_I3C1_CLK(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_I3C1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_I3C1_CLK_MASK)
#define CLKCTL1_PSCCTL2_GPIOINTCTL_MASK          (0x40000000U)
#define CLKCTL1_PSCCTL2_GPIOINTCTL_SHIFT         (30U)
/*! GPIOINTCTL - PINT clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_GPIOINTCTL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_GPIOINTCTL_SHIFT)) & CLKCTL1_PSCCTL2_GPIOINTCTL_MASK)
#define CLKCTL1_PSCCTL2_PIMCTL_MASK              (0x80000000U)
#define CLKCTL1_PSCCTL2_PIMCTL_SHIFT             (31U)
/*! PIMCTL - INPUTMUX clock control
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_PIMCTL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_PIMCTL_SHIFT)) & CLKCTL1_PSCCTL2_PIMCTL_MASK)
/*! @} */

/*! @name PSCCTL0_SET - Clock Set 0 */
/*! @{ */
#define CLKCTL1_PSCCTL0_SET_FC0_CLK_MASK         (0x100U)
#define CLKCTL1_PSCCTL0_SET_FC0_CLK_SHIFT        (8U)
/*! FC0_CLK - Flexcomm Interface 0 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC0_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC0_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC0_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC1_CLK_MASK         (0x200U)
#define CLKCTL1_PSCCTL0_SET_FC1_CLK_SHIFT        (9U)
/*! FC1_CLK - Flexcomm Interface 1 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC1_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC1_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC2_CLK_MASK         (0x400U)
#define CLKCTL1_PSCCTL0_SET_FC2_CLK_SHIFT        (10U)
/*! FC2_CLK - Flexcomm Interface 2 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC2_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC2_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC2_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC3_CLK_MASK         (0x800U)
#define CLKCTL1_PSCCTL0_SET_FC3_CLK_SHIFT        (11U)
/*! FC3_CLK - Flexcomm Interface 3 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC3_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC3_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC3_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC4_CLK_MASK         (0x1000U)
#define CLKCTL1_PSCCTL0_SET_FC4_CLK_SHIFT        (12U)
/*! FC4_CLK - Flexcomm Interface 4 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC4_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC4_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC4_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC5_CLK_MASK         (0x2000U)
#define CLKCTL1_PSCCTL0_SET_FC5_CLK_SHIFT        (13U)
/*! FC5_CLK - Flexcomm Interface 5 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC5_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC5_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC5_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC6_CLK_MASK         (0x4000U)
#define CLKCTL1_PSCCTL0_SET_FC6_CLK_SHIFT        (14U)
/*! FC6_CLK - Flexcomm Interface 6 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC6_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC6_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC6_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC7_CLK_MASK         (0x8000U)
#define CLKCTL1_PSCCTL0_SET_FC7_CLK_SHIFT        (15U)
/*! FC7_CLK - Flexcomm Interface 7 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC7_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC7_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC7_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC8_CLK_MASK         (0x10000U)
#define CLKCTL1_PSCCTL0_SET_FC8_CLK_SHIFT        (16U)
/*! FC8_CLK - Flexcomm Interface 8 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC8_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC8_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC8_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC9_CLK_MASK         (0x20000U)
#define CLKCTL1_PSCCTL0_SET_FC9_CLK_SHIFT        (17U)
/*! FC9_CLK - Flexcomm Interface 9 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC9_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC9_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC9_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC10_CLK_MASK        (0x40000U)
#define CLKCTL1_PSCCTL0_SET_FC10_CLK_SHIFT       (18U)
/*! FC10_CLK - Flexcomm Interface 10 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC10_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC10_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC10_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC11_CLK_MASK        (0x80000U)
#define CLKCTL1_PSCCTL0_SET_FC11_CLK_SHIFT       (19U)
/*! FC11_CLK - Flexcomm Interface 11 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC11_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC11_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC11_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC12_CLK_MASK        (0x100000U)
#define CLKCTL1_PSCCTL0_SET_FC12_CLK_SHIFT       (20U)
/*! FC12_CLK - Flexcomm Interface 12 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC12_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC12_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC12_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC13_CLK_MASK        (0x200000U)
#define CLKCTL1_PSCCTL0_SET_FC13_CLK_SHIFT       (21U)
/*! FC13_CLK - Flexcomm Interface 13 clock set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC13_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC13_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC13_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_MASK    (0x400000U)
#define CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_SHIFT   (22U)
/*! FC14_SPI_CLK - Flexcomm Interface 14 SPI clock control
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC14_SPI_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_MASK    (0x800000U)
#define CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_SHIFT   (23U)
/*! FC15_I2C_CLK - Flexcomm Interface 15 I2C clock control
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC15_I2C_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_DMIC0_MASK           (0x1000000U)
#define CLKCTL1_PSCCTL0_SET_DMIC0_SHIFT          (24U)
/*! DMIC0 - DMIC0 clock control
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_DMIC0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_SET_DMIC0_MASK)
#define CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_MASK    (0x2000000U)
#define CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_SHIFT   (25U)
/*! FC16_SPI_CLK - Flexcomm Interface 16 SPI clock control
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_SET_FC16_SPI_CLK_MASK)
#define CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_MASK   (0x8000000U)
#define CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_SHIFT  (27U)
/*! OSEVENT_TIMER - OS event timer bus clock control
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_SHIFT)) & CLKCTL1_PSCCTL0_SET_OSEVENT_TIMER_MASK)
#define CLKCTL1_PSCCTL0_SET_FlexIO_MASK          (0x20000000U)
#define CLKCTL1_PSCCTL0_SET_FlexIO_SHIFT         (29U)
/*! FlexIO - FlexIO clock control
 *  0b0..No effect
 *  0b1..Sets the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_SET_FlexIO(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_SET_FlexIO_SHIFT)) & CLKCTL1_PSCCTL0_SET_FlexIO_MASK)
/*! @} */

/*! @name PSCCTL1_SET - Clock Set 1 */
/*! @{ */
#define CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_MASK     (0x1U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_SHIFT    (0U)
/*! HSGPIO0_CLK - Non-secure GPIO0 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO0_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_MASK     (0x2U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_SHIFT    (1U)
/*! HSGPIO1_CLK - Non-secure GPIO1 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO1_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_MASK     (0x4U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_SHIFT    (2U)
/*! HSGPIO2_CLK - Non-secure GPIO2 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO2_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_MASK     (0x8U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_SHIFT    (3U)
/*! HSGPIO3_CLK - Non-secure GPIO3 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO3_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_MASK     (0x10U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_SHIFT    (4U)
/*! HSGPIO4_CLK - Non-secure GPIO4 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO4_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_MASK     (0x20U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_SHIFT    (5U)
/*! HSGPIO5_CLK - Non-secure GPIO5 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO5_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_MASK     (0x40U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_SHIFT    (6U)
/*! HSGPIO6_CLK - Non-secure GPIO6 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO6_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_MASK     (0x80U)
#define CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_SHIFT    (7U)
/*! HSGPIO7_CLK - Non-secure GPIO7 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_HSGPIO7_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_CRC_CLK_MASK         (0x10000U)
#define CLKCTL1_PSCCTL1_SET_CRC_CLK_SHIFT        (16U)
/*! CRC_CLK - CRC clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_CRC_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CRC_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_CRC_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_DMAC0_CLK_MASK       (0x800000U)
#define CLKCTL1_PSCCTL1_SET_DMAC0_CLK_SHIFT      (23U)
/*! DMAC0_CLK - DMAC0 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_DMAC0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_DMAC0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_DMAC0_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_DMAC1_CLK_MASK       (0x1000000U)
#define CLKCTL1_PSCCTL1_SET_DMAC1_CLK_SHIFT      (24U)
/*! DMAC1_CLK - DMAC1 clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_DMAC1_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_DMAC1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_DMAC1_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_MU_CLK_MASK          (0x10000000U)
#define CLKCTL1_PSCCTL1_SET_MU_CLK_SHIFT         (28U)
/*! MU_CLK - Messaging Unit clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_MU_CLK(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_MU_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_MU_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_SEMA_CLK_MASK        (0x20000000U)
#define CLKCTL1_PSCCTL1_SET_SEMA_CLK_SHIFT       (29U)
/*! SEMA_CLK - Semaphore clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_SEMA_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_SEMA_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_SEMA_CLK_MASK)
#define CLKCTL1_PSCCTL1_SET_FREQME_CLK_MASK      (0x80000000U)
#define CLKCTL1_PSCCTL1_SET_FREQME_CLK_SHIFT     (31U)
/*! FREQME_CLK - Frequency Measurement clock control set
 *  0b0..No effect
 *  0b1..Sets the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_SET_FREQME_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_FREQME_CLK_SHIFT)) & CLKCTL1_PSCCTL1_SET_FREQME_CLK_MASK)
/*! @} */

/*! @name PSCCTL2_SET - Clock Set 2 */
/*! @{ */
#define CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_MASK    (0x1U)
#define CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_SHIFT   (0U)
/*! CT32BIT0_CLK - CT32BIT 0 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT0_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_MASK    (0x2U)
#define CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_SHIFT   (1U)
/*! CT32BIT1_CLK - CT32BIT 1 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT1_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_MASK    (0x4U)
#define CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_SHIFT   (2U)
/*! CT32BIT2_CLK - CT32BIT 2 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT2_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_MASK    (0x8U)
#define CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_SHIFT   (3U)
/*! CT32BIT3_CLK - CT32BIT 3 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT3_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_MASK    (0x10U)
#define CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_SHIFT   (4U)
/*! CT32BIT4_CLK - CT32BIT 4 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_CT32BIT4_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_MASK     (0x80U)
#define CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_SHIFT    (7U)
/*! RTCLITE_CLK - RTC clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_RTCLITE_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_RTCLITE_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_MRT0_CLK_MASK        (0x100U)
#define CLKCTL1_PSCCTL2_SET_MRT0_CLK_SHIFT       (8U)
/*! MRT0_CLK - Multi-Rate Timer 0 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_MRT0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_MRT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_MRT0_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_WWDT1_CLK_MASK       (0x400U)
#define CLKCTL1_PSCCTL2_SET_WWDT1_CLK_SHIFT      (10U)
/*! WWDT1_CLK - Watchdog Timer 1 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_WWDT1_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_WWDT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_WWDT1_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_I3C0_CLK_MASK        (0x10000U)
#define CLKCTL1_PSCCTL2_SET_I3C0_CLK_SHIFT       (16U)
/*! I3C0_CLK - I3C0 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_I3C0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_I3C0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_I3C0_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_I3C1_CLK_MASK        (0x20000U)
#define CLKCTL1_PSCCTL2_SET_I3C1_CLK_SHIFT       (17U)
/*! I3C1_CLK - I3C1 clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_I3C1_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_I3C1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_SET_I3C1_CLK_MASK)
#define CLKCTL1_PSCCTL2_SET_GPIOINTCTL_MASK      (0x40000000U)
#define CLKCTL1_PSCCTL2_SET_GPIOINTCTL_SHIFT     (30U)
/*! GPIOINTCTL - PINT clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_GPIOINTCTL(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_GPIOINTCTL_SHIFT)) & CLKCTL1_PSCCTL2_SET_GPIOINTCTL_MASK)
#define CLKCTL1_PSCCTL2_SET_PIMCTL_MASK          (0x80000000U)
#define CLKCTL1_PSCCTL2_SET_PIMCTL_SHIFT         (31U)
/*! PIMCTL - INPUTMUX clock control set
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_SET_PIMCTL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_SET_PIMCTL_SHIFT)) & CLKCTL1_PSCCTL2_SET_PIMCTL_MASK)
/*! @} */

/*! @name PSCCTL0_CLR - Clock Clear 0 */
/*! @{ */
#define CLKCTL1_PSCCTL0_CLR_FC0_CLK_MASK         (0x100U)
#define CLKCTL1_PSCCTL0_CLR_FC0_CLK_SHIFT        (8U)
/*! FC0_CLK - Flexcomm Interface 0 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC0_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC0_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC0_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC1_CLK_MASK         (0x200U)
#define CLKCTL1_PSCCTL0_CLR_FC1_CLK_SHIFT        (9U)
/*! FC1_CLK - Flexcomm Interface 1 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC1_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC1_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC2_CLK_MASK         (0x400U)
#define CLKCTL1_PSCCTL0_CLR_FC2_CLK_SHIFT        (10U)
/*! FC2_CLK - Flexcomm Interface 2 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC2_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC2_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC2_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC3_CLK_MASK         (0x800U)
#define CLKCTL1_PSCCTL0_CLR_FC3_CLK_SHIFT        (11U)
/*! FC3_CLK - Flexcomm Interface 3 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC3_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC3_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC3_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC4_CLK_MASK         (0x1000U)
#define CLKCTL1_PSCCTL0_CLR_FC4_CLK_SHIFT        (12U)
/*! FC4_CLK - Flexcomm Interface 4 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC4_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC4_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC4_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC5_CLK_MASK         (0x2000U)
#define CLKCTL1_PSCCTL0_CLR_FC5_CLK_SHIFT        (13U)
/*! FC5_CLK - Flexcomm Interface 5 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC5_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC5_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC5_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC6_CLK_MASK         (0x4000U)
#define CLKCTL1_PSCCTL0_CLR_FC6_CLK_SHIFT        (14U)
/*! FC6_CLK - Flexcomm Interface 6 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC6_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC6_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC6_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC7_CLK_MASK         (0x8000U)
#define CLKCTL1_PSCCTL0_CLR_FC7_CLK_SHIFT        (15U)
/*! FC7_CLK - Flexcomm Interface 7 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC7_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC7_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC7_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC8_CLK_MASK         (0x10000U)
#define CLKCTL1_PSCCTL0_CLR_FC8_CLK_SHIFT        (16U)
/*! FC8_CLK - Flexcomm Interface 8 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC8_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC8_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC8_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC9_CLK_MASK         (0x20000U)
#define CLKCTL1_PSCCTL0_CLR_FC9_CLK_SHIFT        (17U)
/*! FC9_CLK - Flexcomm Interface 9 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC9_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC9_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC9_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC10_CLK_MASK        (0x40000U)
#define CLKCTL1_PSCCTL0_CLR_FC10_CLK_SHIFT       (18U)
/*! FC10_CLK - Flexcomm Interface 10 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC10_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC10_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC10_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC11_CLK_MASK        (0x80000U)
#define CLKCTL1_PSCCTL0_CLR_FC11_CLK_SHIFT       (19U)
/*! FC11_CLK - Flexcomm Interface 11 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC11_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC11_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC11_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC12_CLK_MASK        (0x100000U)
#define CLKCTL1_PSCCTL0_CLR_FC12_CLK_SHIFT       (20U)
/*! FC12_CLK - Flexcomm Interface 12 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC12_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC12_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC12_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC13_CLK_MASK        (0x200000U)
#define CLKCTL1_PSCCTL0_CLR_FC13_CLK_SHIFT       (21U)
/*! FC13_CLK - Flexcomm Interface 13 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC13_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC13_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC13_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_MASK    (0x400000U)
#define CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_SHIFT   (22U)
/*! FC14_SPI_CLK - Flexcomm Interface 14 SPI clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC14_SPI_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_MASK    (0x800000U)
#define CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_SHIFT   (23U)
/*! FC15_I2C_CLK - Flexcomm Interface 15 I2C clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC15_I2C_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_DMIC0_MASK           (0x1000000U)
#define CLKCTL1_PSCCTL0_CLR_DMIC0_SHIFT          (24U)
/*! DMIC0 - DMIC0 clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_DMIC0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_DMIC0_SHIFT)) & CLKCTL1_PSCCTL0_CLR_DMIC0_MASK)
#define CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_MASK    (0x2000000U)
#define CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_SHIFT   (25U)
/*! FC16_SPI_CLK - Flexcomm Interface 16 SPI clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FC16_SPI_CLK_MASK)
#define CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_MASK   (0x8000000U)
#define CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_SHIFT  (27U)
/*! OSEVENT_TIMER - OS event timer bus clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_SHIFT)) & CLKCTL1_PSCCTL0_CLR_OSEVENT_TIMER_MASK)
#define CLKCTL1_PSCCTL0_CLR_FlexIO_MASK          (0x20000000U)
#define CLKCTL1_PSCCTL0_CLR_FlexIO_SHIFT         (29U)
/*! FlexIO - FlexIO clock control clear
 *  0b0..No effect
 *  0b1..Clears the PSCCTL0 bit
 */
#define CLKCTL1_PSCCTL0_CLR_FlexIO(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_FlexIO_SHIFT)) & CLKCTL1_PSCCTL0_CLR_FlexIO_MASK)
/*! @} */

/*! @name PSCCTL1_CLR - Clock Clear 1 */
/*! @{ */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_MASK     (0x1U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_SHIFT    (0U)
/*! HSGPIO0_CLK - Non-secure GPIO0 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO0_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_MASK     (0x2U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_SHIFT    (1U)
/*! HSGPIO1_CLK - Non-secure GPIO1 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO1_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_MASK     (0x4U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_SHIFT    (2U)
/*! HSGPIO2_CLK - Non-secure GPIO2 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO2_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_MASK     (0x8U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_SHIFT    (3U)
/*! HSGPIO3_CLK - Non-secure GPIO3 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO3_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_MASK     (0x10U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_SHIFT    (4U)
/*! HSGPIO4_CLK - Non-secure GPIO4 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO4_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_MASK     (0x20U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_SHIFT    (5U)
/*! HSGPIO5_CLK - Non-secure GPIO5 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO5_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_MASK     (0x40U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_SHIFT    (6U)
/*! HSGPIO6_CLK - Non-secure GPIO6 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO6_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_MASK     (0x80U)
#define CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_SHIFT    (7U)
/*! HSGPIO7_CLK - Non-secure GPIO7 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_HSGPIO7_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_CRC_CLK_MASK         (0x10000U)
#define CLKCTL1_PSCCTL1_CLR_CRC_CLK_SHIFT        (16U)
/*! CRC_CLK - CRC clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_CRC_CLK(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_CRC_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_CRC_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_MASK       (0x800000U)
#define CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_SHIFT      (23U)
/*! DMAC0_CLK - DMAC0 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_DMAC0_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_DMAC0_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_MASK       (0x1000000U)
#define CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_SHIFT      (24U)
/*! DMAC1_CLK - DMAC1 clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_DMAC1_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_DMAC1_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_MU_CLK_MASK          (0x10000000U)
#define CLKCTL1_PSCCTL1_CLR_MU_CLK_SHIFT         (28U)
/*! MU_CLK - Messaging Unit clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_MU_CLK(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_MU_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_MU_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_SEMA_CLK_MASK        (0x20000000U)
#define CLKCTL1_PSCCTL1_CLR_SEMA_CLK_SHIFT       (29U)
/*! SEMA_CLK - Semaphore clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_SEMA_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_SEMA_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_SEMA_CLK_MASK)
#define CLKCTL1_PSCCTL1_CLR_FREQME_CLK_MASK      (0x80000000U)
#define CLKCTL1_PSCCTL1_CLR_FREQME_CLK_SHIFT     (31U)
/*! FREQME_CLK - Frequency Measurement clock control
 *  0b0..No effect
 *  0b1..Clears the PSCCTL1 bit
 */
#define CLKCTL1_PSCCTL1_CLR_FREQME_CLK(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_CLR_FREQME_CLK_SHIFT)) & CLKCTL1_PSCCTL1_CLR_FREQME_CLK_MASK)
/*! @} */

/*! @name PSCCTL2_CLR - Clock Clear 2 */
/*! @{ */
#define CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_MASK    (0x1U)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_SHIFT   (0U)
/*! CT32BIT0_CLK - CT32BIT 0 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT0_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_MASK    (0x2U)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_SHIFT   (1U)
/*! CT32BIT1_CLK - CT32BIT 1 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT1_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_MASK    (0x4U)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_SHIFT   (2U)
/*! CT32BIT2_CLK - CT32BIT 2 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT2_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_MASK    (0x8U)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_SHIFT   (3U)
/*! CT32BIT3_CLK - CT32BIT 3 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT3_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_MASK    (0x10U)
#define CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_SHIFT   (4U)
/*! CT32BIT4_CLK - CT32BIT 4 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_CT32BIT4_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_MASK     (0x80U)
#define CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_SHIFT    (7U)
/*! RTCLITE_CLK - RTC clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_RTCLITE_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_MRT0_CLK_MASK        (0x100U)
#define CLKCTL1_PSCCTL2_CLR_MRT0_CLK_SHIFT       (8U)
/*! MRT0_CLK - Multi-Rate Timer 0 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_MRT0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_MRT0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_MRT0_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_MASK       (0x400U)
#define CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_SHIFT      (10U)
/*! WWDT1_CLK - Watchdog Timer 1 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_WWDT1_CLK(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_WWDT1_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_I3C0_CLK_MASK        (0x10000U)
#define CLKCTL1_PSCCTL2_CLR_I3C0_CLK_SHIFT       (16U)
/*! I3C0_CLK - I3C0 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_I3C0_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_I3C0_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_I3C0_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_I3C1_CLK_MASK        (0x20000U)
#define CLKCTL1_PSCCTL2_CLR_I3C1_CLK_SHIFT       (17U)
/*! I3C1_CLK - I3C1 clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_I3C1_CLK(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_I3C1_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_I3C1_CLK_MASK)
#define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_MASK      (0x40000000U)
#define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_SHIFT     (30U)
/*! GPIOINTCTL - PINT clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_MASK)
#define CLKCTL1_PSCCTL2_CLR_PIMCTL_MASK          (0x80000000U)
#define CLKCTL1_PSCCTL2_CLR_PIMCTL_SHIFT         (31U)
/*! PIMCTL - INPUTMUX clock control clear
 *  0b0..Disable Clock
 *  0b1..Enable Clock
 */
#define CLKCTL1_PSCCTL2_CLR_PIMCTL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL2_CLR_PIMCTL_SHIFT)) & CLKCTL1_PSCCTL2_CLR_PIMCTL_MASK)
/*! @} */

/*! @name AUDIOPLL0CLKSEL - Audio PLL0 Clock Select */
/*! @{ */
#define CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK         (0x7U)
#define CLKCTL1_AUDIOPLL0CLKSEL_SEL_SHIFT        (0U)
/*! SEL - Audio PLL0 Clock Select
 *  0b000..FRO Clock (Divided-by-8 selection)
 *  0b001..OSC_CLK clock (User-Selectable)
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_AUDIOPLL0CLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CLKSEL_SEL_SHIFT)) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK)
/*! @} */

/*! @name AUDIOPLL0CTL0 - Audio PLL0 Control 0 */
/*! @{ */
#define CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK        (0x1U)
#define CLKCTL1_AUDIOPLL0CTL0_BYPASS_SHIFT       (0U)
/*! BYPASS - AUDIOPLL0 BYPASS Mode
 *  0b0..PFD outputs are PFD-programmed clocks
 *  0b1..Bypass Mode. PFD outputs are sourced directly from the reference input clock
 */
#define CLKCTL1_AUDIOPLL0CTL0_BYPASS(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_BYPASS_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK)
#define CLKCTL1_AUDIOPLL0CTL0_RESET_MASK         (0x2U)
#define CLKCTL1_AUDIOPLL0CTL0_RESET_SHIFT        (1U)
/*! RESET - AUDIOPLL0 Reset
 *  0b0..AUDIOPLL0 reset is removed
 *  0b1..AUDIOPLL0 is placed into reset
 */
#define CLKCTL1_AUDIOPLL0CTL0_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_RESET_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK)
#define CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK (0x2000U)
#define CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_SHIFT (13U)
/*! HOLDRINGOFF_ENA - Hold Ring Off Control
 *  0b0..Disable
 *  0b1..Enable
 */
#define CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK)
#define CLKCTL1_AUDIOPLL0CTL0_MULT_MASK          (0xFF0000U)
#define CLKCTL1_AUDIOPLL0CTL0_MULT_SHIFT         (16U)
/*! MULT - Multiplication Factor for F SYSPLL0_OUTPUT
 *  0b00010000..Divide by 16
 *  0b00010001..Divide by 17
 *  0b00010100..Divide by 20
 *  0b00010110..Divide by 22
 *  0b00011011..Divide by 27
 *  0b00100001..Divide by 33
 */
#define CLKCTL1_AUDIOPLL0CTL0_MULT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0CTL0_MULT_SHIFT)) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK)
/*! @} */

/*! @name AUDIOPLL0LOCKTIMEDIV2 - Audio PLL0 Lock Time Divide-by-2 */
/*! @{ */
#define CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
#define CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
/*! LOCKTIMEDIV2 - AUDIOPLL0 Lock Time Divide-by-2
 */
#define CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
/*! @} */

/*! @name AUDIOPLL0NUM - Audio PLL0 Numerator */
/*! @{ */
#define CLKCTL1_AUDIOPLL0NUM_NUM_MASK            (0x3FFFFFFFU)
#define CLKCTL1_AUDIOPLL0NUM_NUM_SHIFT           (0U)
/*! NUM - Numerator
 */
#define CLKCTL1_AUDIOPLL0NUM_NUM(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0NUM_NUM_SHIFT)) & CLKCTL1_AUDIOPLL0NUM_NUM_MASK)
/*! @} */

/*! @name AUDIOPLL0DENOM - Audio PLL0 Denominator */
/*! @{ */
#define CLKCTL1_AUDIOPLL0DENOM_DENOM_MASK        (0x3FFFFFFFU)
#define CLKCTL1_AUDIOPLL0DENOM_DENOM_SHIFT       (0U)
/*! DENOM - Denominator
 */
#define CLKCTL1_AUDIOPLL0DENOM_DENOM(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0DENOM_DENOM_SHIFT)) & CLKCTL1_AUDIOPLL0DENOM_DENOM_MASK)
/*! @} */

/*! @name AUDIOPLL0PFD - Audio PLL0 PFD */
/*! @{ */
#define CLKCTL1_AUDIOPLL0PFD_PFD0_MASK           (0x3FU)
#define CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT          (0U)
/*! PFD0 - PLL Fractional Divider 0
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD0(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK    (0x40U)
#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_SHIFT   (6U)
/*! PFD0_CLKRDY - PFD0 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK   (0x80U)
#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_SHIFT  (7U)
/*! PFD0_CLKGATE - PFD0 Clock Gate
 *  0b0..PFD0 clock is not gated
 *  0b1..PFD0 clock is gated
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD1_MASK           (0x3F00U)
#define CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT          (8U)
/*! PFD1 - PLL Fractional Divider 1
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD1(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_MASK    (0x4000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_SHIFT   (14U)
/*! PFD1_CLKRDY - PFD1 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD1_CLKRDY_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_MASK   (0x8000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_SHIFT  (15U)
/*! PFD1_CLKGATE - PFD1 Clock Gate
 *  0b0..PFD1 clock is not gated
 *  0b1..PFD1 clock is gated
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD1_CLKGATE_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD2_MASK           (0x3F0000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT          (16U)
/*! PFD2 - PLL Fractional Divider 2
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD2(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_MASK    (0x400000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_SHIFT   (22U)
/*! PFD2_CLKRDY - PFD2 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD2_CLKRDY_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_MASK   (0x800000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_SHIFT  (23U)
/*! PFD2_CLKGATE - PFD2 Clock Gate
 *  0b0..PFD2 clock is not gated
 *  0b1..PFD2 clock is gated
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD2_CLKGATE_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD3_MASK           (0x3F000000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD3_SHIFT          (24U)
/*! PFD3 - PLL Fractional Divider 3
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD3(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD3_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD3_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_MASK    (0x40000000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_SHIFT   (30U)
/*! PFD3_CLKRDY - PFD3 Clock Ready Status Flag
 *  0b0..Not ready
 *  0b1..Ready
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY(x)      (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD3_CLKRDY_MASK)
#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_MASK   (0x80000000U)
#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_SHIFT  (31U)
/*! PFD3_CLKGATE - PFD3 Clock Gate
 *  0b0..PFD3 clock is not gated
 *  0b1..PFD3 clock is gated
 */
#define CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_SHIFT)) & CLKCTL1_AUDIOPLL0PFD_PFD3_CLKGATE_MASK)
/*! @} */

/*! @name AUDIOPLLCLKDIV - Audio PLL Clock Divider */
/*! @{ */
#define CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK          (0xFFU)
#define CLKCTL1_AUDIOPLLCLKDIV_DIV_SHIFT         (0U)
/*! DIV - 32 KHz Wake Clock Divider Value
 */
#define CLKCTL1_AUDIOPLLCLKDIV_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_DIV_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK)
#define CLKCTL1_AUDIOPLLCLKDIV_RESET_MASK        (0x20000000U)
#define CLKCTL1_AUDIOPLLCLKDIV_RESET_SHIFT       (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_AUDIOPLLCLKDIV_RESET(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_RESET_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_RESET_MASK)
#define CLKCTL1_AUDIOPLLCLKDIV_HALT_MASK         (0x40000000U)
#define CLKCTL1_AUDIOPLLCLKDIV_HALT_SHIFT        (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_AUDIOPLLCLKDIV_HALT(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_HALT_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_HALT_MASK)
#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_MASK      (0x80000000U)
#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_SHIFT     (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished
 *  0b1..The Divider value has changed
 */
#define CLKCTL1_AUDIOPLLCLKDIV_REQFLAG(x)        (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_AUDIOPLLCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DSPCPUCLKDIV - DSP CPU Clock Divider */
/*! @{ */
#define CLKCTL1_DSPCPUCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_DSPCPUCLKDIV_DIV_SHIFT           (0U)
/*! DIV - DSP Clock Divider Value
 */
#define CLKCTL1_DSPCPUCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_DIV_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_DIV_MASK)
#define CLKCTL1_DSPCPUCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_DSPCPUCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_DSPCPUCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_RESET_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_RESET_MASK)
#define CLKCTL1_DSPCPUCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_DSPCPUCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_DSPCPUCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_HALT_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_HALT_MASK)
#define CLKCTL1_DSPCPUCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_DSPCPUCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_DSPCPUCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_DSPCPUCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DSPCPUCLKSELA - DSP CPU Clock Select A */
/*! @{ */
#define CLKCTL1_DSPCPUCLKSELA_SEL_MASK           (0x3U)
#define CLKCTL1_DSPCPUCLKSELA_SEL_SHIFT          (0U)
/*! SEL - DSP Main 1st Stage Control Clock Source
 *  0b00..FRO Clock
 *  0b01..OSC_CLK Clock
 *  0b10..Low Power Oscillator Clock (LPOSC)
 *  0b11..Reserved
 */
#define CLKCTL1_DSPCPUCLKSELA_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKSELA_SEL_SHIFT)) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK)
/*! @} */

/*! @name DSPCPUCLKSELB - DSP CPU Clock Select B */
/*! @{ */
#define CLKCTL1_DSPCPUCLKSELB_SEL_MASK           (0x3U)
#define CLKCTL1_DSPCPUCLKSELB_SEL_SHIFT          (0U)
/*! SEL - Main Clock Source
 *  0b00..MAINCLKSELA 1st Stage Clock
 *  0b01..Main System PLL Clock
 *  0b10..DSP System PLL Clock
 *  0b11..RTC 32 KHz Clock
 */
#define CLKCTL1_DSPCPUCLKSELB_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DSPCPUCLKSELB_SEL_SHIFT)) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK)
/*! @} */

/*! @name OSEVENTTFCLKSEL - OS Event Timer Functional Clock Select */
/*! @{ */
#define CLKCTL1_OSEVENTTFCLKSEL_SEL_MASK         (0x7U)
#define CLKCTL1_OSEVENTTFCLKSEL_SEL_SHIFT        (0U)
/*! SEL - OS Event Timer Functional Clock Source
 *  0b000..Low Power Oscillator Clock (LPOSC)
 *  0b001..RTC 32 KHz Clock
 *  0b010..HCLK Free-Running Clock (Global Time Stamping)
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_OSEVENTTFCLKSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_OSEVENTTFCLKSEL_SEL_SHIFT)) & CLKCTL1_OSEVENTTFCLKSEL_SEL_MASK)
/*! @} */

/*! @name FRGCLKSEL - Fractional Rate Generator 0 Clock Select..Fractional Rate Generator 16 Clock Select */
/*! @{ */
#define CLKCTL1_FRGCLKSEL_SEL_MASK               (0x7U)
#define CLKCTL1_FRGCLKSEL_SEL_SHIFT              (0U)
/*! SEL - Fractional Generator 16 Clock Source
 *  0b000..Main Clock
 *  0b001..FRG PLL Clock
 *  0b010..FRO Clock Divided by 4
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_FRGCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCLKSEL_SEL_SHIFT)) & CLKCTL1_FRGCLKSEL_SEL_MASK)
/*! @} */

/* The count of CLKCTL1_FRGCLKSEL */
#define CLKCTL1_FRGCLKSEL_COUNT                  (17U)

/*! @name FRGCTL - Fractional Rate Generator 0 Control..Fractional Rate Generator 16 Control */
/*! @{ */
#define CLKCTL1_FRGCTL_DIV_MASK                  (0xFFU)
#define CLKCTL1_FRGCTL_DIV_SHIFT                 (0U)
#define CLKCTL1_FRGCTL_DIV(x)                    (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCTL_DIV_SHIFT)) & CLKCTL1_FRGCTL_DIV_MASK)
#define CLKCTL1_FRGCTL_MULT_MASK                 (0xFF00U)
#define CLKCTL1_FRGCTL_MULT_SHIFT                (8U)
#define CLKCTL1_FRGCTL_MULT(x)                   (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGCTL_MULT_SHIFT)) & CLKCTL1_FRGCTL_MULT_MASK)
/*! @} */

/* The count of CLKCTL1_FRGCTL */
#define CLKCTL1_FRGCTL_COUNT                     (17U)

/*! @name FCFCLKSEL - Flexcomm0 Clock Select..Flexcomm16 Clock Select */
/*! @{ */
#define CLKCTL1_FCFCLKSEL_SEL_MASK               (0x7U)
#define CLKCTL1_FCFCLKSEL_SEL_SHIFT              (0U)
/*! SEL - Flexcomm Functional Clock Source
 *  0b000..FRO Clock Divided-by-4
 *  0b001..Audio PLL Clock
 *  0b010..Master Clock In
 *  0b011..FCn FRG Clock
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_FCFCLKSEL_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FCFCLKSEL_SEL_SHIFT)) & CLKCTL1_FCFCLKSEL_SEL_MASK)
/*! @} */

/* The count of CLKCTL1_FCFCLKSEL */
#define CLKCTL1_FCFCLKSEL_COUNT                  (17U)

/*! @name FRG17CLKSEL - Fractional Rate Generator 17 Clock Select */
/*! @{ */
#define CLKCTL1_FRG17CLKSEL_SEL_MASK             (0x7U)
#define CLKCTL1_FRG17CLKSEL_SEL_SHIFT            (0U)
/*! SEL - Fractional Generator 17 Clock Source
 *  0b000..Main Clock
 *  0b001..FRG PLL Clock
 *  0b010..FRO Clock Divided by 4
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_FRG17CLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG17CLKSEL_SEL_SHIFT)) & CLKCTL1_FRG17CLKSEL_SEL_MASK)
/*! @} */

/*! @name FRG17CTL - Fractional Rate Generator 17 Control */
/*! @{ */
#define CLKCTL1_FRG17CTL_DIV_MASK                (0xFFU)
#define CLKCTL1_FRG17CTL_DIV_SHIFT               (0U)
#define CLKCTL1_FRG17CTL_DIV(x)                  (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG17CTL_DIV_SHIFT)) & CLKCTL1_FRG17CTL_DIV_MASK)
#define CLKCTL1_FRG17CTL_MULT_MASK               (0xFF00U)
#define CLKCTL1_FRG17CTL_MULT_SHIFT              (8U)
#define CLKCTL1_FRG17CTL_MULT(x)                 (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRG17CTL_MULT_SHIFT)) & CLKCTL1_FRG17CTL_MULT_MASK)
/*! @} */

/*! @name FLEXIOCLKSEL - FlexIO Clock Select */
/*! @{ */
#define CLKCTL1_FLEXIOCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL1_FLEXIOCLKSEL_SEL_SHIFT           (0U)
/*! SEL - FlexIO Functional Clock Source
 *  0b000..FRO Clock (Divided-by-4 selection)
 *  0b001..Audio PLL Clock
 *  0b010..Master Clock In
 *  0b011..FC17 FRG Clock
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_FLEXIOCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKSEL_SEL_SHIFT)) & CLKCTL1_FLEXIOCLKSEL_SEL_MASK)
/*! @} */

/*! @name FLEXIOCLKDIV - FlexIO Clock Divider */
/*! @{ */
#define CLKCTL1_FLEXIOCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_FLEXIOCLKDIV_DIV_SHIFT           (0U)
/*! DIV - FLEXIO Clock Divider Value
 */
#define CLKCTL1_FLEXIOCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_DIV_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_DIV_MASK)
#define CLKCTL1_FLEXIOCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_FLEXIOCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_FLEXIOCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_RESET_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_RESET_MASK)
#define CLKCTL1_FLEXIOCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_FLEXIOCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_FLEXIOCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_HALT_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_HALT_MASK)
#define CLKCTL1_FLEXIOCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_FLEXIOCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed
 */
#define CLKCTL1_FLEXIOCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FLEXIOCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_FLEXIOCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name FRGPLLCLKDIV - Fractional Rate Generator PLL Clock Divider */
/*! @{ */
#define CLKCTL1_FRGPLLCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_FRGPLLCLKDIV_DIV_SHIFT           (0U)
/*! DIV - FRG PLL Clock Divider Value
 */
#define CLKCTL1_FRGPLLCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_DIV_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_DIV_MASK)
#define CLKCTL1_FRGPLLCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_FRGPLLCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_FRGPLLCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_RESET_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_RESET_MASK)
#define CLKCTL1_FRGPLLCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_FRGPLLCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_FRGPLLCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_HALT_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_HALT_MASK)
#define CLKCTL1_FRGPLLCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_FRGPLLCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_FRGPLLCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_FRGPLLCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_FRGPLLCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name DMIC0FCLKSEL - DMIC0 Functional Clock Select */
/*! @{ */
#define CLKCTL1_DMIC0FCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL1_DMIC0FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - DMIC Functional Clock Source
 *  0b000..FRO Clock (Divided-by-4 selection)
 *  0b001..Audio PLL Clock
 *  0b010..Master Clock In
 *  0b011..Low Power Oscillator Clock (LPOSC)
 *  0b100..32 KHz Wake Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_DMIC0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKSEL_SEL_SHIFT)) & CLKCTL1_DMIC0FCLKSEL_SEL_MASK)
/*! @} */

/*! @name DMIC0FCLKDIV - DMIC0 Functional Clock Divider */
/*! @{ */
#define CLKCTL1_DMIC0FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_DMIC0FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - 32 KHz Wake Clock Divider Value
 */
#define CLKCTL1_DMIC0FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_DIV_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_DIV_MASK)
#define CLKCTL1_DMIC0FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_DMIC0FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_DMIC0FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_RESET_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_RESET_MASK)
#define CLKCTL1_DMIC0FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_DMIC0FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_DMIC0FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_HALT_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_HALT_MASK)
#define CLKCTL1_DMIC0FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_DMIC0FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_DMIC0FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_DMIC0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_DMIC0FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name CT32BITFCLKSEL - CT32BIT 0 Functional Clock Select..CT32BIT 4 Functional Clock Select */
/*! @{ */
#define CLKCTL1_CT32BITFCLKSEL_SEL_MASK          (0x7U)
#define CLKCTL1_CT32BITFCLKSEL_SEL_SHIFT         (0U)
/*! SEL - CT32BIT 4 Functional Clock Source
 *  0b000..Main Clock
 *  0b001..FRO Clock
 *  0b010..Audio PLL Clock
 *  0b011..Master Clock In
 *  0b100..32 KHZ Wake Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_CT32BITFCLKSEL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CT32BITFCLKSEL_SEL_SHIFT)) & CLKCTL1_CT32BITFCLKSEL_SEL_MASK)
/*! @} */

/* The count of CLKCTL1_CT32BITFCLKSEL */
#define CLKCTL1_CT32BITFCLKSEL_COUNT             (5U)

/*! @name AUDIOMCLKSEL - Audio MCLK Clock Select */
/*! @{ */
#define CLKCTL1_AUDIOMCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL1_AUDIOMCLKSEL_SEL_SHIFT           (0U)
/*! SEL - Audio MCLK Clock Source Select
 *  0b000..FRO Clock (Divided-by-8 selection)
 *  0b001..AUDIO PLL Clock (Shared Domain)
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_AUDIOMCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKSEL_SEL_SHIFT)) & CLKCTL1_AUDIOMCLKSEL_SEL_MASK)
/*! @} */

/*! @name AUDIOMCLKDIV - Audio MCLK Clock Divider */
/*! @{ */
#define CLKCTL1_AUDIOMCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_AUDIOMCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Audio MCLK Clock Divider Value
 */
#define CLKCTL1_AUDIOMCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_DIV_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_DIV_MASK)
#define CLKCTL1_AUDIOMCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_AUDIOMCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_AUDIOMCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_RESET_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_RESET_MASK)
#define CLKCTL1_AUDIOMCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_AUDIOMCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_AUDIOMCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_HALT_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_HALT_MASK)
#define CLKCTL1_AUDIOMCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_AUDIOMCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_AUDIOMCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_AUDIOMCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_AUDIOMCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name CLKOUTSEL0 - CLKOUT Clock Select 0 */
/*! @{ */
#define CLKCTL1_CLKOUTSEL0_SEL_MASK              (0x7U)
#define CLKCTL1_CLKOUTSEL0_SEL_SHIFT             (0U)
/*! SEL - Clock Output Select 1st Stage
 *  0b000..OSC_CLK Clock
 *  0b001..Low Power Oscillator Clock (LPOSC)
 *  0b010..FRO Clock
 *  0b011..Main Clock
 *  0b100..DSP Main Clock
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_CLKOUTSEL0_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL0_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL0_SEL_MASK)
/*! @} */

/*! @name CLKOUTSEL1 - CLKOUT Clock Select 1 */
/*! @{ */
#define CLKCTL1_CLKOUTSEL1_SEL_MASK              (0x7U)
#define CLKCTL1_CLKOUTSEL1_SEL_SHIFT             (0U)
/*! SEL - Clock Out Source
 *  0b000..CLKOUTSEL0 Multiplexed Output
 *  0b001..Main System PLL Clock
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..DSP PLL Clock
 *  0b100..SYSPLL0 AUX1_PLL_Clock
 *  0b101..AUDIO PLL Clock
 *  0b110..32 KHz RTC Clock
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_CLKOUTSEL1_SEL(x)                (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTSEL1_SEL_SHIFT)) & CLKCTL1_CLKOUTSEL1_SEL_MASK)
/*! @} */

/*! @name CLKOUTFCLKDIV - CLKOUT Functional Clock Divider */
/*! @{ */
#define CLKCTL1_CLKOUTFCLKDIV_DIV_MASK           (0xFFU)
#define CLKCTL1_CLKOUTFCLKDIV_DIV_SHIFT          (0U)
/*! DIV - Clock-Out Clock Divider Value
 */
#define CLKCTL1_CLKOUTFCLKDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_DIV_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_DIV_MASK)
#define CLKCTL1_CLKOUTFCLKDIV_RESET_MASK         (0x20000000U)
#define CLKCTL1_CLKOUTFCLKDIV_RESET_SHIFT        (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_CLKOUTFCLKDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_RESET_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_RESET_MASK)
#define CLKCTL1_CLKOUTFCLKDIV_HALT_MASK          (0x40000000U)
#define CLKCTL1_CLKOUTFCLKDIV_HALT_SHIFT         (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_CLKOUTFCLKDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_HALT_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_HALT_MASK)
#define CLKCTL1_CLKOUTFCLKDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL1_CLKOUTFCLKDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed
 */
#define CLKCTL1_CLKOUTFCLKDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_CLKOUTFCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_CLKOUTFCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name I3C01FCLKSEL - I3C0, I3C1 Functional Clock Select */
/*! @{ */
#define CLKCTL1_I3C01FCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL1_I3C01FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - I3C0, I3C1 Clock Source
 *  0b000..Main Clock
 *  0b001..FRO Clock (Divided-by-8 selection)
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_I3C01FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSEL_SEL_SHIFT)) & CLKCTL1_I3C01FCLKSEL_SEL_MASK)
/*! @} */

/*! @name I3C01FCLKSTCSEL - I3C0, I3C1 Functional Slow Time Control Clock Select */
/*! @{ */
#define CLKCTL1_I3C01FCLKSTCSEL_SEL_MASK         (0x7U)
#define CLKCTL1_I3C01FCLKSTCSEL_SEL_SHIFT        (0U)
/*! SEL - I3C0, I3C1 Clock Source
 *  0b000..I3C0 FCLK
 *  0b001..Low Power Oscillator Clock (LPOSC)
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_I3C01FCLKSTCSEL_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCSEL_SEL_SHIFT)) & CLKCTL1_I3C01FCLKSTCSEL_SEL_MASK)
/*! @} */

/*! @name I3C01FCLKSTCDIV - I3C0, I3C1 Functional Slow Time Control Clock Divider */
/*! @{ */
#define CLKCTL1_I3C01FCLKSTCDIV_DIV_MASK         (0xFFU)
#define CLKCTL1_I3C01FCLKSTCDIV_DIV_SHIFT        (0U)
/*! DIV - I3C0, I3C1 Clock Divider Value
 */
#define CLKCTL1_I3C01FCLKSTCDIV_DIV(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_DIV_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_DIV_MASK)
#define CLKCTL1_I3C01FCLKSTCDIV_RESET_MASK       (0x20000000U)
#define CLKCTL1_I3C01FCLKSTCDIV_RESET_SHIFT      (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_I3C01FCLKSTCDIV_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_RESET_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_RESET_MASK)
#define CLKCTL1_I3C01FCLKSTCDIV_HALT_MASK        (0x40000000U)
#define CLKCTL1_I3C01FCLKSTCDIV_HALT_SHIFT       (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_I3C01FCLKSTCDIV_HALT(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_HALT_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_HALT_MASK)
#define CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_MASK     (0x80000000U)
#define CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_SHIFT    (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_I3C01FCLKSTCDIV_REQFLAG(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_SHIFT)) & CLKCTL1_I3C01FCLKSTCDIV_REQFLAG_MASK)
/*! @} */

/*! @name I3C01FCLKSDIV - I3C0, I3C1 Functional Slow Clock Divider */
/*! @{ */
#define CLKCTL1_I3C01FCLKSDIV_DIV_MASK           (0xFFU)
#define CLKCTL1_I3C01FCLKSDIV_DIV_SHIFT          (0U)
/*! DIV - I3C0, I3C1 Clock Divider Value
 */
#define CLKCTL1_I3C01FCLKSDIV_DIV(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_DIV_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_DIV_MASK)
#define CLKCTL1_I3C01FCLKSDIV_RESET_MASK         (0x20000000U)
#define CLKCTL1_I3C01FCLKSDIV_RESET_SHIFT        (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_I3C01FCLKSDIV_RESET(x)           (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_RESET_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_RESET_MASK)
#define CLKCTL1_I3C01FCLKSDIV_HALT_MASK          (0x40000000U)
#define CLKCTL1_I3C01FCLKSDIV_HALT_SHIFT         (30U)
/*! HALT - Halt the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_I3C01FCLKSDIV_HALT(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_HALT_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_HALT_MASK)
#define CLKCTL1_I3C01FCLKSDIV_REQFLAG_MASK       (0x80000000U)
#define CLKCTL1_I3C01FCLKSDIV_REQFLAG_SHIFT      (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_I3C01FCLKSDIV_REQFLAG(x)         (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSDIV_REQFLAG_SHIFT)) & CLKCTL1_I3C01FCLKSDIV_REQFLAG_MASK)
/*! @} */

/*! @name I3C01FCLKDIV - I3C0, I3C1 Functional Clock Divider */
/*! @{ */
#define CLKCTL1_I3C01FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_I3C01FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - I3C0, I3C1 Clock Divider Value
 */
#define CLKCTL1_I3C01FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_DIV_SHIFT)) & CLKCTL1_I3C01FCLKDIV_DIV_MASK)
#define CLKCTL1_I3C01FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_I3C01FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_I3C01FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_RESET_SHIFT)) & CLKCTL1_I3C01FCLKDIV_RESET_MASK)
#define CLKCTL1_I3C01FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_I3C01FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halts the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_I3C01FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_HALT_SHIFT)) & CLKCTL1_I3C01FCLKDIV_HALT_MASK)
#define CLKCTL1_I3C01FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_I3C01FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_I3C01FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_I3C01FCLKDIV_REQFLAG_MASK)
/*! @} */

/*! @name I3C01FCLKSTSTCLKSEL - I3C01 Functional Clock Select */
/*! @{ */
#define CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_MASK     (0x7U)
#define CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_SHIFT    (0U)
/*! SEL - I3C0, I3C1 FCLK Test Clock Source
 *  0b000..Low Power Oscillator Clock (LPOSC)
 *  0b001..Reserved
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL(x)       (((uint32_t)(((uint32_t)(x)) << CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_SHIFT)) & CLKCTL1_I3C01FCLKSTSTCLKSEL_SEL_MASK)
/*! @} */

/*! @name WDT1FCLKSEL - Watchdog Timer 1 Functional Clock Select */
/*! @{ */
#define CLKCTL1_WDT1FCLKSEL_SEL_MASK             (0x7U)
#define CLKCTL1_WDT1FCLKSEL_SEL_SHIFT            (0U)
/*! SEL - WDT1 Functional Clock Source
 *  0b000..Low Power Oscillator Clock (LPOSC)
 *  0b001..Main Clock
 *  0b010..Reserved
 *  0b011..Reserved
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_WDT1FCLKSEL_SEL(x)               (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
/*! @} */

/*! @name ACMP0FCLKSEL - Analog Comparator 0 Clock Select */
/*! @{ */
#define CLKCTL1_ACMP0FCLKSEL_SEL_MASK            (0x7U)
#define CLKCTL1_ACMP0FCLKSEL_SEL_SHIFT           (0U)
/*! SEL - ACMP0 Fast Functional Clock Source
 *  0b000..Main Clock
 *  0b001..FRO Clock (Divided-by-4 selection)
 *  0b010..SYSPLL0 AUX0_PLL_Clock
 *  0b011..SYSPLL0 AUX1_PLL_Clock
 *  0b100..Reserved
 *  0b101..Reserved
 *  0b110..Reserved
 *  0b111..None, output gated to reduce power
 */
#define CLKCTL1_ACMP0FCLKSEL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKSEL_SEL_SHIFT)) & CLKCTL1_ACMP0FCLKSEL_SEL_MASK)
/*! @} */

/*! @name ACMP0FCLKDIV - Analog comparator 0 FCLK divider */
/*! @{ */
#define CLKCTL1_ACMP0FCLKDIV_DIV_MASK            (0xFFU)
#define CLKCTL1_ACMP0FCLKDIV_DIV_SHIFT           (0U)
/*! DIV - Clock Out Clock Divider Value
 */
#define CLKCTL1_ACMP0FCLKDIV_DIV(x)              (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_DIV_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_DIV_MASK)
#define CLKCTL1_ACMP0FCLKDIV_RESET_MASK          (0x20000000U)
#define CLKCTL1_ACMP0FCLKDIV_RESET_SHIFT         (29U)
/*! RESET - Reset the Divider Counter
 *  0b0..No effect
 *  0b1..Reset the Divider Counter
 */
#define CLKCTL1_ACMP0FCLKDIV_RESET(x)            (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_RESET_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_RESET_MASK)
#define CLKCTL1_ACMP0FCLKDIV_HALT_MASK           (0x40000000U)
#define CLKCTL1_ACMP0FCLKDIV_HALT_SHIFT          (30U)
/*! HALT - Halts the Divider Counter
 *  0b0..No effect
 *  0b1..Halt (stop) the Divider Counter
 */
#define CLKCTL1_ACMP0FCLKDIV_HALT(x)             (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_HALT_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_HALT_MASK)
#define CLKCTL1_ACMP0FCLKDIV_REQFLAG_MASK        (0x80000000U)
#define CLKCTL1_ACMP0FCLKDIV_REQFLAG_SHIFT       (31U)
/*! REQFLAG - Divider Status Flag
 *  0b0..The Divider change has finished (clock being divided must be running for this status to change).
 *  0b1..The Divider value has changed.
 */
#define CLKCTL1_ACMP0FCLKDIV_REQFLAG(x)          (((uint32_t)(((uint32_t)(x)) << CLKCTL1_ACMP0FCLKDIV_REQFLAG_SHIFT)) & CLKCTL1_ACMP0FCLKDIV_REQFLAG_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CLKCTL1_Register_Masks */


/* CLKCTL1 - Peripheral instance base addresses */
/** Peripheral CLKCTL1 base address */
#define CLKCTL1_BASE                             (0x40021000u)
/** Peripheral CLKCTL1 base pointer */
#define CLKCTL1                                  ((CLKCTL1_Type *)CLKCTL1_BASE)
/** Array initializer of CLKCTL1 peripheral base addresses */
#define CLKCTL1_BASE_ADDRS                       { CLKCTL1_BASE }
/** Array initializer of CLKCTL1 peripheral base pointers */
#define CLKCTL1_BASE_PTRS                        { CLKCTL1 }

/*!
 * @}
 */ /* end of group CLKCTL1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CRC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
 * @{
 */

/** CRC - Register Layout Typedef */
typedef struct {
  __IO uint32_t MODE;                              /**< MODE Register, offset: 0x0 */
  __IO uint32_t SEED;                              /**< CRC Seed Register, offset: 0x4 */
  union {                                          /* offset: 0x8 */
    __I  uint32_t SUM;                               /**< CRC Sum, offset: 0x8 */
    __IO uint32_t WR_DATA;                           /**< CRC Write Data, offset: 0x8 */
  };
} CRC_Type;

/* ----------------------------------------------------------------------------
   -- CRC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CRC_Register_Masks CRC Register Masks
 * @{
 */

/*! @name MODE - MODE Register */
/*! @{ */
#define CRC_MODE_CRC_POLY_MASK                   (0x3U)
#define CRC_MODE_CRC_POLY_SHIFT                  (0U)
/*! CRC_POLY - CRC Polynomial
 *  0b00..Use CRC-CCITT polynomial
 *  0b01..Use CRC-16 polynomial
 *  0b10..Use CRC-32 polynomial
 *  0b11..Reserved
 */
#define CRC_MODE_CRC_POLY(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
#define CRC_MODE_BIT_RVS_WR_MASK                 (0x4U)
#define CRC_MODE_BIT_RVS_WR_SHIFT                (2U)
/*! BIT_RVS_WR - Bit-order Reverse for Write Data
 *  0b0..Do not use bit-order reverse for WR_DATA (per byte)
 *  0b1..Use bit-order reverse for WR_DATA (per byte)
 */
#define CRC_MODE_BIT_RVS_WR(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
#define CRC_MODE_CMPL_WR_MASK                    (0x8U)
#define CRC_MODE_CMPL_WR_SHIFT                   (3U)
/*! CMPL_WR - 1's Complement for Write Data
 *  0b0..Do not use 1's complement for WR_DATA
 *  0b1..Use 1's complement for WR_DATA
 */
#define CRC_MODE_CMPL_WR(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
#define CRC_MODE_BIT_RVS_SUM_MASK                (0x10U)
#define CRC_MODE_BIT_RVS_SUM_SHIFT               (4U)
/*! BIT_RVS_SUM - Bit-order Reverse for CRC Sum
 *  0b0..Do not use bit-order reverse for CRC Sum
 *  0b1..Use bit-order reverse for CRC Sum
 */
#define CRC_MODE_BIT_RVS_SUM(x)                  (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
#define CRC_MODE_CMPL_SUM_MASK                   (0x20U)
#define CRC_MODE_CMPL_SUM_SHIFT                  (5U)
/*! CMPL_SUM - 1's Complement for CRC Sum
 *  0b0..Do not use 1's complement for CRC Sum
 *  0b1..Use 1's complement for CRC Sum
 */
#define CRC_MODE_CMPL_SUM(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
/*! @} */

/*! @name SEED - CRC Seed Register */
/*! @{ */
#define CRC_SEED_CRC_SEED_MASK                   (0xFFFFFFFFU)
#define CRC_SEED_CRC_SEED_SHIFT                  (0U)
/*! CRC_SEED - CRC Seed
 */
#define CRC_SEED_CRC_SEED(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
/*! @} */

/*! @name SUM - CRC Sum */
/*! @{ */
#define CRC_SUM_CRC_SUM_MASK                     (0xFFFFFFFFU)
#define CRC_SUM_CRC_SUM_SHIFT                    (0U)
/*! CRC_SUM - CRC Sum
 */
#define CRC_SUM_CRC_SUM(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
/*! @} */

/*! @name WR_DATA - CRC Write Data */
/*! @{ */
#define CRC_WR_DATA_WR_DATA_MASK                 (0xFFFFFFFFU)
#define CRC_WR_DATA_WR_DATA_SHIFT                (0U)
/*! WR_DATA - CRC Write Data
 */
#define CRC_WR_DATA_WR_DATA(x)                   (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_WR_DATA_SHIFT)) & CRC_WR_DATA_WR_DATA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group CRC_Register_Masks */


/* CRC - Peripheral instance base addresses */
/** Peripheral CRC_ENGINE base address */
#define CRC_ENGINE_BASE                          (0x40120000u)
/** Peripheral CRC_ENGINE base pointer */
#define CRC_ENGINE                               ((CRC_Type *)CRC_ENGINE_BASE)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS                           { CRC_ENGINE_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS                            { CRC_ENGINE }

/*!
 * @}
 */ /* end of group CRC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- CTIMER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
 * @{
 */

/** CTIMER - Register Layout Typedef */
typedef struct {
  __IO uint32_t IR;                                /**< Interrupt Register., offset: 0x0 */
  __IO uint32_t TCR;                               /**< Timer Control Register, offset: 0x4 */
  __IO uint32_t TC;                                /**< Timer Counter, offset: 0x8 */
  __IO uint32_t PR;                                /**< Prescale Register, offset: 0xC */
  __IO uint32_t PC;                                /**< Prescale Counter., offset: 0x10 */
  __IO uint32_t MCR;                               /**< Match Control Register., offset: 0x14 */
  __IO uint32_t MR[4];                             /**< Match Register, array offset: 0x18, array step: 0x4 */
  __IO uint32_t CCR;                               /**< Capture Control Register, offset: 0x28 */
  __I  uint32_t CR[4];                             /**< Capture Register, array offset: 0x2C, array step: 0x4 */
  __IO uint32_t EMR;                               /**< External Match Register, offset: 0x3C */
       uint8_t RESERVED_0[48];
  __IO uint32_t CTCR;                              /**< Count Control Register, offset: 0x70 */
  __IO uint32_t PWMC;                              /**< PWM Control Register, offset: 0x74 */
  __IO uint32_t MSR[4];                            /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
} CTIMER_Type;

/* ----------------------------------------------------------------------------
   -- CTIMER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
 * @{
 */

/*! @name IR - Interrupt Register. */
/*! @{ */
#define CTIMER_IR_MR0INT_MASK                    (0x1U)
#define CTIMER_IR_MR0INT_SHIFT                   (0U)
/*! MR0INT - Interrupt flag for match channel 0
 */
#define CTIMER_IR_MR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
#define CTIMER_IR_MR1INT_MASK                    (0x2U)
#define CTIMER_IR_MR1INT_SHIFT                   (1U)
/*! MR1INT - Interrupt flag for match channel 1
 */
#define CTIMER_IR_MR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
#define CTIMER_IR_MR2INT_MASK                    (0x4U)
#define CTIMER_IR_MR2INT_SHIFT                   (2U)
/*! MR2INT - Interrupt flag for match channel 2
 */
#define CTIMER_IR_MR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
#define CTIMER_IR_MR3INT_MASK                    (0x8U)
#define CTIMER_IR_MR3INT_SHIFT                   (3U)
/*! MR3INT - Interrupt flag for match channel 3
 */
#define CTIMER_IR_MR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
#define CTIMER_IR_CR0INT_MASK                    (0x10U)
#define CTIMER_IR_CR0INT_SHIFT                   (4U)
/*! CR0INT - Interrupt flag for capture channel 0 event
 */
#define CTIMER_IR_CR0INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
#define CTIMER_IR_CR1INT_MASK                    (0x20U)
#define CTIMER_IR_CR1INT_SHIFT                   (5U)
/*! CR1INT - Interrupt flag for capture channel 1 event
 */
#define CTIMER_IR_CR1INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
#define CTIMER_IR_CR2INT_MASK                    (0x40U)
#define CTIMER_IR_CR2INT_SHIFT                   (6U)
/*! CR2INT - Interrupt flag for capture channel 2 event
 */
#define CTIMER_IR_CR2INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
#define CTIMER_IR_CR3INT_MASK                    (0x80U)
#define CTIMER_IR_CR3INT_SHIFT                   (7U)
/*! CR3INT - Interrupt flag for capture channel 3 event
 */
#define CTIMER_IR_CR3INT(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
/*! @} */

/*! @name TCR - Timer Control Register */
/*! @{ */
#define CTIMER_TCR_CEN_MASK                      (0x1U)
#define CTIMER_TCR_CEN_SHIFT                     (0U)
/*! CEN - Counter enable.
 *  0b0..Disabled. The counters are disabled.
 *  0b1..Enabled. The Timer Counter and Prescale Counter are enabled.
 */
#define CTIMER_TCR_CEN(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
#define CTIMER_TCR_CRST_MASK                     (0x2U)
#define CTIMER_TCR_CRST_SHIFT                    (1U)
/*! CRST - Counter reset.
 *  0b0..Disabled. Do nothing.
 *  0b1..Enabled
 */
#define CTIMER_TCR_CRST(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
/*! @} */

/*! @name TC - Timer Counter */
/*! @{ */
#define CTIMER_TC_TCVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_TC_TCVAL_SHIFT                    (0U)
/*! TCVAL - Timer counter value.
 */
#define CTIMER_TC_TCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
/*! @} */

/*! @name PR - Prescale Register */
/*! @{ */
#define CTIMER_PR_PRVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_PR_PRVAL_SHIFT                    (0U)
/*! PRVAL - Prescale reload value.
 */
#define CTIMER_PR_PRVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
/*! @} */

/*! @name PC - Prescale Counter. */
/*! @{ */
#define CTIMER_PC_PCVAL_MASK                     (0xFFFFFFFFU)
#define CTIMER_PC_PCVAL_SHIFT                    (0U)
/*! PCVAL - Prescale counter value.
 */
#define CTIMER_PC_PCVAL(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
/*! @} */

/*! @name MCR - Match Control Register. */
/*! @{ */
#define CTIMER_MCR_MR0I_MASK                     (0x1U)
#define CTIMER_MCR_MR0I_SHIFT                    (0U)
/*! MR0I - Interrupt on MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
#define CTIMER_MCR_MR0R_MASK                     (0x2U)
#define CTIMER_MCR_MR0R_SHIFT                    (1U)
/*! MR0R - Reset on MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
#define CTIMER_MCR_MR0S_MASK                     (0x4U)
#define CTIMER_MCR_MR0S_SHIFT                    (2U)
/*! MR0S - Stop on MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
#define CTIMER_MCR_MR1I_MASK                     (0x8U)
#define CTIMER_MCR_MR1I_SHIFT                    (3U)
/*! MR1I - Interrupt on MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
#define CTIMER_MCR_MR1R_MASK                     (0x10U)
#define CTIMER_MCR_MR1R_SHIFT                    (4U)
/*! MR1R - Reset on MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
#define CTIMER_MCR_MR1S_MASK                     (0x20U)
#define CTIMER_MCR_MR1S_SHIFT                    (5U)
/*! MR1S - Stop on MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
#define CTIMER_MCR_MR2I_MASK                     (0x40U)
#define CTIMER_MCR_MR2I_SHIFT                    (6U)
/*! MR2I - Interrupt on MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
#define CTIMER_MCR_MR2R_MASK                     (0x80U)
#define CTIMER_MCR_MR2R_SHIFT                    (7U)
/*! MR2R - Reset on MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
#define CTIMER_MCR_MR2S_MASK                     (0x100U)
#define CTIMER_MCR_MR2S_SHIFT                    (8U)
/*! MR2S - Stop on MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
#define CTIMER_MCR_MR3I_MASK                     (0x200U)
#define CTIMER_MCR_MR3I_SHIFT                    (9U)
/*! MR3I - Interrupt on MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3I(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
#define CTIMER_MCR_MR3R_MASK                     (0x400U)
#define CTIMER_MCR_MR3R_SHIFT                    (10U)
/*! MR3R - Reset on MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3R(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
#define CTIMER_MCR_MR3S_MASK                     (0x800U)
#define CTIMER_MCR_MR3S_SHIFT                    (11U)
/*! MR3S - Stop on MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3S(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
#define CTIMER_MCR_MR0RL_MASK                    (0x1000000U)
#define CTIMER_MCR_MR0RL_SHIFT                   (24U)
/*! MR0RL - Reload MR0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR0RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
#define CTIMER_MCR_MR1RL_MASK                    (0x2000000U)
#define CTIMER_MCR_MR1RL_SHIFT                   (25U)
/*! MR1RL - Reload MR1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR1RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
#define CTIMER_MCR_MR2RL_MASK                    (0x4000000U)
#define CTIMER_MCR_MR2RL_SHIFT                   (26U)
/*! MR2RL - Reload MR2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR2RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
#define CTIMER_MCR_MR3RL_MASK                    (0x8000000U)
#define CTIMER_MCR_MR3RL_SHIFT                   (27U)
/*! MR3RL - Reload MR3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_MCR_MR3RL(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
/*! @} */

/*! @name MR - Match Register */
/*! @{ */
#define CTIMER_MR_MATCH_MASK                     (0xFFFFFFFFU)
#define CTIMER_MR_MATCH_SHIFT                    (0U)
/*! MATCH - Timer counter match value.
 */
#define CTIMER_MR_MATCH(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
/*! @} */

/* The count of CTIMER_MR */
#define CTIMER_MR_COUNT                          (4U)

/*! @name CCR - Capture Control Register */
/*! @{ */
#define CTIMER_CCR_CAP0RE_MASK                   (0x1U)
#define CTIMER_CCR_CAP0RE_SHIFT                  (0U)
/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP0RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
#define CTIMER_CCR_CAP0FE_MASK                   (0x2U)
#define CTIMER_CCR_CAP0FE_SHIFT                  (1U)
/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP0FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
#define CTIMER_CCR_CAP0I_MASK                    (0x4U)
#define CTIMER_CCR_CAP0I_SHIFT                   (2U)
/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP0I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
#define CTIMER_CCR_CAP1RE_MASK                   (0x8U)
#define CTIMER_CCR_CAP1RE_SHIFT                  (3U)
/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP1RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
#define CTIMER_CCR_CAP1FE_MASK                   (0x10U)
#define CTIMER_CCR_CAP1FE_SHIFT                  (4U)
/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP1FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
#define CTIMER_CCR_CAP1I_MASK                    (0x20U)
#define CTIMER_CCR_CAP1I_SHIFT                   (5U)
/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP1I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
#define CTIMER_CCR_CAP2RE_MASK                   (0x40U)
#define CTIMER_CCR_CAP2RE_SHIFT                  (6U)
/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP2RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
#define CTIMER_CCR_CAP2FE_MASK                   (0x80U)
#define CTIMER_CCR_CAP2FE_SHIFT                  (7U)
/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP2FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
#define CTIMER_CCR_CAP2I_MASK                    (0x100U)
#define CTIMER_CCR_CAP2I_SHIFT                   (8U)
/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP2I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
#define CTIMER_CCR_CAP3RE_MASK                   (0x200U)
#define CTIMER_CCR_CAP3RE_SHIFT                  (9U)
/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP3RE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
#define CTIMER_CCR_CAP3FE_MASK                   (0x400U)
#define CTIMER_CCR_CAP3FE_SHIFT                  (10U)
/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP3FE(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
#define CTIMER_CCR_CAP3I_MASK                    (0x800U)
#define CTIMER_CCR_CAP3I_SHIFT                   (11U)
/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define CTIMER_CCR_CAP3I(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
/*! @} */

/*! @name CR - Capture Register */
/*! @{ */
#define CTIMER_CR_CAP_MASK                       (0xFFFFFFFFU)
#define CTIMER_CR_CAP_SHIFT                      (0U)
/*! CAP - Timer counter capture value.
 */
#define CTIMER_CR_CAP(x)                         (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
/*! @} */

/* The count of CTIMER_CR */
#define CTIMER_CR_COUNT                          (4U)

/*! @name EMR - External Match Register */
/*! @{ */
#define CTIMER_EMR_EM0_MASK                      (0x1U)
#define CTIMER_EMR_EM0_SHIFT                     (0U)
/*! EM0 - External Match 0
 */
#define CTIMER_EMR_EM0(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
#define CTIMER_EMR_EM1_MASK                      (0x2U)
#define CTIMER_EMR_EM1_SHIFT                     (1U)
/*! EM1 - External Match 1
 */
#define CTIMER_EMR_EM1(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
#define CTIMER_EMR_EM2_MASK                      (0x4U)
#define CTIMER_EMR_EM2_SHIFT                     (2U)
/*! EM2 - External Match 2
 */
#define CTIMER_EMR_EM2(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
#define CTIMER_EMR_EM3_MASK                      (0x8U)
#define CTIMER_EMR_EM3_SHIFT                     (3U)
/*! EM3 - External Match 3
 */
#define CTIMER_EMR_EM3(x)                        (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
#define CTIMER_EMR_EMC0_MASK                     (0x30U)
#define CTIMER_EMR_EMC0_SHIFT                    (4U)
/*! EMC0 - External Match Control 0
 *  0b00..Do Nothing.
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).
 *  0b11..Toggle. Toggle the corresponding External Match bit/output.
 */
#define CTIMER_EMR_EMC0(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
#define CTIMER_EMR_EMC1_MASK                     (0xC0U)
#define CTIMER_EMR_EMC1_SHIFT                    (6U)
/*! EMC1 - External Match Control 1
 *  0b00..Do Nothing
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).
 *  0b11..Toggle. Toggle the corresponding External Match bit/output.
 */
#define CTIMER_EMR_EMC1(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
#define CTIMER_EMR_EMC2_MASK                     (0x300U)
#define CTIMER_EMR_EMC2_SHIFT                    (8U)
/*! EMC2 - External Match Control 2
 *  0b00..Do Nothing.
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).
 *  0b11..Toggle. Toggle the corresponding External Match bit/output.
 */
#define CTIMER_EMR_EMC2(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
#define CTIMER_EMR_EMC3_MASK                     (0xC00U)
#define CTIMER_EMR_EMC3_SHIFT                    (10U)
/*! EMC3 - External Match Control 3
 *  0b00..Do Nothing.
 *  0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).
 *  0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).
 *  0b11..Toggle. Toggle the corresponding External Match bit/output.
 */
#define CTIMER_EMR_EMC3(x)                       (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
/*! @} */

/*! @name CTCR - Count Control Register */
/*! @{ */
#define CTIMER_CTCR_CTMODE_MASK                  (0x3U)
#define CTIMER_CTCR_CTMODE_SHIFT                 (0U)
/*! CTMODE - The Count Control Register (CTCR) is used to select between Timer and Counter mode, and
 *    in Counter mode to select the pin and edge(s) for counting. When Counter Mode is chosen as a
 *    mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising
 *    edge of the CTIMER function clock. After comparing two consecutive samples of this CAP input,
 *    one of the following four events is recognized: rising edge, falling edge, either of edges or no
 *    changes in the level of the selected CAP input. Only if the identified event occurs and the
 *    event corresponds to the one selected by bits 1:0 in the CTCR register, will the Timer Counter
 *    register be incremented. Effective processing of the externally supplied clock to the counter
 *    has some limitations. Since two successive rising edges of the CTIMER function clock are used
 *    to identify only one edge on the CAP selected input, the frequency of the CAP input cannot
 *    exceed one half of the CTIMER function clock. Consequently, duration of the HIGH/LOWLOW levels on
 *    the same CAP input in this case cannot be shorter than a CTIMER function clock. Bits 7:4 of
 *    this register are also used to enable and configure the capture-clears-timer feature. This
 *    feature allows for a designated edge on a particular CAP input to reset the timer to all zeros.
 *    Using this mechanism to clear the timer on the leading edge of an input pulse and performing a
 *    capture on the trailing edge, permits direct pulse-width measurement using a single capture
 *    input without the need to perform a subtraction operation in software.
 *  0b00..Timer Mode
 *  0b01..Counter Mode rising edge
 *  0b10..Counter Mode falling edge
 *  0b11..Counter Mode dual edge
 */
#define CTIMER_CTCR_CTMODE(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
#define CTIMER_CTCR_CINSEL_MASK                  (0xCU)
#define CTIMER_CTCR_CINSEL_SHIFT                 (2U)
/*! CINSEL - Count Input Select
 *  0b00..Channel 0. CAPn.0 for CTIMERn
 *  0b01..Channel 1. CAPn.1 for CTIMERn
 *  0b10..Channel 2. CAPn.2 for CTIMERn
 *  0b11..Channel 3. CAPn.3 for CTIMERn
 */
#define CTIMER_CTCR_CINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
#define CTIMER_CTCR_ENCC_MASK                    (0x10U)
#define CTIMER_CTCR_ENCC_SHIFT                   (4U)
#define CTIMER_CTCR_ENCC(x)                      (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
#define CTIMER_CTCR_SELCC_MASK                   (0xE0U)
#define CTIMER_CTCR_SELCC_SHIFT                  (5U)
/*! SELCC - Edge select
 *  0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
 *  0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).
 *  0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
 *  0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).
 *  0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
 *  0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).
 */
#define CTIMER_CTCR_SELCC(x)                     (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
/*! @} */

/*! @name PWMC - PWM Control Register */
/*! @{ */
#define CTIMER_PWMC_PWMEN0_MASK                  (0x1U)
#define CTIMER_PWMC_PWMEN0_SHIFT                 (0U)
/*! PWMEN0 - PWM mode enable for channel0.
 *  0b0..Match. CTIMERn_MAT0 is controlled by EM0.
 *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.
 */
#define CTIMER_PWMC_PWMEN0(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
#define CTIMER_PWMC_PWMEN1_MASK                  (0x2U)
#define CTIMER_PWMC_PWMEN1_SHIFT                 (1U)
/*! PWMEN1 - PWM mode enable for channel1.
 *  0b0..Match. CTIMERn_MAT01 is controlled by EM1.
 *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.
 */
#define CTIMER_PWMC_PWMEN1(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
#define CTIMER_PWMC_PWMEN2_MASK                  (0x4U)
#define CTIMER_PWMC_PWMEN2_SHIFT                 (2U)
/*! PWMEN2 - PWM mode enable for channel2.
 *  0b0..Match. CTIMERn_MAT2 is controlled by EM2.
 *  0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.
 */
#define CTIMER_PWMC_PWMEN2(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
#define CTIMER_PWMC_PWMEN3_MASK                  (0x8U)
#define CTIMER_PWMC_PWMEN3_SHIFT                 (3U)
/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.
 *  0b0..Match. CTIMERn_MAT3 is controlled by EM3.
 *  0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.
 */
#define CTIMER_PWMC_PWMEN3(x)                    (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
/*! @} */

/*! @name MSR - Match Shadow Register */
/*! @{ */
#define CTIMER_MSR_MATCH_SHADOW_MASK             (0xFFFFFFFFU)
#define CTIMER_MSR_MATCH_SHADOW_SHIFT            (0U)
/*! MATCH_SHADOW - Timer counter match shadow value.
 */
#define CTIMER_MSR_MATCH_SHADOW(x)               (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK)
/*! @} */

/* The count of CTIMER_MSR */
#define CTIMER_MSR_COUNT                         (4U)


/*!
 * @}
 */ /* end of group CTIMER_Register_Masks */


/* CTIMER - Peripheral instance base addresses */
/** Peripheral CTIMER0 base address */
#define CTIMER0_BASE                             (0x40028000u)
/** Peripheral CTIMER0 base pointer */
#define CTIMER0                                  ((CTIMER_Type *)CTIMER0_BASE)
/** Peripheral CTIMER1 base address */
#define CTIMER1_BASE                             (0x40029000u)
/** Peripheral CTIMER1 base pointer */
#define CTIMER1                                  ((CTIMER_Type *)CTIMER1_BASE)
/** Peripheral CTIMER2 base address */
#define CTIMER2_BASE                             (0x4002A000u)
/** Peripheral CTIMER2 base pointer */
#define CTIMER2                                  ((CTIMER_Type *)CTIMER2_BASE)
/** Peripheral CTIMER3 base address */
#define CTIMER3_BASE                             (0x4002B000u)
/** Peripheral CTIMER3 base pointer */
#define CTIMER3                                  ((CTIMER_Type *)CTIMER3_BASE)
/** Peripheral CTIMER4 base address */
#define CTIMER4_BASE                             (0x4002C000u)
/** Peripheral CTIMER4 base pointer */
#define CTIMER4                                  ((CTIMER_Type *)CTIMER4_BASE)
/** Array initializer of CTIMER peripheral base addresses */
#define CTIMER_BASE_ADDRS                        { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
/** Array initializer of CTIMER peripheral base pointers */
#define CTIMER_BASE_PTRS                         { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
/** Interrupt vectors for the CTIMER peripheral type */
#define CTIMER_IRQS                              { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }

/*!
 * @}
 */ /* end of group CTIMER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DEBUGGER_MAILBOX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DEBUGGER_MAILBOX_Peripheral_Access_Layer DEBUGGER_MAILBOX Peripheral Access Layer
 * @{
 */

/** DEBUGGER_MAILBOX - Register Layout Typedef */
typedef struct {
  __IO uint32_t CSW;                               /**< Command and status word, offset: 0x0 */
  __IO uint32_t REQUEST;                           /**< Request Value, offset: 0x4 */
  __IO uint32_t RETURN;                            /**< Return Value, offset: 0x8 */
       uint8_t RESERVED_0[240];
  __I  uint32_t ID;                                /**< Identification, offset: 0xFC */
} DEBUGGER_MAILBOX_Type;

/* ----------------------------------------------------------------------------
   -- DEBUGGER_MAILBOX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DEBUGGER_MAILBOX_Register_Masks DEBUGGER_MAILBOX Register Masks
 * @{
 */

/*! @name CSW - Command and status word */
/*! @{ */
#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK    (0x1U)
#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT   (0U)
/*! RESYNCH_REQ - Re-synchronization Request
 *  0b0..No Request
 *  0b1..Request for re-synchronization
 */
#define DEBUGGER_MAILBOX_CSW_RESYNCH_REQ(x)      (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_RESYNCH_REQ_MASK)
#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK    (0x2U)
#define DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT   (1U)
/*! REQ_PENDING - Request Pending
 *  0b0..No Request Pending
 *  0b1..Request for Re-synchronization Pending
 */
#define DEBUGGER_MAILBOX_CSW_REQ_PENDING(x)      (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGGER_MAILBOX_CSW_REQ_PENDING_MASK)
#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK     (0x4U)
#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT    (2U)
/*! DBG_OR_ERR - Debug Overrun Error
 *  0b0..No Debug Overrun error
 *  0b1..Debug Overrun Error. A debug overrun occurred.
 */
#define DEBUGGER_MAILBOX_CSW_DBG_OR_ERR(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_DBG_OR_ERR_MASK)
#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK     (0x8U)
#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT    (3U)
/*! AHB_OR_ERR - When 1, an AHB overrun has occurred: a RETURN value has been overwritten by the
 *    device before the RETURN value was read by the debugger.
 *  0b0..No AHB Overrun Error
 *  0b1..AHB Overrun Error. An AHB overrun occurred.
 */
#define DEBUGGER_MAILBOX_CSW_AHB_OR_ERR(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGGER_MAILBOX_CSW_AHB_OR_ERR_MASK)
#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK     (0x10U)
#define DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT    (4U)
/*! SOFT_RESET - Soft Reset
 */
#define DEBUGGER_MAILBOX_CSW_SOFT_RESET(x)       (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGGER_MAILBOX_CSW_SOFT_RESET_MASK)
#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)
#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)
/*! CHIP_RESET_REQ - Chip Reset Request
 */
#define DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ(x)   (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGGER_MAILBOX_CSW_CHIP_RESET_REQ_MASK)
/*! @} */

/*! @name REQUEST - Request Value */
/*! @{ */
#define DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK    (0xFFFFFFFFU)
#define DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT   (0U)
/*! REQUEST - Request Value
 */
#define DEBUGGER_MAILBOX_REQUEST_REQUEST(x)      (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGGER_MAILBOX_REQUEST_REQUEST_MASK)
/*! @} */

/*! @name RETURN - Return Value */
/*! @{ */
#define DEBUGGER_MAILBOX_RETURN_RETURN_MASK      (0xFFFFFFFFU)
#define DEBUGGER_MAILBOX_RETURN_RETURN_SHIFT     (0U)
/*! RETURN - Return Value
 */
#define DEBUGGER_MAILBOX_RETURN_RETURN(x)        (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_RETURN_RETURN_SHIFT)) & DEBUGGER_MAILBOX_RETURN_RETURN_MASK)
/*! @} */

/*! @name ID - Identification */
/*! @{ */
#define DEBUGGER_MAILBOX_ID_ID_MASK              (0xFFFFFFFFU)
#define DEBUGGER_MAILBOX_ID_ID_SHIFT             (0U)
/*! ID - Identification Value
 */
#define DEBUGGER_MAILBOX_ID_ID(x)                (((uint32_t)(((uint32_t)(x)) << DEBUGGER_MAILBOX_ID_ID_SHIFT)) & DEBUGGER_MAILBOX_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DEBUGGER_MAILBOX_Register_Masks */


/* DEBUGGER_MAILBOX - Peripheral instance base addresses */
/** Peripheral DEBUGGER_MAILBOX base address */
#define DEBUGGER_MAILBOX_BASE                    (0x4010F000u)
/** Peripheral DEBUGGER_MAILBOX base pointer */
#define DEBUGGER_MAILBOX                         ((DEBUGGER_MAILBOX_Type *)DEBUGGER_MAILBOX_BASE)
/** Array initializer of DEBUGGER_MAILBOX peripheral base addresses */
#define DEBUGGER_MAILBOX_BASE_ADDRS              { DEBUGGER_MAILBOX_BASE }
/** Array initializer of DEBUGGER_MAILBOX peripheral base pointers */
#define DEBUGGER_MAILBOX_BASE_PTRS               { DEBUGGER_MAILBOX }

/*!
 * @}
 */ /* end of group DEBUGGER_MAILBOX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMA Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 * @{
 */

/** DMA - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< DMA control, offset: 0x0 */
  __I  uint32_t INTSTAT;                           /**< Interrupt status, offset: 0x4 */
  __IO uint32_t SRAMBASE;                          /**< SRAM address of the channel configuration table, offset: 0x8 */
       uint8_t RESERVED_0[20];
  struct {                                         /* offset: 0x20, array step: 0x60 */
    __IO uint32_t ENABLESET;                         /**< Channel Enable read and set for all DMA channels, array offset: 0x20, array step: 0x60 */
    __IO uint32_t ENABLESET1;                        /**< Channel Enable read and set for all DMA channels, array offset: 0x24, array step: 0x60 */
    __IO uint32_t ENABLECLR;                         /**< Channel Enable Clear for all DMA channels, array offset: 0x28, array step: 0x60 */
    __IO uint32_t ENABLECLR1;                        /**< Channel Enable Clear for all DMA channels, array offset: 0x2C, array step: 0x60 */
    __I  uint32_t ACTIVE;                            /**< Channel Active status for all DMA channels, array offset: 0x30, array step: 0x60 */
    __I  uint32_t ACTIVE1;                           /**< Channel Active status for all DMA channels, array offset: 0x34, array step: 0x60 */
    __I  uint32_t BUSY;                              /**< Channel Busy status for all DMA channels, array offset: 0x38, array step: 0x60 */
    __I  uint32_t BUSY1;                             /**< Channel Busy status for all DMA channels, array offset: 0x3C, array step: 0x60 */
    __IO uint32_t ERRINT;                            /**< Error Interrupt status for all DMA channels, array offset: 0x40, array step: 0x60 */
    __IO uint32_t ERRINT1;                           /**< Error Interrupt status for all DMA channels, array offset: 0x44, array step: 0x60 */
    __IO uint32_t INTENSET;                          /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x48, array step: 0x60 */
    __IO uint32_t INTENSET1;                         /**< Interrupt Enable read and Set for all DMA channels, array offset: 0x4C, array step: 0x60 */
    __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear for all DMA channels, array offset: 0x50, array step: 0x60 */
    __O  uint32_t INTENCLR1;                         /**< Interrupt Enable Clear for all DMA channels, array offset: 0x54, array step: 0x60 */
    __IO uint32_t INTA;                              /**< Interrupt A status for all DMA channels, array offset: 0x58, array step: 0x60 */
    __IO uint32_t INTA1;                             /**< Interrupt A status for all DMA channels, array offset: 0x5C, array step: 0x60 */
    __IO uint32_t INTB;                              /**< Interrupt B status for all DMA channels, array offset: 0x60, array step: 0x60 */
    __IO uint32_t INTB1;                             /**< Interrupt B status for all DMA channels, array offset: 0x64, array step: 0x60 */
    __O  uint32_t SETVALID;                          /**< Set ValidPending control bits for all DMA channels, array offset: 0x68, array step: 0x60 */
    __O  uint32_t SETVALID1;                         /**< Set ValidPending control bits for all DMA channels, array offset: 0x6C, array step: 0x60 */
    __O  uint32_t SETTRIG;                           /**< Set Trigger control bits for all DMA channels, array offset: 0x70, array step: 0x60 */
    __O  uint32_t SETTRIG1;                          /**< Set Trigger control bits for all DMA channels, array offset: 0x74, array step: 0x60 */
    __O  uint32_t ABORT;                             /**< Channel Abort control for all DMA channels, array offset: 0x78, array step: 0x60 */
    __O  uint32_t ABORT1;                            /**< Channel Abort control for all DMA channels, array offset: 0x7C, array step: 0x60 */
  } COMMON[1];
       uint8_t RESERVED_1[896];
  struct {                                         /* offset: 0x400, array step: 0x10 */
    __IO uint32_t CFG;                               /**< Configuration register for DMA channel, array offset: 0x400, array step: 0x10 */
    __I  uint32_t CTLSTAT;                           /**< Control and status register for DMA channel, array offset: 0x404, array step: 0x10 */
    __IO uint32_t XFERCFG;                           /**< Transfer configuration register for DMA channel, array offset: 0x408, array step: 0x10 */
         uint8_t RESERVED_0[4];
  } CHANNEL[37];
} DMA_Type;

/* ----------------------------------------------------------------------------
   -- DMA Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMA_Register_Masks DMA Register Masks
 * @{
 */

/*! @name CTRL - DMA control */
/*! @{ */
#define DMA_CTRL_ENABLE_MASK                     (0x1U)
#define DMA_CTRL_ENABLE_SHIFT                    (0U)
/*! ENABLE - DMA controller master enable.
 *  0b0..DMA controller is disabled.
 *  0b1..Enabled.
 */
#define DMA_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt status */
/*! @{ */
#define DMA_INTSTAT_ACTIVEINT_MASK               (0x2U)
#define DMA_INTSTAT_ACTIVEINT_SHIFT              (1U)
/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
 *  0b0..No enabled interrupts are pending.
 *  0b1..At least one enabled interrupt is pending.
 */
#define DMA_INTSTAT_ACTIVEINT(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
#define DMA_INTSTAT_ACTIVEERRINT_MASK            (0x4U)
#define DMA_INTSTAT_ACTIVEERRINT_SHIFT           (2U)
/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
 *  0b0..No error interrupts are pending.
 *  0b1..At least one error interrupt is pending.
 */
#define DMA_INTSTAT_ACTIVEERRINT(x)              (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
/*! @} */

/*! @name SRAMBASE - SRAM address of the channel configuration table */
/*! @{ */
#define DMA_SRAMBASE_OFFSET_MASK                 (0xFFFFFE00U)
#define DMA_SRAMBASE_OFFSET_SHIFT                (9U)
/*! OFFSET - Offset
 */
#define DMA_SRAMBASE_OFFSET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
/*! @} */

/*! @name COMMON_ENABLESET - Channel Enable read and set for all DMA channels */
/*! @{ */
#define DMA_COMMON_ENABLESET_ENABLE0_MASK        (0x1U)
#define DMA_COMMON_ENABLESET_ENABLE0_SHIFT       (0U)
/*! ENABLE0 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE0(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
#define DMA_COMMON_ENABLESET_ENABLE1_MASK        (0x2U)
#define DMA_COMMON_ENABLESET_ENABLE1_SHIFT       (1U)
/*! ENABLE1 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE1(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE1_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE1_MASK)
#define DMA_COMMON_ENABLESET_ENABLE2_MASK        (0x4U)
#define DMA_COMMON_ENABLESET_ENABLE2_SHIFT       (2U)
/*! ENABLE2 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE2(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE2_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE2_MASK)
#define DMA_COMMON_ENABLESET_ENABLE3_MASK        (0x8U)
#define DMA_COMMON_ENABLESET_ENABLE3_SHIFT       (3U)
/*! ENABLE3 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE3(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE3_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE3_MASK)
#define DMA_COMMON_ENABLESET_ENABLE4_MASK        (0x10U)
#define DMA_COMMON_ENABLESET_ENABLE4_SHIFT       (4U)
/*! ENABLE4 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE4(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE4_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE4_MASK)
#define DMA_COMMON_ENABLESET_ENABLE5_MASK        (0x20U)
#define DMA_COMMON_ENABLESET_ENABLE5_SHIFT       (5U)
/*! ENABLE5 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE5(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE5_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE5_MASK)
#define DMA_COMMON_ENABLESET_ENABLE6_MASK        (0x40U)
#define DMA_COMMON_ENABLESET_ENABLE6_SHIFT       (6U)
/*! ENABLE6 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE6(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE6_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE6_MASK)
#define DMA_COMMON_ENABLESET_ENABLE7_MASK        (0x80U)
#define DMA_COMMON_ENABLESET_ENABLE7_SHIFT       (7U)
/*! ENABLE7 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE7(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE7_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE7_MASK)
#define DMA_COMMON_ENABLESET_ENABLE8_MASK        (0x100U)
#define DMA_COMMON_ENABLESET_ENABLE8_SHIFT       (8U)
/*! ENABLE8 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE8(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE8_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE8_MASK)
#define DMA_COMMON_ENABLESET_ENABLE9_MASK        (0x200U)
#define DMA_COMMON_ENABLESET_ENABLE9_SHIFT       (9U)
/*! ENABLE9 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE9(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE9_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE9_MASK)
#define DMA_COMMON_ENABLESET_ENABLE10_MASK       (0x400U)
#define DMA_COMMON_ENABLESET_ENABLE10_SHIFT      (10U)
/*! ENABLE10 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE10(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE10_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE10_MASK)
#define DMA_COMMON_ENABLESET_ENABLE11_MASK       (0x800U)
#define DMA_COMMON_ENABLESET_ENABLE11_SHIFT      (11U)
/*! ENABLE11 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE11(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE11_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE11_MASK)
#define DMA_COMMON_ENABLESET_ENABLE12_MASK       (0x1000U)
#define DMA_COMMON_ENABLESET_ENABLE12_SHIFT      (12U)
/*! ENABLE12 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE12(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE12_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE12_MASK)
#define DMA_COMMON_ENABLESET_ENABLE13_MASK       (0x2000U)
#define DMA_COMMON_ENABLESET_ENABLE13_SHIFT      (13U)
/*! ENABLE13 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE13(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE13_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE13_MASK)
#define DMA_COMMON_ENABLESET_ENABLE14_MASK       (0x4000U)
#define DMA_COMMON_ENABLESET_ENABLE14_SHIFT      (14U)
/*! ENABLE14 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE14(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE14_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE14_MASK)
#define DMA_COMMON_ENABLESET_ENABLE15_MASK       (0x8000U)
#define DMA_COMMON_ENABLESET_ENABLE15_SHIFT      (15U)
/*! ENABLE15 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE15(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE15_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE15_MASK)
#define DMA_COMMON_ENABLESET_ENABLE16_MASK       (0x10000U)
#define DMA_COMMON_ENABLESET_ENABLE16_SHIFT      (16U)
/*! ENABLE16 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE16(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE16_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE16_MASK)
#define DMA_COMMON_ENABLESET_ENABLE17_MASK       (0x20000U)
#define DMA_COMMON_ENABLESET_ENABLE17_SHIFT      (17U)
/*! ENABLE17 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE17(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE17_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE17_MASK)
#define DMA_COMMON_ENABLESET_ENABLE18_MASK       (0x40000U)
#define DMA_COMMON_ENABLESET_ENABLE18_SHIFT      (18U)
/*! ENABLE18 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE18(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE18_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE18_MASK)
#define DMA_COMMON_ENABLESET_ENABLE19_MASK       (0x80000U)
#define DMA_COMMON_ENABLESET_ENABLE19_SHIFT      (19U)
/*! ENABLE19 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE19(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE19_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE19_MASK)
#define DMA_COMMON_ENABLESET_ENABLE20_MASK       (0x100000U)
#define DMA_COMMON_ENABLESET_ENABLE20_SHIFT      (20U)
/*! ENABLE20 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE20(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE20_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE20_MASK)
#define DMA_COMMON_ENABLESET_ENABLE21_MASK       (0x200000U)
#define DMA_COMMON_ENABLESET_ENABLE21_SHIFT      (21U)
/*! ENABLE21 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE21(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE21_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE21_MASK)
#define DMA_COMMON_ENABLESET_ENABLE22_MASK       (0x400000U)
#define DMA_COMMON_ENABLESET_ENABLE22_SHIFT      (22U)
/*! ENABLE22 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE22(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE22_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE22_MASK)
#define DMA_COMMON_ENABLESET_ENABLE23_MASK       (0x800000U)
#define DMA_COMMON_ENABLESET_ENABLE23_SHIFT      (23U)
/*! ENABLE23 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE23(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE23_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE23_MASK)
#define DMA_COMMON_ENABLESET_ENABLE24_MASK       (0x1000000U)
#define DMA_COMMON_ENABLESET_ENABLE24_SHIFT      (24U)
/*! ENABLE24 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE24(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE24_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE24_MASK)
#define DMA_COMMON_ENABLESET_ENABLE25_MASK       (0x2000000U)
#define DMA_COMMON_ENABLESET_ENABLE25_SHIFT      (25U)
/*! ENABLE25 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE25(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE25_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE25_MASK)
#define DMA_COMMON_ENABLESET_ENABLE26_MASK       (0x4000000U)
#define DMA_COMMON_ENABLESET_ENABLE26_SHIFT      (26U)
/*! ENABLE26 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE26(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE26_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE26_MASK)
#define DMA_COMMON_ENABLESET_ENABLE27_MASK       (0x8000000U)
#define DMA_COMMON_ENABLESET_ENABLE27_SHIFT      (27U)
/*! ENABLE27 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE27(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE27_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE27_MASK)
#define DMA_COMMON_ENABLESET_ENABLE28_MASK       (0x10000000U)
#define DMA_COMMON_ENABLESET_ENABLE28_SHIFT      (28U)
/*! ENABLE28 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE28(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE28_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE28_MASK)
#define DMA_COMMON_ENABLESET_ENABLE29_MASK       (0x20000000U)
#define DMA_COMMON_ENABLESET_ENABLE29_SHIFT      (29U)
/*! ENABLE29 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE29(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE29_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE29_MASK)
#define DMA_COMMON_ENABLESET_ENABLE30_MASK       (0x40000000U)
#define DMA_COMMON_ENABLESET_ENABLE30_SHIFT      (30U)
/*! ENABLE30 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE30(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE30_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE30_MASK)
#define DMA_COMMON_ENABLESET_ENABLE31_MASK       (0x80000000U)
#define DMA_COMMON_ENABLESET_ENABLE31_SHIFT      (31U)
/*! ENABLE31 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET_ENABLE31(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE31_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE31_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLESET */
#define DMA_COMMON_ENABLESET_COUNT               (1U)

/*! @name COMMON_ENABLESET1 - Channel Enable read and set for all DMA channels */
/*! @{ */
#define DMA_COMMON_ENABLESET1_ENABLE32_MASK      (0x1U)
#define DMA_COMMON_ENABLESET1_ENABLE32_SHIFT     (0U)
/*! ENABLE32 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE32(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE32_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE32_MASK)
#define DMA_COMMON_ENABLESET1_ENABLE33_MASK      (0x2U)
#define DMA_COMMON_ENABLESET1_ENABLE33_SHIFT     (1U)
/*! ENABLE33 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE33(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE33_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE33_MASK)
#define DMA_COMMON_ENABLESET1_ENABLE34_MASK      (0x4U)
#define DMA_COMMON_ENABLESET1_ENABLE34_SHIFT     (2U)
/*! ENABLE34 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE34(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE34_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE34_MASK)
#define DMA_COMMON_ENABLESET1_ENABLE35_MASK      (0x8U)
#define DMA_COMMON_ENABLESET1_ENABLE35_SHIFT     (3U)
/*! ENABLE35 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE35(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE35_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE35_MASK)
#define DMA_COMMON_ENABLESET1_ENABLE36_MASK      (0x10U)
#define DMA_COMMON_ENABLESET1_ENABLE36_SHIFT     (4U)
/*! ENABLE36 - Enable for DMA channel
 *  0b0..DMA channel is disabled.
 *  0b1..DMA channel is enabled.
 */
#define DMA_COMMON_ENABLESET1_ENABLE36(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET1_ENABLE36_SHIFT)) & DMA_COMMON_ENABLESET1_ENABLE36_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLESET1 */
#define DMA_COMMON_ENABLESET1_COUNT              (1U)

/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels */
/*! @{ */
#define DMA_COMMON_ENABLECLR_CLR0_MASK           (0x1U)
#define DMA_COMMON_ENABLECLR_CLR0_SHIFT          (0U)
/*! CLR0 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR0(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
#define DMA_COMMON_ENABLECLR_CLR1_MASK           (0x2U)
#define DMA_COMMON_ENABLECLR_CLR1_SHIFT          (1U)
/*! CLR1 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR1(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR1_SHIFT)) & DMA_COMMON_ENABLECLR_CLR1_MASK)
#define DMA_COMMON_ENABLECLR_CLR2_MASK           (0x4U)
#define DMA_COMMON_ENABLECLR_CLR2_SHIFT          (2U)
/*! CLR2 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR2(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR2_SHIFT)) & DMA_COMMON_ENABLECLR_CLR2_MASK)
#define DMA_COMMON_ENABLECLR_CLR3_MASK           (0x8U)
#define DMA_COMMON_ENABLECLR_CLR3_SHIFT          (3U)
/*! CLR3 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR3(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR3_SHIFT)) & DMA_COMMON_ENABLECLR_CLR3_MASK)
#define DMA_COMMON_ENABLECLR_CLR4_MASK           (0x10U)
#define DMA_COMMON_ENABLECLR_CLR4_SHIFT          (4U)
/*! CLR4 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR4(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR4_SHIFT)) & DMA_COMMON_ENABLECLR_CLR4_MASK)
#define DMA_COMMON_ENABLECLR_CLR5_MASK           (0x20U)
#define DMA_COMMON_ENABLECLR_CLR5_SHIFT          (5U)
/*! CLR5 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR5(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR5_SHIFT)) & DMA_COMMON_ENABLECLR_CLR5_MASK)
#define DMA_COMMON_ENABLECLR_CLR6_MASK           (0x40U)
#define DMA_COMMON_ENABLECLR_CLR6_SHIFT          (6U)
/*! CLR6 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR6(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR6_SHIFT)) & DMA_COMMON_ENABLECLR_CLR6_MASK)
#define DMA_COMMON_ENABLECLR_CLR7_MASK           (0x80U)
#define DMA_COMMON_ENABLECLR_CLR7_SHIFT          (7U)
/*! CLR7 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR7(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR7_SHIFT)) & DMA_COMMON_ENABLECLR_CLR7_MASK)
#define DMA_COMMON_ENABLECLR_CLR8_MASK           (0x100U)
#define DMA_COMMON_ENABLECLR_CLR8_SHIFT          (8U)
/*! CLR8 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR8(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR8_SHIFT)) & DMA_COMMON_ENABLECLR_CLR8_MASK)
#define DMA_COMMON_ENABLECLR_CLR9_MASK           (0x200U)
#define DMA_COMMON_ENABLECLR_CLR9_SHIFT          (9U)
/*! CLR9 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR9(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR9_SHIFT)) & DMA_COMMON_ENABLECLR_CLR9_MASK)
#define DMA_COMMON_ENABLECLR_CLR10_MASK          (0x400U)
#define DMA_COMMON_ENABLECLR_CLR10_SHIFT         (10U)
/*! CLR10 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR10(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR10_SHIFT)) & DMA_COMMON_ENABLECLR_CLR10_MASK)
#define DMA_COMMON_ENABLECLR_CLR11_MASK          (0x800U)
#define DMA_COMMON_ENABLECLR_CLR11_SHIFT         (11U)
/*! CLR11 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR11(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR11_SHIFT)) & DMA_COMMON_ENABLECLR_CLR11_MASK)
#define DMA_COMMON_ENABLECLR_CLR12_MASK          (0x1000U)
#define DMA_COMMON_ENABLECLR_CLR12_SHIFT         (12U)
/*! CLR12 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR12(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR12_SHIFT)) & DMA_COMMON_ENABLECLR_CLR12_MASK)
#define DMA_COMMON_ENABLECLR_CLR13_MASK          (0x2000U)
#define DMA_COMMON_ENABLECLR_CLR13_SHIFT         (13U)
/*! CLR13 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR13(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR13_SHIFT)) & DMA_COMMON_ENABLECLR_CLR13_MASK)
#define DMA_COMMON_ENABLECLR_CLR14_MASK          (0x4000U)
#define DMA_COMMON_ENABLECLR_CLR14_SHIFT         (14U)
/*! CLR14 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR14(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR14_SHIFT)) & DMA_COMMON_ENABLECLR_CLR14_MASK)
#define DMA_COMMON_ENABLECLR_CLR15_MASK          (0x8000U)
#define DMA_COMMON_ENABLECLR_CLR15_SHIFT         (15U)
/*! CLR15 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR15(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR15_SHIFT)) & DMA_COMMON_ENABLECLR_CLR15_MASK)
#define DMA_COMMON_ENABLECLR_CLR16_MASK          (0x10000U)
#define DMA_COMMON_ENABLECLR_CLR16_SHIFT         (16U)
/*! CLR16 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR16(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR16_SHIFT)) & DMA_COMMON_ENABLECLR_CLR16_MASK)
#define DMA_COMMON_ENABLECLR_CLR17_MASK          (0x20000U)
#define DMA_COMMON_ENABLECLR_CLR17_SHIFT         (17U)
/*! CLR17 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR17(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR17_SHIFT)) & DMA_COMMON_ENABLECLR_CLR17_MASK)
#define DMA_COMMON_ENABLECLR_CLR18_MASK          (0x40000U)
#define DMA_COMMON_ENABLECLR_CLR18_SHIFT         (18U)
/*! CLR18 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR18(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR18_SHIFT)) & DMA_COMMON_ENABLECLR_CLR18_MASK)
#define DMA_COMMON_ENABLECLR_CLR19_MASK          (0x80000U)
#define DMA_COMMON_ENABLECLR_CLR19_SHIFT         (19U)
/*! CLR19 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR19(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR19_SHIFT)) & DMA_COMMON_ENABLECLR_CLR19_MASK)
#define DMA_COMMON_ENABLECLR_CLR20_MASK          (0x100000U)
#define DMA_COMMON_ENABLECLR_CLR20_SHIFT         (20U)
/*! CLR20 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR20(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR20_SHIFT)) & DMA_COMMON_ENABLECLR_CLR20_MASK)
#define DMA_COMMON_ENABLECLR_CLR21_MASK          (0x200000U)
#define DMA_COMMON_ENABLECLR_CLR21_SHIFT         (21U)
/*! CLR21 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR21(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR21_SHIFT)) & DMA_COMMON_ENABLECLR_CLR21_MASK)
#define DMA_COMMON_ENABLECLR_CLR22_MASK          (0x400000U)
#define DMA_COMMON_ENABLECLR_CLR22_SHIFT         (22U)
/*! CLR22 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR22(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR22_SHIFT)) & DMA_COMMON_ENABLECLR_CLR22_MASK)
#define DMA_COMMON_ENABLECLR_CLR23_MASK          (0x800000U)
#define DMA_COMMON_ENABLECLR_CLR23_SHIFT         (23U)
/*! CLR23 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR23(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR23_SHIFT)) & DMA_COMMON_ENABLECLR_CLR23_MASK)
#define DMA_COMMON_ENABLECLR_CLR24_MASK          (0x1000000U)
#define DMA_COMMON_ENABLECLR_CLR24_SHIFT         (24U)
/*! CLR24 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR24(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR24_SHIFT)) & DMA_COMMON_ENABLECLR_CLR24_MASK)
#define DMA_COMMON_ENABLECLR_CLR25_MASK          (0x2000000U)
#define DMA_COMMON_ENABLECLR_CLR25_SHIFT         (25U)
/*! CLR25 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR25(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR25_SHIFT)) & DMA_COMMON_ENABLECLR_CLR25_MASK)
#define DMA_COMMON_ENABLECLR_CLR26_MASK          (0x4000000U)
#define DMA_COMMON_ENABLECLR_CLR26_SHIFT         (26U)
/*! CLR26 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR26(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR26_SHIFT)) & DMA_COMMON_ENABLECLR_CLR26_MASK)
#define DMA_COMMON_ENABLECLR_CLR27_MASK          (0x8000000U)
#define DMA_COMMON_ENABLECLR_CLR27_SHIFT         (27U)
/*! CLR27 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR27(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR27_SHIFT)) & DMA_COMMON_ENABLECLR_CLR27_MASK)
#define DMA_COMMON_ENABLECLR_CLR28_MASK          (0x10000000U)
#define DMA_COMMON_ENABLECLR_CLR28_SHIFT         (28U)
/*! CLR28 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR28(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR28_SHIFT)) & DMA_COMMON_ENABLECLR_CLR28_MASK)
#define DMA_COMMON_ENABLECLR_CLR29_MASK          (0x20000000U)
#define DMA_COMMON_ENABLECLR_CLR29_SHIFT         (29U)
/*! CLR29 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR29(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR29_SHIFT)) & DMA_COMMON_ENABLECLR_CLR29_MASK)
#define DMA_COMMON_ENABLECLR_CLR30_MASK          (0x40000000U)
#define DMA_COMMON_ENABLECLR_CLR30_SHIFT         (30U)
/*! CLR30 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR30(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR30_SHIFT)) & DMA_COMMON_ENABLECLR_CLR30_MASK)
#define DMA_COMMON_ENABLECLR_CLR31_MASK          (0x80000000U)
#define DMA_COMMON_ENABLECLR_CLR31_SHIFT         (31U)
/*! CLR31 - Writing ones to this register clears the corresponding bits in ENABLESET0.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR_CLR31(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR31_SHIFT)) & DMA_COMMON_ENABLECLR_CLR31_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLECLR */
#define DMA_COMMON_ENABLECLR_COUNT               (1U)

/*! @name COMMON_ENABLECLR1 - Channel Enable Clear for all DMA channels */
/*! @{ */
#define DMA_COMMON_ENABLECLR1_CLR32_MASK         (0x1U)
#define DMA_COMMON_ENABLECLR1_CLR32_SHIFT        (0U)
/*! CLR32 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR32(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
#define DMA_COMMON_ENABLECLR1_CLR33_MASK         (0x2U)
#define DMA_COMMON_ENABLECLR1_CLR33_SHIFT        (1U)
/*! CLR33 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR33(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR33_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR33_MASK)
#define DMA_COMMON_ENABLECLR1_CLR34_MASK         (0x4U)
#define DMA_COMMON_ENABLECLR1_CLR34_SHIFT        (2U)
/*! CLR34 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR34(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR34_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR34_MASK)
#define DMA_COMMON_ENABLECLR1_CLR35_MASK         (0x8U)
#define DMA_COMMON_ENABLECLR1_CLR35_SHIFT        (3U)
/*! CLR35 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR35(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR35_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR35_MASK)
#define DMA_COMMON_ENABLECLR1_CLR36_MASK         (0x10U)
#define DMA_COMMON_ENABLECLR1_CLR36_SHIFT        (4U)
/*! CLR36 - Writing ones to this register clears the corresponding bits in ENABLESET1.
 *  0b0..No effect.
 *  0b1..DMA channel is cleared.
 */
#define DMA_COMMON_ENABLECLR1_CLR36(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR36_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR36_MASK)
/*! @} */

/* The count of DMA_COMMON_ENABLECLR1 */
#define DMA_COMMON_ENABLECLR1_COUNT              (1U)

/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels */
/*! @{ */
#define DMA_COMMON_ACTIVE_ACTIVE0_MASK           (0x1U)
#define DMA_COMMON_ACTIVE_ACTIVE0_SHIFT          (0U)
/*! ACTIVE0 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE0(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE0_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE0_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE1_MASK           (0x2U)
#define DMA_COMMON_ACTIVE_ACTIVE1_SHIFT          (1U)
/*! ACTIVE1 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE1(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE1_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE1_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE2_MASK           (0x4U)
#define DMA_COMMON_ACTIVE_ACTIVE2_SHIFT          (2U)
/*! ACTIVE2 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE2(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE2_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE2_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE3_MASK           (0x8U)
#define DMA_COMMON_ACTIVE_ACTIVE3_SHIFT          (3U)
/*! ACTIVE3 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE3(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE3_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE3_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE4_MASK           (0x10U)
#define DMA_COMMON_ACTIVE_ACTIVE4_SHIFT          (4U)
/*! ACTIVE4 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE4(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE4_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE4_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE5_MASK           (0x20U)
#define DMA_COMMON_ACTIVE_ACTIVE5_SHIFT          (5U)
/*! ACTIVE5 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE5(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE5_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE5_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE6_MASK           (0x40U)
#define DMA_COMMON_ACTIVE_ACTIVE6_SHIFT          (6U)
/*! ACTIVE6 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE6(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE6_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE6_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE7_MASK           (0x80U)
#define DMA_COMMON_ACTIVE_ACTIVE7_SHIFT          (7U)
/*! ACTIVE7 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE7(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE7_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE7_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE8_MASK           (0x100U)
#define DMA_COMMON_ACTIVE_ACTIVE8_SHIFT          (8U)
/*! ACTIVE8 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE8(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE8_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE8_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE9_MASK           (0x200U)
#define DMA_COMMON_ACTIVE_ACTIVE9_SHIFT          (9U)
/*! ACTIVE9 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE9(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE9_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE9_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE10_MASK          (0x400U)
#define DMA_COMMON_ACTIVE_ACTIVE10_SHIFT         (10U)
/*! ACTIVE10 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE10(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE10_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE10_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE11_MASK          (0x800U)
#define DMA_COMMON_ACTIVE_ACTIVE11_SHIFT         (11U)
/*! ACTIVE11 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE11(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE11_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE11_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE12_MASK          (0x1000U)
#define DMA_COMMON_ACTIVE_ACTIVE12_SHIFT         (12U)
/*! ACTIVE12 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE12(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE12_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE12_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE13_MASK          (0x2000U)
#define DMA_COMMON_ACTIVE_ACTIVE13_SHIFT         (13U)
/*! ACTIVE13 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE13(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE13_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE13_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE14_MASK          (0x4000U)
#define DMA_COMMON_ACTIVE_ACTIVE14_SHIFT         (14U)
/*! ACTIVE14 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE14(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE14_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE14_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE15_MASK          (0x8000U)
#define DMA_COMMON_ACTIVE_ACTIVE15_SHIFT         (15U)
/*! ACTIVE15 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE15(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE15_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE15_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE16_MASK          (0x10000U)
#define DMA_COMMON_ACTIVE_ACTIVE16_SHIFT         (16U)
/*! ACTIVE16 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE16(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE16_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE16_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE17_MASK          (0x20000U)
#define DMA_COMMON_ACTIVE_ACTIVE17_SHIFT         (17U)
/*! ACTIVE17 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE17(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE17_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE17_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE18_MASK          (0x40000U)
#define DMA_COMMON_ACTIVE_ACTIVE18_SHIFT         (18U)
/*! ACTIVE18 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE18(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE18_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE18_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE19_MASK          (0x80000U)
#define DMA_COMMON_ACTIVE_ACTIVE19_SHIFT         (19U)
/*! ACTIVE19 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE19(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE19_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE19_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE20_MASK          (0x100000U)
#define DMA_COMMON_ACTIVE_ACTIVE20_SHIFT         (20U)
/*! ACTIVE20 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE20(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE20_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE20_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE21_MASK          (0x200000U)
#define DMA_COMMON_ACTIVE_ACTIVE21_SHIFT         (21U)
/*! ACTIVE21 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE21(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE21_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE21_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE22_MASK          (0x400000U)
#define DMA_COMMON_ACTIVE_ACTIVE22_SHIFT         (22U)
/*! ACTIVE22 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE22(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE22_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE22_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE23_MASK          (0x800000U)
#define DMA_COMMON_ACTIVE_ACTIVE23_SHIFT         (23U)
/*! ACTIVE23 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE23(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE23_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE23_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE24_MASK          (0x1000000U)
#define DMA_COMMON_ACTIVE_ACTIVE24_SHIFT         (24U)
/*! ACTIVE24 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE24(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE24_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE24_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE25_MASK          (0x2000000U)
#define DMA_COMMON_ACTIVE_ACTIVE25_SHIFT         (25U)
/*! ACTIVE25 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE25(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE25_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE25_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE26_MASK          (0x4000000U)
#define DMA_COMMON_ACTIVE_ACTIVE26_SHIFT         (26U)
/*! ACTIVE26 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE26(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE26_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE26_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE27_MASK          (0x8000000U)
#define DMA_COMMON_ACTIVE_ACTIVE27_SHIFT         (27U)
/*! ACTIVE27 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE27(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE27_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE27_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE28_MASK          (0x10000000U)
#define DMA_COMMON_ACTIVE_ACTIVE28_SHIFT         (28U)
/*! ACTIVE28 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE28(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE28_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE28_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE29_MASK          (0x20000000U)
#define DMA_COMMON_ACTIVE_ACTIVE29_SHIFT         (29U)
/*! ACTIVE29 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE29(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE29_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE29_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE30_MASK          (0x40000000U)
#define DMA_COMMON_ACTIVE_ACTIVE30_SHIFT         (30U)
/*! ACTIVE30 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE30(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE30_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE30_MASK)
#define DMA_COMMON_ACTIVE_ACTIVE31_MASK          (0x80000000U)
#define DMA_COMMON_ACTIVE_ACTIVE31_SHIFT         (31U)
/*! ACTIVE31 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE_ACTIVE31(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACTIVE31_SHIFT)) & DMA_COMMON_ACTIVE_ACTIVE31_MASK)
/*! @} */

/* The count of DMA_COMMON_ACTIVE */
#define DMA_COMMON_ACTIVE_COUNT                  (1U)

/*! @name COMMON_ACTIVE1 - Channel Active status for all DMA channels */
/*! @{ */
#define DMA_COMMON_ACTIVE1_ACTIVE32_MASK         (0x1U)
#define DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT        (0U)
/*! ACTIVE32 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE32(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE32_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE32_MASK)
#define DMA_COMMON_ACTIVE1_ACTIVE33_MASK         (0x2U)
#define DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT        (1U)
/*! ACTIVE33 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE33(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE33_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE33_MASK)
#define DMA_COMMON_ACTIVE1_ACTIVE34_MASK         (0x4U)
#define DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT        (2U)
/*! ACTIVE34 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE34(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE34_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE34_MASK)
#define DMA_COMMON_ACTIVE1_ACTIVE35_MASK         (0x8U)
#define DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT        (3U)
/*! ACTIVE35 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE35(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE35_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE35_MASK)
#define DMA_COMMON_ACTIVE1_ACTIVE36_MASK         (0x10U)
#define DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT        (4U)
/*! ACTIVE36 - Active flag for DMA channel.
 *  0b0..DMA channel is not active.
 *  0b1..DMA channel is active.
 */
#define DMA_COMMON_ACTIVE1_ACTIVE36(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE1_ACTIVE36_SHIFT)) & DMA_COMMON_ACTIVE1_ACTIVE36_MASK)
/*! @} */

/* The count of DMA_COMMON_ACTIVE1 */
#define DMA_COMMON_ACTIVE1_COUNT                 (1U)

/*! @name COMMON_BUSY - Channel Busy status for all DMA channels */
/*! @{ */
#define DMA_COMMON_BUSY_BUSY0_MASK               (0x1U)
#define DMA_COMMON_BUSY_BUSY0_SHIFT              (0U)
/*! BUSY0 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY0_SHIFT)) & DMA_COMMON_BUSY_BUSY0_MASK)
#define DMA_COMMON_BUSY_BUSY1_MASK               (0x2U)
#define DMA_COMMON_BUSY_BUSY1_SHIFT              (1U)
/*! BUSY1 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY1_SHIFT)) & DMA_COMMON_BUSY_BUSY1_MASK)
#define DMA_COMMON_BUSY_BUSY2_MASK               (0x4U)
#define DMA_COMMON_BUSY_BUSY2_SHIFT              (2U)
/*! BUSY2 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY2_SHIFT)) & DMA_COMMON_BUSY_BUSY2_MASK)
#define DMA_COMMON_BUSY_BUSY3_MASK               (0x8U)
#define DMA_COMMON_BUSY_BUSY3_SHIFT              (3U)
/*! BUSY3 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY3_SHIFT)) & DMA_COMMON_BUSY_BUSY3_MASK)
#define DMA_COMMON_BUSY_BUSY4_MASK               (0x10U)
#define DMA_COMMON_BUSY_BUSY4_SHIFT              (4U)
/*! BUSY4 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY4_SHIFT)) & DMA_COMMON_BUSY_BUSY4_MASK)
#define DMA_COMMON_BUSY_BUSY5_MASK               (0x20U)
#define DMA_COMMON_BUSY_BUSY5_SHIFT              (5U)
/*! BUSY5 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY5_SHIFT)) & DMA_COMMON_BUSY_BUSY5_MASK)
#define DMA_COMMON_BUSY_BUSY6_MASK               (0x40U)
#define DMA_COMMON_BUSY_BUSY6_SHIFT              (6U)
/*! BUSY6 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY6_SHIFT)) & DMA_COMMON_BUSY_BUSY6_MASK)
#define DMA_COMMON_BUSY_BUSY7_MASK               (0x80U)
#define DMA_COMMON_BUSY_BUSY7_SHIFT              (7U)
/*! BUSY7 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY7_SHIFT)) & DMA_COMMON_BUSY_BUSY7_MASK)
#define DMA_COMMON_BUSY_BUSY8_MASK               (0x100U)
#define DMA_COMMON_BUSY_BUSY8_SHIFT              (8U)
/*! BUSY8 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY8_SHIFT)) & DMA_COMMON_BUSY_BUSY8_MASK)
#define DMA_COMMON_BUSY_BUSY9_MASK               (0x200U)
#define DMA_COMMON_BUSY_BUSY9_SHIFT              (9U)
/*! BUSY9 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY9_SHIFT)) & DMA_COMMON_BUSY_BUSY9_MASK)
#define DMA_COMMON_BUSY_BUSY10_MASK              (0x400U)
#define DMA_COMMON_BUSY_BUSY10_SHIFT             (10U)
/*! BUSY10 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY10_SHIFT)) & DMA_COMMON_BUSY_BUSY10_MASK)
#define DMA_COMMON_BUSY_BUSY11_MASK              (0x800U)
#define DMA_COMMON_BUSY_BUSY11_SHIFT             (11U)
/*! BUSY11 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY11_SHIFT)) & DMA_COMMON_BUSY_BUSY11_MASK)
#define DMA_COMMON_BUSY_BUSY12_MASK              (0x1000U)
#define DMA_COMMON_BUSY_BUSY12_SHIFT             (12U)
/*! BUSY12 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY12_SHIFT)) & DMA_COMMON_BUSY_BUSY12_MASK)
#define DMA_COMMON_BUSY_BUSY13_MASK              (0x2000U)
#define DMA_COMMON_BUSY_BUSY13_SHIFT             (13U)
/*! BUSY13 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY13_SHIFT)) & DMA_COMMON_BUSY_BUSY13_MASK)
#define DMA_COMMON_BUSY_BUSY14_MASK              (0x4000U)
#define DMA_COMMON_BUSY_BUSY14_SHIFT             (14U)
/*! BUSY14 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY14_SHIFT)) & DMA_COMMON_BUSY_BUSY14_MASK)
#define DMA_COMMON_BUSY_BUSY15_MASK              (0x8000U)
#define DMA_COMMON_BUSY_BUSY15_SHIFT             (15U)
/*! BUSY15 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY15_SHIFT)) & DMA_COMMON_BUSY_BUSY15_MASK)
#define DMA_COMMON_BUSY_BUSY16_MASK              (0x10000U)
#define DMA_COMMON_BUSY_BUSY16_SHIFT             (16U)
/*! BUSY16 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY16_SHIFT)) & DMA_COMMON_BUSY_BUSY16_MASK)
#define DMA_COMMON_BUSY_BUSY17_MASK              (0x20000U)
#define DMA_COMMON_BUSY_BUSY17_SHIFT             (17U)
/*! BUSY17 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY17_SHIFT)) & DMA_COMMON_BUSY_BUSY17_MASK)
#define DMA_COMMON_BUSY_BUSY18_MASK              (0x40000U)
#define DMA_COMMON_BUSY_BUSY18_SHIFT             (18U)
/*! BUSY18 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY18_SHIFT)) & DMA_COMMON_BUSY_BUSY18_MASK)
#define DMA_COMMON_BUSY_BUSY19_MASK              (0x80000U)
#define DMA_COMMON_BUSY_BUSY19_SHIFT             (19U)
/*! BUSY19 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY19_SHIFT)) & DMA_COMMON_BUSY_BUSY19_MASK)
#define DMA_COMMON_BUSY_BUSY20_MASK              (0x100000U)
#define DMA_COMMON_BUSY_BUSY20_SHIFT             (20U)
/*! BUSY20 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY20_SHIFT)) & DMA_COMMON_BUSY_BUSY20_MASK)
#define DMA_COMMON_BUSY_BUSY21_MASK              (0x200000U)
#define DMA_COMMON_BUSY_BUSY21_SHIFT             (21U)
/*! BUSY21 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY21_SHIFT)) & DMA_COMMON_BUSY_BUSY21_MASK)
#define DMA_COMMON_BUSY_BUSY22_MASK              (0x400000U)
#define DMA_COMMON_BUSY_BUSY22_SHIFT             (22U)
/*! BUSY22 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY22_SHIFT)) & DMA_COMMON_BUSY_BUSY22_MASK)
#define DMA_COMMON_BUSY_BUSY23_MASK              (0x800000U)
#define DMA_COMMON_BUSY_BUSY23_SHIFT             (23U)
/*! BUSY23 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY23_SHIFT)) & DMA_COMMON_BUSY_BUSY23_MASK)
#define DMA_COMMON_BUSY_BUSY24_MASK              (0x1000000U)
#define DMA_COMMON_BUSY_BUSY24_SHIFT             (24U)
/*! BUSY24 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY24_SHIFT)) & DMA_COMMON_BUSY_BUSY24_MASK)
#define DMA_COMMON_BUSY_BUSY25_MASK              (0x2000000U)
#define DMA_COMMON_BUSY_BUSY25_SHIFT             (25U)
/*! BUSY25 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY25_SHIFT)) & DMA_COMMON_BUSY_BUSY25_MASK)
#define DMA_COMMON_BUSY_BUSY26_MASK              (0x4000000U)
#define DMA_COMMON_BUSY_BUSY26_SHIFT             (26U)
/*! BUSY26 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY26_SHIFT)) & DMA_COMMON_BUSY_BUSY26_MASK)
#define DMA_COMMON_BUSY_BUSY27_MASK              (0x8000000U)
#define DMA_COMMON_BUSY_BUSY27_SHIFT             (27U)
/*! BUSY27 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY27_SHIFT)) & DMA_COMMON_BUSY_BUSY27_MASK)
#define DMA_COMMON_BUSY_BUSY28_MASK              (0x10000000U)
#define DMA_COMMON_BUSY_BUSY28_SHIFT             (28U)
/*! BUSY28 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY28_SHIFT)) & DMA_COMMON_BUSY_BUSY28_MASK)
#define DMA_COMMON_BUSY_BUSY29_MASK              (0x20000000U)
#define DMA_COMMON_BUSY_BUSY29_SHIFT             (29U)
/*! BUSY29 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY29_SHIFT)) & DMA_COMMON_BUSY_BUSY29_MASK)
#define DMA_COMMON_BUSY_BUSY30_MASK              (0x40000000U)
#define DMA_COMMON_BUSY_BUSY30_SHIFT             (30U)
/*! BUSY30 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY30_SHIFT)) & DMA_COMMON_BUSY_BUSY30_MASK)
#define DMA_COMMON_BUSY_BUSY31_MASK              (0x80000000U)
#define DMA_COMMON_BUSY_BUSY31_SHIFT             (31U)
/*! BUSY31 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY_BUSY31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BUSY31_SHIFT)) & DMA_COMMON_BUSY_BUSY31_MASK)
/*! @} */

/* The count of DMA_COMMON_BUSY */
#define DMA_COMMON_BUSY_COUNT                    (1U)

/*! @name COMMON_BUSY1 - Channel Busy status for all DMA channels */
/*! @{ */
#define DMA_COMMON_BUSY1_BUSY32_MASK             (0x1U)
#define DMA_COMMON_BUSY1_BUSY32_SHIFT            (0U)
/*! BUSY32 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY32(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY32_SHIFT)) & DMA_COMMON_BUSY1_BUSY32_MASK)
#define DMA_COMMON_BUSY1_BUSY33_MASK             (0x2U)
#define DMA_COMMON_BUSY1_BUSY33_SHIFT            (1U)
/*! BUSY33 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY33(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY33_SHIFT)) & DMA_COMMON_BUSY1_BUSY33_MASK)
#define DMA_COMMON_BUSY1_BUSY34_MASK             (0x4U)
#define DMA_COMMON_BUSY1_BUSY34_SHIFT            (2U)
/*! BUSY34 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY34(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY34_SHIFT)) & DMA_COMMON_BUSY1_BUSY34_MASK)
#define DMA_COMMON_BUSY1_BUSY35_MASK             (0x8U)
#define DMA_COMMON_BUSY1_BUSY35_SHIFT            (3U)
/*! BUSY35 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY35(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY35_SHIFT)) & DMA_COMMON_BUSY1_BUSY35_MASK)
#define DMA_COMMON_BUSY1_BUSY36_MASK             (0x10U)
#define DMA_COMMON_BUSY1_BUSY36_SHIFT            (4U)
/*! BUSY36 - Busy flag for DMA channel.
 *  0b0..DMA channel is not busy.
 *  0b1..DMA channel is busy.
 */
#define DMA_COMMON_BUSY1_BUSY36(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY1_BUSY36_SHIFT)) & DMA_COMMON_BUSY1_BUSY36_MASK)
/*! @} */

/* The count of DMA_COMMON_BUSY1 */
#define DMA_COMMON_BUSY1_COUNT                   (1U)

/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels */
/*! @{ */
#define DMA_COMMON_ERRINT_ERR0_MASK              (0x1U)
#define DMA_COMMON_ERRINT_ERR0_SHIFT             (0U)
/*! ERR0 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR0(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR0_SHIFT)) & DMA_COMMON_ERRINT_ERR0_MASK)
#define DMA_COMMON_ERRINT_ERR1_MASK              (0x2U)
#define DMA_COMMON_ERRINT_ERR1_SHIFT             (1U)
/*! ERR1 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR1(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR1_SHIFT)) & DMA_COMMON_ERRINT_ERR1_MASK)
#define DMA_COMMON_ERRINT_ERR2_MASK              (0x4U)
#define DMA_COMMON_ERRINT_ERR2_SHIFT             (2U)
/*! ERR2 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR2(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR2_SHIFT)) & DMA_COMMON_ERRINT_ERR2_MASK)
#define DMA_COMMON_ERRINT_ERR3_MASK              (0x8U)
#define DMA_COMMON_ERRINT_ERR3_SHIFT             (3U)
/*! ERR3 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR3(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR3_SHIFT)) & DMA_COMMON_ERRINT_ERR3_MASK)
#define DMA_COMMON_ERRINT_ERR4_MASK              (0x10U)
#define DMA_COMMON_ERRINT_ERR4_SHIFT             (4U)
/*! ERR4 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR4(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR4_SHIFT)) & DMA_COMMON_ERRINT_ERR4_MASK)
#define DMA_COMMON_ERRINT_ERR5_MASK              (0x20U)
#define DMA_COMMON_ERRINT_ERR5_SHIFT             (5U)
/*! ERR5 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR5(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR5_SHIFT)) & DMA_COMMON_ERRINT_ERR5_MASK)
#define DMA_COMMON_ERRINT_ERR6_MASK              (0x40U)
#define DMA_COMMON_ERRINT_ERR6_SHIFT             (6U)
/*! ERR6 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR6(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR6_SHIFT)) & DMA_COMMON_ERRINT_ERR6_MASK)
#define DMA_COMMON_ERRINT_ERR7_MASK              (0x80U)
#define DMA_COMMON_ERRINT_ERR7_SHIFT             (7U)
/*! ERR7 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR7(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR7_SHIFT)) & DMA_COMMON_ERRINT_ERR7_MASK)
#define DMA_COMMON_ERRINT_ERR8_MASK              (0x100U)
#define DMA_COMMON_ERRINT_ERR8_SHIFT             (8U)
/*! ERR8 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR8(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR8_SHIFT)) & DMA_COMMON_ERRINT_ERR8_MASK)
#define DMA_COMMON_ERRINT_ERR9_MASK              (0x200U)
#define DMA_COMMON_ERRINT_ERR9_SHIFT             (9U)
/*! ERR9 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR9(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR9_SHIFT)) & DMA_COMMON_ERRINT_ERR9_MASK)
#define DMA_COMMON_ERRINT_ERR10_MASK             (0x400U)
#define DMA_COMMON_ERRINT_ERR10_SHIFT            (10U)
/*! ERR10 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR10(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR10_SHIFT)) & DMA_COMMON_ERRINT_ERR10_MASK)
#define DMA_COMMON_ERRINT_ERR11_MASK             (0x800U)
#define DMA_COMMON_ERRINT_ERR11_SHIFT            (11U)
/*! ERR11 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR11(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR11_SHIFT)) & DMA_COMMON_ERRINT_ERR11_MASK)
#define DMA_COMMON_ERRINT_ERR12_MASK             (0x1000U)
#define DMA_COMMON_ERRINT_ERR12_SHIFT            (12U)
/*! ERR12 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR12(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR12_SHIFT)) & DMA_COMMON_ERRINT_ERR12_MASK)
#define DMA_COMMON_ERRINT_ERR13_MASK             (0x2000U)
#define DMA_COMMON_ERRINT_ERR13_SHIFT            (13U)
/*! ERR13 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR13(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR13_SHIFT)) & DMA_COMMON_ERRINT_ERR13_MASK)
#define DMA_COMMON_ERRINT_ERR14_MASK             (0x4000U)
#define DMA_COMMON_ERRINT_ERR14_SHIFT            (14U)
/*! ERR14 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR14(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR14_SHIFT)) & DMA_COMMON_ERRINT_ERR14_MASK)
#define DMA_COMMON_ERRINT_ERR15_MASK             (0x8000U)
#define DMA_COMMON_ERRINT_ERR15_SHIFT            (15U)
/*! ERR15 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR15(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR15_SHIFT)) & DMA_COMMON_ERRINT_ERR15_MASK)
#define DMA_COMMON_ERRINT_ERR16_MASK             (0x10000U)
#define DMA_COMMON_ERRINT_ERR16_SHIFT            (16U)
/*! ERR16 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR16(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR16_SHIFT)) & DMA_COMMON_ERRINT_ERR16_MASK)
#define DMA_COMMON_ERRINT_ERR17_MASK             (0x20000U)
#define DMA_COMMON_ERRINT_ERR17_SHIFT            (17U)
/*! ERR17 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR17(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR17_SHIFT)) & DMA_COMMON_ERRINT_ERR17_MASK)
#define DMA_COMMON_ERRINT_ERR18_MASK             (0x40000U)
#define DMA_COMMON_ERRINT_ERR18_SHIFT            (18U)
/*! ERR18 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR18(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR18_SHIFT)) & DMA_COMMON_ERRINT_ERR18_MASK)
#define DMA_COMMON_ERRINT_ERR19_MASK             (0x80000U)
#define DMA_COMMON_ERRINT_ERR19_SHIFT            (19U)
/*! ERR19 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR19(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR19_SHIFT)) & DMA_COMMON_ERRINT_ERR19_MASK)
#define DMA_COMMON_ERRINT_ERR20_MASK             (0x100000U)
#define DMA_COMMON_ERRINT_ERR20_SHIFT            (20U)
/*! ERR20 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR20(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR20_SHIFT)) & DMA_COMMON_ERRINT_ERR20_MASK)
#define DMA_COMMON_ERRINT_ERR21_MASK             (0x200000U)
#define DMA_COMMON_ERRINT_ERR21_SHIFT            (21U)
/*! ERR21 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR21(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR21_SHIFT)) & DMA_COMMON_ERRINT_ERR21_MASK)
#define DMA_COMMON_ERRINT_ERR22_MASK             (0x400000U)
#define DMA_COMMON_ERRINT_ERR22_SHIFT            (22U)
/*! ERR22 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR22(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR22_SHIFT)) & DMA_COMMON_ERRINT_ERR22_MASK)
#define DMA_COMMON_ERRINT_ERR23_MASK             (0x800000U)
#define DMA_COMMON_ERRINT_ERR23_SHIFT            (23U)
/*! ERR23 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR23(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR23_SHIFT)) & DMA_COMMON_ERRINT_ERR23_MASK)
#define DMA_COMMON_ERRINT_ERR24_MASK             (0x1000000U)
#define DMA_COMMON_ERRINT_ERR24_SHIFT            (24U)
/*! ERR24 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR24(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR24_SHIFT)) & DMA_COMMON_ERRINT_ERR24_MASK)
#define DMA_COMMON_ERRINT_ERR25_MASK             (0x2000000U)
#define DMA_COMMON_ERRINT_ERR25_SHIFT            (25U)
/*! ERR25 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR25(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR25_SHIFT)) & DMA_COMMON_ERRINT_ERR25_MASK)
#define DMA_COMMON_ERRINT_ERR26_MASK             (0x4000000U)
#define DMA_COMMON_ERRINT_ERR26_SHIFT            (26U)
/*! ERR26 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR26(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR26_SHIFT)) & DMA_COMMON_ERRINT_ERR26_MASK)
#define DMA_COMMON_ERRINT_ERR27_MASK             (0x8000000U)
#define DMA_COMMON_ERRINT_ERR27_SHIFT            (27U)
/*! ERR27 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR27(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR27_SHIFT)) & DMA_COMMON_ERRINT_ERR27_MASK)
#define DMA_COMMON_ERRINT_ERR28_MASK             (0x10000000U)
#define DMA_COMMON_ERRINT_ERR28_SHIFT            (28U)
/*! ERR28 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR28(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR28_SHIFT)) & DMA_COMMON_ERRINT_ERR28_MASK)
#define DMA_COMMON_ERRINT_ERR29_MASK             (0x20000000U)
#define DMA_COMMON_ERRINT_ERR29_SHIFT            (29U)
/*! ERR29 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR29(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR29_SHIFT)) & DMA_COMMON_ERRINT_ERR29_MASK)
#define DMA_COMMON_ERRINT_ERR30_MASK             (0x40000000U)
#define DMA_COMMON_ERRINT_ERR30_SHIFT            (30U)
/*! ERR30 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR30(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR30_SHIFT)) & DMA_COMMON_ERRINT_ERR30_MASK)
#define DMA_COMMON_ERRINT_ERR31_MASK             (0x80000000U)
#define DMA_COMMON_ERRINT_ERR31_SHIFT            (31U)
/*! ERR31 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT_ERR31(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR31_SHIFT)) & DMA_COMMON_ERRINT_ERR31_MASK)
/*! @} */

/* The count of DMA_COMMON_ERRINT */
#define DMA_COMMON_ERRINT_COUNT                  (1U)

/*! @name COMMON_ERRINT1 - Error Interrupt status for all DMA channels */
/*! @{ */
#define DMA_COMMON_ERRINT1_ERR32_MASK            (0x1U)
#define DMA_COMMON_ERRINT1_ERR32_SHIFT           (0U)
/*! ERR32 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR32(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR32_SHIFT)) & DMA_COMMON_ERRINT1_ERR32_MASK)
#define DMA_COMMON_ERRINT1_ERR33_MASK            (0x2U)
#define DMA_COMMON_ERRINT1_ERR33_SHIFT           (1U)
/*! ERR33 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR33(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR33_SHIFT)) & DMA_COMMON_ERRINT1_ERR33_MASK)
#define DMA_COMMON_ERRINT1_ERR34_MASK            (0x4U)
#define DMA_COMMON_ERRINT1_ERR34_SHIFT           (2U)
/*! ERR34 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR34(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR34_SHIFT)) & DMA_COMMON_ERRINT1_ERR34_MASK)
#define DMA_COMMON_ERRINT1_ERR35_MASK            (0x8U)
#define DMA_COMMON_ERRINT1_ERR35_SHIFT           (3U)
/*! ERR35 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR35(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR35_SHIFT)) & DMA_COMMON_ERRINT1_ERR35_MASK)
#define DMA_COMMON_ERRINT1_ERR36_MASK            (0x10U)
#define DMA_COMMON_ERRINT1_ERR36_SHIFT           (4U)
/*! ERR36 - Error Interrupt flag for DMA channel.
 *  0b0..The Error Interrupt is not active for DMA channel.
 *  0b1..The Error Interrupt is pending for DMA channel.
 */
#define DMA_COMMON_ERRINT1_ERR36(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT1_ERR36_SHIFT)) & DMA_COMMON_ERRINT1_ERR36_MASK)
/*! @} */

/* The count of DMA_COMMON_ERRINT1 */
#define DMA_COMMON_ERRINT1_COUNT                 (1U)

/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTENSET_INTEN0_MASK          (0x1U)
#define DMA_COMMON_INTENSET_INTEN0_SHIFT         (0U)
/*! INTEN0 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN0(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN0_SHIFT)) & DMA_COMMON_INTENSET_INTEN0_MASK)
#define DMA_COMMON_INTENSET_INTEN1_MASK          (0x2U)
#define DMA_COMMON_INTENSET_INTEN1_SHIFT         (1U)
/*! INTEN1 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN1(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN1_SHIFT)) & DMA_COMMON_INTENSET_INTEN1_MASK)
#define DMA_COMMON_INTENSET_INTEN2_MASK          (0x4U)
#define DMA_COMMON_INTENSET_INTEN2_SHIFT         (2U)
/*! INTEN2 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN2(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN2_SHIFT)) & DMA_COMMON_INTENSET_INTEN2_MASK)
#define DMA_COMMON_INTENSET_INTEN3_MASK          (0x8U)
#define DMA_COMMON_INTENSET_INTEN3_SHIFT         (3U)
/*! INTEN3 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN3(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN3_SHIFT)) & DMA_COMMON_INTENSET_INTEN3_MASK)
#define DMA_COMMON_INTENSET_INTEN4_MASK          (0x10U)
#define DMA_COMMON_INTENSET_INTEN4_SHIFT         (4U)
/*! INTEN4 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN4(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN4_SHIFT)) & DMA_COMMON_INTENSET_INTEN4_MASK)
#define DMA_COMMON_INTENSET_INTEN5_MASK          (0x20U)
#define DMA_COMMON_INTENSET_INTEN5_SHIFT         (5U)
/*! INTEN5 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN5(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN5_SHIFT)) & DMA_COMMON_INTENSET_INTEN5_MASK)
#define DMA_COMMON_INTENSET_INTEN6_MASK          (0x40U)
#define DMA_COMMON_INTENSET_INTEN6_SHIFT         (6U)
/*! INTEN6 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN6(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN6_SHIFT)) & DMA_COMMON_INTENSET_INTEN6_MASK)
#define DMA_COMMON_INTENSET_INTEN7_MASK          (0x80U)
#define DMA_COMMON_INTENSET_INTEN7_SHIFT         (7U)
/*! INTEN7 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN7(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN7_SHIFT)) & DMA_COMMON_INTENSET_INTEN7_MASK)
#define DMA_COMMON_INTENSET_INTEN8_MASK          (0x100U)
#define DMA_COMMON_INTENSET_INTEN8_SHIFT         (8U)
/*! INTEN8 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN8(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN8_SHIFT)) & DMA_COMMON_INTENSET_INTEN8_MASK)
#define DMA_COMMON_INTENSET_INTEN9_MASK          (0x200U)
#define DMA_COMMON_INTENSET_INTEN9_SHIFT         (9U)
/*! INTEN9 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN9(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN9_SHIFT)) & DMA_COMMON_INTENSET_INTEN9_MASK)
#define DMA_COMMON_INTENSET_INTEN10_MASK         (0x400U)
#define DMA_COMMON_INTENSET_INTEN10_SHIFT        (10U)
/*! INTEN10 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN10(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN10_SHIFT)) & DMA_COMMON_INTENSET_INTEN10_MASK)
#define DMA_COMMON_INTENSET_INTEN11_MASK         (0x800U)
#define DMA_COMMON_INTENSET_INTEN11_SHIFT        (11U)
/*! INTEN11 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN11(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN11_SHIFT)) & DMA_COMMON_INTENSET_INTEN11_MASK)
#define DMA_COMMON_INTENSET_INTEN12_MASK         (0x1000U)
#define DMA_COMMON_INTENSET_INTEN12_SHIFT        (12U)
/*! INTEN12 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN12(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN12_SHIFT)) & DMA_COMMON_INTENSET_INTEN12_MASK)
#define DMA_COMMON_INTENSET_INTEN13_MASK         (0x2000U)
#define DMA_COMMON_INTENSET_INTEN13_SHIFT        (13U)
/*! INTEN13 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN13(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN13_SHIFT)) & DMA_COMMON_INTENSET_INTEN13_MASK)
#define DMA_COMMON_INTENSET_INTEN14_MASK         (0x4000U)
#define DMA_COMMON_INTENSET_INTEN14_SHIFT        (14U)
/*! INTEN14 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN14(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN14_SHIFT)) & DMA_COMMON_INTENSET_INTEN14_MASK)
#define DMA_COMMON_INTENSET_INTEN15_MASK         (0x8000U)
#define DMA_COMMON_INTENSET_INTEN15_SHIFT        (15U)
/*! INTEN15 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN15(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN15_SHIFT)) & DMA_COMMON_INTENSET_INTEN15_MASK)
#define DMA_COMMON_INTENSET_INTEN16_MASK         (0x10000U)
#define DMA_COMMON_INTENSET_INTEN16_SHIFT        (16U)
/*! INTEN16 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN16(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN16_SHIFT)) & DMA_COMMON_INTENSET_INTEN16_MASK)
#define DMA_COMMON_INTENSET_INTEN17_MASK         (0x20000U)
#define DMA_COMMON_INTENSET_INTEN17_SHIFT        (17U)
/*! INTEN17 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN17(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN17_SHIFT)) & DMA_COMMON_INTENSET_INTEN17_MASK)
#define DMA_COMMON_INTENSET_INTEN18_MASK         (0x40000U)
#define DMA_COMMON_INTENSET_INTEN18_SHIFT        (18U)
/*! INTEN18 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN18(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN18_SHIFT)) & DMA_COMMON_INTENSET_INTEN18_MASK)
#define DMA_COMMON_INTENSET_INTEN19_MASK         (0x80000U)
#define DMA_COMMON_INTENSET_INTEN19_SHIFT        (19U)
/*! INTEN19 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN19(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN19_SHIFT)) & DMA_COMMON_INTENSET_INTEN19_MASK)
#define DMA_COMMON_INTENSET_INTEN20_MASK         (0x100000U)
#define DMA_COMMON_INTENSET_INTEN20_SHIFT        (20U)
/*! INTEN20 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN20(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN20_SHIFT)) & DMA_COMMON_INTENSET_INTEN20_MASK)
#define DMA_COMMON_INTENSET_INTEN21_MASK         (0x200000U)
#define DMA_COMMON_INTENSET_INTEN21_SHIFT        (21U)
/*! INTEN21 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN21(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN21_SHIFT)) & DMA_COMMON_INTENSET_INTEN21_MASK)
#define DMA_COMMON_INTENSET_INTEN22_MASK         (0x400000U)
#define DMA_COMMON_INTENSET_INTEN22_SHIFT        (22U)
/*! INTEN22 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN22(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN22_SHIFT)) & DMA_COMMON_INTENSET_INTEN22_MASK)
#define DMA_COMMON_INTENSET_INTEN23_MASK         (0x800000U)
#define DMA_COMMON_INTENSET_INTEN23_SHIFT        (23U)
/*! INTEN23 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN23(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN23_SHIFT)) & DMA_COMMON_INTENSET_INTEN23_MASK)
#define DMA_COMMON_INTENSET_INTEN24_MASK         (0x1000000U)
#define DMA_COMMON_INTENSET_INTEN24_SHIFT        (24U)
/*! INTEN24 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN24(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN24_SHIFT)) & DMA_COMMON_INTENSET_INTEN24_MASK)
#define DMA_COMMON_INTENSET_INTEN25_MASK         (0x2000000U)
#define DMA_COMMON_INTENSET_INTEN25_SHIFT        (25U)
/*! INTEN25 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN25(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN25_SHIFT)) & DMA_COMMON_INTENSET_INTEN25_MASK)
#define DMA_COMMON_INTENSET_INTEN26_MASK         (0x4000000U)
#define DMA_COMMON_INTENSET_INTEN26_SHIFT        (26U)
/*! INTEN26 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN26(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN26_SHIFT)) & DMA_COMMON_INTENSET_INTEN26_MASK)
#define DMA_COMMON_INTENSET_INTEN27_MASK         (0x8000000U)
#define DMA_COMMON_INTENSET_INTEN27_SHIFT        (27U)
/*! INTEN27 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN27(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN27_SHIFT)) & DMA_COMMON_INTENSET_INTEN27_MASK)
#define DMA_COMMON_INTENSET_INTEN28_MASK         (0x10000000U)
#define DMA_COMMON_INTENSET_INTEN28_SHIFT        (28U)
/*! INTEN28 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN28(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN28_SHIFT)) & DMA_COMMON_INTENSET_INTEN28_MASK)
#define DMA_COMMON_INTENSET_INTEN29_MASK         (0x20000000U)
#define DMA_COMMON_INTENSET_INTEN29_SHIFT        (29U)
/*! INTEN29 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN29(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN29_SHIFT)) & DMA_COMMON_INTENSET_INTEN29_MASK)
#define DMA_COMMON_INTENSET_INTEN30_MASK         (0x40000000U)
#define DMA_COMMON_INTENSET_INTEN30_SHIFT        (30U)
/*! INTEN30 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN30(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN30_SHIFT)) & DMA_COMMON_INTENSET_INTEN30_MASK)
#define DMA_COMMON_INTENSET_INTEN31_MASK         (0x80000000U)
#define DMA_COMMON_INTENSET_INTEN31_SHIFT        (31U)
/*! INTEN31 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET_INTEN31(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN31_SHIFT)) & DMA_COMMON_INTENSET_INTEN31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENSET */
#define DMA_COMMON_INTENSET_COUNT                (1U)

/*! @name COMMON_INTENSET1 - Interrupt Enable read and Set for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTENSET1_INTEN32_MASK        (0x1U)
#define DMA_COMMON_INTENSET1_INTEN32_SHIFT       (0U)
/*! INTEN32 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN32(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
#define DMA_COMMON_INTENSET1_INTEN33_MASK        (0x2U)
#define DMA_COMMON_INTENSET1_INTEN33_SHIFT       (1U)
/*! INTEN33 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN33(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN33_SHIFT)) & DMA_COMMON_INTENSET1_INTEN33_MASK)
#define DMA_COMMON_INTENSET1_INTEN34_MASK        (0x4U)
#define DMA_COMMON_INTENSET1_INTEN34_SHIFT       (2U)
/*! INTEN34 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN34(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN34_SHIFT)) & DMA_COMMON_INTENSET1_INTEN34_MASK)
#define DMA_COMMON_INTENSET1_INTEN35_MASK        (0x8U)
#define DMA_COMMON_INTENSET1_INTEN35_SHIFT       (3U)
/*! INTEN35 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN35(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN35_SHIFT)) & DMA_COMMON_INTENSET1_INTEN35_MASK)
#define DMA_COMMON_INTENSET1_INTEN36_MASK        (0x10U)
#define DMA_COMMON_INTENSET1_INTEN36_SHIFT       (4U)
/*! INTEN36 - Interrupt Enable read and set for DMA channel.
 *  0b0..The Interrupt for DMA channel is disabled.
 *  0b1..The Interrupt for DMA channel is enabled.
 */
#define DMA_COMMON_INTENSET1_INTEN36(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN36_SHIFT)) & DMA_COMMON_INTENSET1_INTEN36_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENSET1 */
#define DMA_COMMON_INTENSET1_COUNT               (1U)

/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTENCLR_CLR0_MASK            (0x1U)
#define DMA_COMMON_INTENCLR_CLR0_SHIFT           (0U)
/*! CLR0 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR0(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR0_SHIFT)) & DMA_COMMON_INTENCLR_CLR0_MASK)
#define DMA_COMMON_INTENCLR_CLR1_MASK            (0x2U)
#define DMA_COMMON_INTENCLR_CLR1_SHIFT           (1U)
/*! CLR1 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR1(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR1_SHIFT)) & DMA_COMMON_INTENCLR_CLR1_MASK)
#define DMA_COMMON_INTENCLR_CLR2_MASK            (0x4U)
#define DMA_COMMON_INTENCLR_CLR2_SHIFT           (2U)
/*! CLR2 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR2(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR2_SHIFT)) & DMA_COMMON_INTENCLR_CLR2_MASK)
#define DMA_COMMON_INTENCLR_CLR3_MASK            (0x8U)
#define DMA_COMMON_INTENCLR_CLR3_SHIFT           (3U)
/*! CLR3 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR3(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR3_SHIFT)) & DMA_COMMON_INTENCLR_CLR3_MASK)
#define DMA_COMMON_INTENCLR_CLR4_MASK            (0x10U)
#define DMA_COMMON_INTENCLR_CLR4_SHIFT           (4U)
/*! CLR4 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR4(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR4_SHIFT)) & DMA_COMMON_INTENCLR_CLR4_MASK)
#define DMA_COMMON_INTENCLR_CLR5_MASK            (0x20U)
#define DMA_COMMON_INTENCLR_CLR5_SHIFT           (5U)
/*! CLR5 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR5(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR5_SHIFT)) & DMA_COMMON_INTENCLR_CLR5_MASK)
#define DMA_COMMON_INTENCLR_CLR6_MASK            (0x40U)
#define DMA_COMMON_INTENCLR_CLR6_SHIFT           (6U)
/*! CLR6 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR6(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR6_SHIFT)) & DMA_COMMON_INTENCLR_CLR6_MASK)
#define DMA_COMMON_INTENCLR_CLR7_MASK            (0x80U)
#define DMA_COMMON_INTENCLR_CLR7_SHIFT           (7U)
/*! CLR7 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR7(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR7_SHIFT)) & DMA_COMMON_INTENCLR_CLR7_MASK)
#define DMA_COMMON_INTENCLR_CLR8_MASK            (0x100U)
#define DMA_COMMON_INTENCLR_CLR8_SHIFT           (8U)
/*! CLR8 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR8(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR8_SHIFT)) & DMA_COMMON_INTENCLR_CLR8_MASK)
#define DMA_COMMON_INTENCLR_CLR9_MASK            (0x200U)
#define DMA_COMMON_INTENCLR_CLR9_SHIFT           (9U)
/*! CLR9 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR9(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR9_SHIFT)) & DMA_COMMON_INTENCLR_CLR9_MASK)
#define DMA_COMMON_INTENCLR_CLR10_MASK           (0x400U)
#define DMA_COMMON_INTENCLR_CLR10_SHIFT          (10U)
/*! CLR10 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR10(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR10_SHIFT)) & DMA_COMMON_INTENCLR_CLR10_MASK)
#define DMA_COMMON_INTENCLR_CLR11_MASK           (0x800U)
#define DMA_COMMON_INTENCLR_CLR11_SHIFT          (11U)
/*! CLR11 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR11(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR11_SHIFT)) & DMA_COMMON_INTENCLR_CLR11_MASK)
#define DMA_COMMON_INTENCLR_CLR12_MASK           (0x1000U)
#define DMA_COMMON_INTENCLR_CLR12_SHIFT          (12U)
/*! CLR12 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR12(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR12_SHIFT)) & DMA_COMMON_INTENCLR_CLR12_MASK)
#define DMA_COMMON_INTENCLR_CLR13_MASK           (0x2000U)
#define DMA_COMMON_INTENCLR_CLR13_SHIFT          (13U)
/*! CLR13 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR13(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR13_SHIFT)) & DMA_COMMON_INTENCLR_CLR13_MASK)
#define DMA_COMMON_INTENCLR_CLR14_MASK           (0x4000U)
#define DMA_COMMON_INTENCLR_CLR14_SHIFT          (14U)
/*! CLR14 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR14(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR14_SHIFT)) & DMA_COMMON_INTENCLR_CLR14_MASK)
#define DMA_COMMON_INTENCLR_CLR15_MASK           (0x8000U)
#define DMA_COMMON_INTENCLR_CLR15_SHIFT          (15U)
/*! CLR15 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR15(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR15_SHIFT)) & DMA_COMMON_INTENCLR_CLR15_MASK)
#define DMA_COMMON_INTENCLR_CLR16_MASK           (0x10000U)
#define DMA_COMMON_INTENCLR_CLR16_SHIFT          (16U)
/*! CLR16 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR16(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR16_SHIFT)) & DMA_COMMON_INTENCLR_CLR16_MASK)
#define DMA_COMMON_INTENCLR_CLR17_MASK           (0x20000U)
#define DMA_COMMON_INTENCLR_CLR17_SHIFT          (17U)
/*! CLR17 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR17(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR17_SHIFT)) & DMA_COMMON_INTENCLR_CLR17_MASK)
#define DMA_COMMON_INTENCLR_CLR18_MASK           (0x40000U)
#define DMA_COMMON_INTENCLR_CLR18_SHIFT          (18U)
/*! CLR18 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR18(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR18_SHIFT)) & DMA_COMMON_INTENCLR_CLR18_MASK)
#define DMA_COMMON_INTENCLR_CLR19_MASK           (0x80000U)
#define DMA_COMMON_INTENCLR_CLR19_SHIFT          (19U)
/*! CLR19 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR19(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR19_SHIFT)) & DMA_COMMON_INTENCLR_CLR19_MASK)
#define DMA_COMMON_INTENCLR_CLR20_MASK           (0x100000U)
#define DMA_COMMON_INTENCLR_CLR20_SHIFT          (20U)
/*! CLR20 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR20(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR20_SHIFT)) & DMA_COMMON_INTENCLR_CLR20_MASK)
#define DMA_COMMON_INTENCLR_CLR21_MASK           (0x200000U)
#define DMA_COMMON_INTENCLR_CLR21_SHIFT          (21U)
/*! CLR21 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR21(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR21_SHIFT)) & DMA_COMMON_INTENCLR_CLR21_MASK)
#define DMA_COMMON_INTENCLR_CLR22_MASK           (0x400000U)
#define DMA_COMMON_INTENCLR_CLR22_SHIFT          (22U)
/*! CLR22 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR22(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR22_SHIFT)) & DMA_COMMON_INTENCLR_CLR22_MASK)
#define DMA_COMMON_INTENCLR_CLR23_MASK           (0x800000U)
#define DMA_COMMON_INTENCLR_CLR23_SHIFT          (23U)
/*! CLR23 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR23(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR23_SHIFT)) & DMA_COMMON_INTENCLR_CLR23_MASK)
#define DMA_COMMON_INTENCLR_CLR24_MASK           (0x1000000U)
#define DMA_COMMON_INTENCLR_CLR24_SHIFT          (24U)
/*! CLR24 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR24(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR24_SHIFT)) & DMA_COMMON_INTENCLR_CLR24_MASK)
#define DMA_COMMON_INTENCLR_CLR25_MASK           (0x2000000U)
#define DMA_COMMON_INTENCLR_CLR25_SHIFT          (25U)
/*! CLR25 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR25(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR25_SHIFT)) & DMA_COMMON_INTENCLR_CLR25_MASK)
#define DMA_COMMON_INTENCLR_CLR26_MASK           (0x4000000U)
#define DMA_COMMON_INTENCLR_CLR26_SHIFT          (26U)
/*! CLR26 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR26(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR26_SHIFT)) & DMA_COMMON_INTENCLR_CLR26_MASK)
#define DMA_COMMON_INTENCLR_CLR27_MASK           (0x8000000U)
#define DMA_COMMON_INTENCLR_CLR27_SHIFT          (27U)
/*! CLR27 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR27(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR27_SHIFT)) & DMA_COMMON_INTENCLR_CLR27_MASK)
#define DMA_COMMON_INTENCLR_CLR28_MASK           (0x10000000U)
#define DMA_COMMON_INTENCLR_CLR28_SHIFT          (28U)
/*! CLR28 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR28(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR28_SHIFT)) & DMA_COMMON_INTENCLR_CLR28_MASK)
#define DMA_COMMON_INTENCLR_CLR29_MASK           (0x20000000U)
#define DMA_COMMON_INTENCLR_CLR29_SHIFT          (29U)
/*! CLR29 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR29(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR29_SHIFT)) & DMA_COMMON_INTENCLR_CLR29_MASK)
#define DMA_COMMON_INTENCLR_CLR30_MASK           (0x40000000U)
#define DMA_COMMON_INTENCLR_CLR30_SHIFT          (30U)
/*! CLR30 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR30(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR30_SHIFT)) & DMA_COMMON_INTENCLR_CLR30_MASK)
#define DMA_COMMON_INTENCLR_CLR31_MASK           (0x80000000U)
#define DMA_COMMON_INTENCLR_CLR31_SHIFT          (31U)
/*! CLR31 - Writing ones to this register clears corresponding bits in the DMAIntEnSet0.
 */
#define DMA_COMMON_INTENCLR_CLR31(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR31_SHIFT)) & DMA_COMMON_INTENCLR_CLR31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENCLR */
#define DMA_COMMON_INTENCLR_COUNT                (1U)

/*! @name COMMON_INTENCLR1 - Interrupt Enable Clear for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTENCLR1_CLR32_MASK          (0x1U)
#define DMA_COMMON_INTENCLR1_CLR32_SHIFT         (0U)
/*! CLR32 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR32(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR32_SHIFT)) & DMA_COMMON_INTENCLR1_CLR32_MASK)
#define DMA_COMMON_INTENCLR1_CLR33_MASK          (0x2U)
#define DMA_COMMON_INTENCLR1_CLR33_SHIFT         (1U)
/*! CLR33 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR33(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR33_SHIFT)) & DMA_COMMON_INTENCLR1_CLR33_MASK)
#define DMA_COMMON_INTENCLR1_CLR34_MASK          (0x4U)
#define DMA_COMMON_INTENCLR1_CLR34_SHIFT         (2U)
/*! CLR34 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR34(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR34_SHIFT)) & DMA_COMMON_INTENCLR1_CLR34_MASK)
#define DMA_COMMON_INTENCLR1_CLR35_MASK          (0x8U)
#define DMA_COMMON_INTENCLR1_CLR35_SHIFT         (3U)
/*! CLR35 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR35(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR35_SHIFT)) & DMA_COMMON_INTENCLR1_CLR35_MASK)
#define DMA_COMMON_INTENCLR1_CLR36_MASK          (0x10U)
#define DMA_COMMON_INTENCLR1_CLR36_SHIFT         (4U)
/*! CLR36 - Writing ones to this register clears corresponding bits in the DMAIntEnSet1.
 */
#define DMA_COMMON_INTENCLR1_CLR36(x)            (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR1_CLR36_SHIFT)) & DMA_COMMON_INTENCLR1_CLR36_MASK)
/*! @} */

/* The count of DMA_COMMON_INTENCLR1 */
#define DMA_COMMON_INTENCLR1_COUNT               (1U)

/*! @name COMMON_INTA - Interrupt A status for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTA_INTA0_MASK               (0x1U)
#define DMA_COMMON_INTA_INTA0_SHIFT              (0U)
/*! INTA0 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA0_SHIFT)) & DMA_COMMON_INTA_INTA0_MASK)
#define DMA_COMMON_INTA_INTA1_MASK               (0x2U)
#define DMA_COMMON_INTA_INTA1_SHIFT              (1U)
/*! INTA1 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA1_SHIFT)) & DMA_COMMON_INTA_INTA1_MASK)
#define DMA_COMMON_INTA_INTA2_MASK               (0x4U)
#define DMA_COMMON_INTA_INTA2_SHIFT              (2U)
/*! INTA2 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA2_SHIFT)) & DMA_COMMON_INTA_INTA2_MASK)
#define DMA_COMMON_INTA_INTA3_MASK               (0x8U)
#define DMA_COMMON_INTA_INTA3_SHIFT              (3U)
/*! INTA3 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA3_SHIFT)) & DMA_COMMON_INTA_INTA3_MASK)
#define DMA_COMMON_INTA_INTA4_MASK               (0x10U)
#define DMA_COMMON_INTA_INTA4_SHIFT              (4U)
/*! INTA4 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA4_SHIFT)) & DMA_COMMON_INTA_INTA4_MASK)
#define DMA_COMMON_INTA_INTA5_MASK               (0x20U)
#define DMA_COMMON_INTA_INTA5_SHIFT              (5U)
/*! INTA5 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA5_SHIFT)) & DMA_COMMON_INTA_INTA5_MASK)
#define DMA_COMMON_INTA_INTA6_MASK               (0x40U)
#define DMA_COMMON_INTA_INTA6_SHIFT              (6U)
/*! INTA6 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA6_SHIFT)) & DMA_COMMON_INTA_INTA6_MASK)
#define DMA_COMMON_INTA_INTA7_MASK               (0x80U)
#define DMA_COMMON_INTA_INTA7_SHIFT              (7U)
/*! INTA7 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA7_SHIFT)) & DMA_COMMON_INTA_INTA7_MASK)
#define DMA_COMMON_INTA_INTA8_MASK               (0x100U)
#define DMA_COMMON_INTA_INTA8_SHIFT              (8U)
/*! INTA8 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA8_SHIFT)) & DMA_COMMON_INTA_INTA8_MASK)
#define DMA_COMMON_INTA_INTA9_MASK               (0x200U)
#define DMA_COMMON_INTA_INTA9_SHIFT              (9U)
/*! INTA9 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA9_SHIFT)) & DMA_COMMON_INTA_INTA9_MASK)
#define DMA_COMMON_INTA_INTA10_MASK              (0x400U)
#define DMA_COMMON_INTA_INTA10_SHIFT             (10U)
/*! INTA10 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA10_SHIFT)) & DMA_COMMON_INTA_INTA10_MASK)
#define DMA_COMMON_INTA_INTA11_MASK              (0x800U)
#define DMA_COMMON_INTA_INTA11_SHIFT             (11U)
/*! INTA11 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA11_SHIFT)) & DMA_COMMON_INTA_INTA11_MASK)
#define DMA_COMMON_INTA_INTA12_MASK              (0x1000U)
#define DMA_COMMON_INTA_INTA12_SHIFT             (12U)
/*! INTA12 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA12_SHIFT)) & DMA_COMMON_INTA_INTA12_MASK)
#define DMA_COMMON_INTA_INTA13_MASK              (0x2000U)
#define DMA_COMMON_INTA_INTA13_SHIFT             (13U)
/*! INTA13 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA13_SHIFT)) & DMA_COMMON_INTA_INTA13_MASK)
#define DMA_COMMON_INTA_INTA14_MASK              (0x4000U)
#define DMA_COMMON_INTA_INTA14_SHIFT             (14U)
/*! INTA14 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA14_SHIFT)) & DMA_COMMON_INTA_INTA14_MASK)
#define DMA_COMMON_INTA_INTA15_MASK              (0x8000U)
#define DMA_COMMON_INTA_INTA15_SHIFT             (15U)
/*! INTA15 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA15_SHIFT)) & DMA_COMMON_INTA_INTA15_MASK)
#define DMA_COMMON_INTA_INTA16_MASK              (0x10000U)
#define DMA_COMMON_INTA_INTA16_SHIFT             (16U)
/*! INTA16 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA16_SHIFT)) & DMA_COMMON_INTA_INTA16_MASK)
#define DMA_COMMON_INTA_INTA17_MASK              (0x20000U)
#define DMA_COMMON_INTA_INTA17_SHIFT             (17U)
/*! INTA17 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA17_SHIFT)) & DMA_COMMON_INTA_INTA17_MASK)
#define DMA_COMMON_INTA_INTA18_MASK              (0x40000U)
#define DMA_COMMON_INTA_INTA18_SHIFT             (18U)
/*! INTA18 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA18_SHIFT)) & DMA_COMMON_INTA_INTA18_MASK)
#define DMA_COMMON_INTA_INTA19_MASK              (0x80000U)
#define DMA_COMMON_INTA_INTA19_SHIFT             (19U)
/*! INTA19 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA19_SHIFT)) & DMA_COMMON_INTA_INTA19_MASK)
#define DMA_COMMON_INTA_INTA20_MASK              (0x100000U)
#define DMA_COMMON_INTA_INTA20_SHIFT             (20U)
/*! INTA20 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA20_SHIFT)) & DMA_COMMON_INTA_INTA20_MASK)
#define DMA_COMMON_INTA_INTA21_MASK              (0x200000U)
#define DMA_COMMON_INTA_INTA21_SHIFT             (21U)
/*! INTA21 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA21_SHIFT)) & DMA_COMMON_INTA_INTA21_MASK)
#define DMA_COMMON_INTA_INTA22_MASK              (0x400000U)
#define DMA_COMMON_INTA_INTA22_SHIFT             (22U)
/*! INTA22 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA22_SHIFT)) & DMA_COMMON_INTA_INTA22_MASK)
#define DMA_COMMON_INTA_INTA23_MASK              (0x800000U)
#define DMA_COMMON_INTA_INTA23_SHIFT             (23U)
/*! INTA23 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA23_SHIFT)) & DMA_COMMON_INTA_INTA23_MASK)
#define DMA_COMMON_INTA_INTA24_MASK              (0x1000000U)
#define DMA_COMMON_INTA_INTA24_SHIFT             (24U)
/*! INTA24 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA24_SHIFT)) & DMA_COMMON_INTA_INTA24_MASK)
#define DMA_COMMON_INTA_INTA25_MASK              (0x2000000U)
#define DMA_COMMON_INTA_INTA25_SHIFT             (25U)
/*! INTA25 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA25_SHIFT)) & DMA_COMMON_INTA_INTA25_MASK)
#define DMA_COMMON_INTA_INTA26_MASK              (0x4000000U)
#define DMA_COMMON_INTA_INTA26_SHIFT             (26U)
/*! INTA26 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA26_SHIFT)) & DMA_COMMON_INTA_INTA26_MASK)
#define DMA_COMMON_INTA_INTA27_MASK              (0x8000000U)
#define DMA_COMMON_INTA_INTA27_SHIFT             (27U)
/*! INTA27 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA27_SHIFT)) & DMA_COMMON_INTA_INTA27_MASK)
#define DMA_COMMON_INTA_INTA28_MASK              (0x10000000U)
#define DMA_COMMON_INTA_INTA28_SHIFT             (28U)
/*! INTA28 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA28_SHIFT)) & DMA_COMMON_INTA_INTA28_MASK)
#define DMA_COMMON_INTA_INTA29_MASK              (0x20000000U)
#define DMA_COMMON_INTA_INTA29_SHIFT             (29U)
/*! INTA29 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA29_SHIFT)) & DMA_COMMON_INTA_INTA29_MASK)
#define DMA_COMMON_INTA_INTA30_MASK              (0x40000000U)
#define DMA_COMMON_INTA_INTA30_SHIFT             (30U)
/*! INTA30 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA30_SHIFT)) & DMA_COMMON_INTA_INTA30_MASK)
#define DMA_COMMON_INTA_INTA31_MASK              (0x80000000U)
#define DMA_COMMON_INTA_INTA31_SHIFT             (31U)
/*! INTA31 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA_INTA31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_INTA31_SHIFT)) & DMA_COMMON_INTA_INTA31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTA */
#define DMA_COMMON_INTA_COUNT                    (1U)

/*! @name COMMON_INTA1 - Interrupt A status for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTA1_INTA32_MASK             (0x1U)
#define DMA_COMMON_INTA1_INTA32_SHIFT            (0U)
/*! INTA32 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA32(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA32_SHIFT)) & DMA_COMMON_INTA1_INTA32_MASK)
#define DMA_COMMON_INTA1_INTA33_MASK             (0x2U)
#define DMA_COMMON_INTA1_INTA33_SHIFT            (1U)
/*! INTA33 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA33(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA33_SHIFT)) & DMA_COMMON_INTA1_INTA33_MASK)
#define DMA_COMMON_INTA1_INTA34_MASK             (0x4U)
#define DMA_COMMON_INTA1_INTA34_SHIFT            (2U)
/*! INTA34 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA34(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA34_SHIFT)) & DMA_COMMON_INTA1_INTA34_MASK)
#define DMA_COMMON_INTA1_INTA35_MASK             (0x8U)
#define DMA_COMMON_INTA1_INTA35_SHIFT            (3U)
/*! INTA35 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA35(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA35_SHIFT)) & DMA_COMMON_INTA1_INTA35_MASK)
#define DMA_COMMON_INTA1_INTA36_MASK             (0x10U)
#define DMA_COMMON_INTA1_INTA36_SHIFT            (4U)
/*! INTA36 - Interrupt A status for DMA channel.
 *  0b0..The DMA channel interrupt A is not active.
 *  0b1..The DMA channel interrupt A is active.
 */
#define DMA_COMMON_INTA1_INTA36(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA1_INTA36_SHIFT)) & DMA_COMMON_INTA1_INTA36_MASK)
/*! @} */

/* The count of DMA_COMMON_INTA1 */
#define DMA_COMMON_INTA1_COUNT                   (1U)

/*! @name COMMON_INTB - Interrupt B status for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTB_INTB0_MASK               (0x1U)
#define DMA_COMMON_INTB_INTB0_SHIFT              (0U)
/*! INTB0 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB0(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB0_SHIFT)) & DMA_COMMON_INTB_INTB0_MASK)
#define DMA_COMMON_INTB_INTB1_MASK               (0x2U)
#define DMA_COMMON_INTB_INTB1_SHIFT              (1U)
/*! INTB1 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB1(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB1_SHIFT)) & DMA_COMMON_INTB_INTB1_MASK)
#define DMA_COMMON_INTB_INTB2_MASK               (0x4U)
#define DMA_COMMON_INTB_INTB2_SHIFT              (2U)
/*! INTB2 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB2(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB2_SHIFT)) & DMA_COMMON_INTB_INTB2_MASK)
#define DMA_COMMON_INTB_INTB3_MASK               (0x8U)
#define DMA_COMMON_INTB_INTB3_SHIFT              (3U)
/*! INTB3 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB3(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB3_SHIFT)) & DMA_COMMON_INTB_INTB3_MASK)
#define DMA_COMMON_INTB_INTB4_MASK               (0x10U)
#define DMA_COMMON_INTB_INTB4_SHIFT              (4U)
/*! INTB4 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB4(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB4_SHIFT)) & DMA_COMMON_INTB_INTB4_MASK)
#define DMA_COMMON_INTB_INTB5_MASK               (0x20U)
#define DMA_COMMON_INTB_INTB5_SHIFT              (5U)
/*! INTB5 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB5(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB5_SHIFT)) & DMA_COMMON_INTB_INTB5_MASK)
#define DMA_COMMON_INTB_INTB6_MASK               (0x40U)
#define DMA_COMMON_INTB_INTB6_SHIFT              (6U)
/*! INTB6 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB6(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB6_SHIFT)) & DMA_COMMON_INTB_INTB6_MASK)
#define DMA_COMMON_INTB_INTB7_MASK               (0x80U)
#define DMA_COMMON_INTB_INTB7_SHIFT              (7U)
/*! INTB7 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB7(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB7_SHIFT)) & DMA_COMMON_INTB_INTB7_MASK)
#define DMA_COMMON_INTB_INTB8_MASK               (0x100U)
#define DMA_COMMON_INTB_INTB8_SHIFT              (8U)
/*! INTB8 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB8(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB8_SHIFT)) & DMA_COMMON_INTB_INTB8_MASK)
#define DMA_COMMON_INTB_INTB9_MASK               (0x200U)
#define DMA_COMMON_INTB_INTB9_SHIFT              (9U)
/*! INTB9 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB9(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB9_SHIFT)) & DMA_COMMON_INTB_INTB9_MASK)
#define DMA_COMMON_INTB_INTB10_MASK              (0x400U)
#define DMA_COMMON_INTB_INTB10_SHIFT             (10U)
/*! INTB10 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB10(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB10_SHIFT)) & DMA_COMMON_INTB_INTB10_MASK)
#define DMA_COMMON_INTB_INTB11_MASK              (0x800U)
#define DMA_COMMON_INTB_INTB11_SHIFT             (11U)
/*! INTB11 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB11(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB11_SHIFT)) & DMA_COMMON_INTB_INTB11_MASK)
#define DMA_COMMON_INTB_INTB12_MASK              (0x1000U)
#define DMA_COMMON_INTB_INTB12_SHIFT             (12U)
/*! INTB12 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB12(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB12_SHIFT)) & DMA_COMMON_INTB_INTB12_MASK)
#define DMA_COMMON_INTB_INTB13_MASK              (0x2000U)
#define DMA_COMMON_INTB_INTB13_SHIFT             (13U)
/*! INTB13 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB13(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB13_SHIFT)) & DMA_COMMON_INTB_INTB13_MASK)
#define DMA_COMMON_INTB_INTB14_MASK              (0x4000U)
#define DMA_COMMON_INTB_INTB14_SHIFT             (14U)
/*! INTB14 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB14(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB14_SHIFT)) & DMA_COMMON_INTB_INTB14_MASK)
#define DMA_COMMON_INTB_INTB15_MASK              (0x8000U)
#define DMA_COMMON_INTB_INTB15_SHIFT             (15U)
/*! INTB15 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB15(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB15_SHIFT)) & DMA_COMMON_INTB_INTB15_MASK)
#define DMA_COMMON_INTB_INTB16_MASK              (0x10000U)
#define DMA_COMMON_INTB_INTB16_SHIFT             (16U)
/*! INTB16 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB16(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB16_SHIFT)) & DMA_COMMON_INTB_INTB16_MASK)
#define DMA_COMMON_INTB_INTB17_MASK              (0x20000U)
#define DMA_COMMON_INTB_INTB17_SHIFT             (17U)
/*! INTB17 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB17(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB17_SHIFT)) & DMA_COMMON_INTB_INTB17_MASK)
#define DMA_COMMON_INTB_INTB18_MASK              (0x40000U)
#define DMA_COMMON_INTB_INTB18_SHIFT             (18U)
/*! INTB18 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB18(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB18_SHIFT)) & DMA_COMMON_INTB_INTB18_MASK)
#define DMA_COMMON_INTB_INTB19_MASK              (0x80000U)
#define DMA_COMMON_INTB_INTB19_SHIFT             (19U)
/*! INTB19 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB19(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB19_SHIFT)) & DMA_COMMON_INTB_INTB19_MASK)
#define DMA_COMMON_INTB_INTB20_MASK              (0x100000U)
#define DMA_COMMON_INTB_INTB20_SHIFT             (20U)
/*! INTB20 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB20(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB20_SHIFT)) & DMA_COMMON_INTB_INTB20_MASK)
#define DMA_COMMON_INTB_INTB21_MASK              (0x200000U)
#define DMA_COMMON_INTB_INTB21_SHIFT             (21U)
/*! INTB21 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB21(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB21_SHIFT)) & DMA_COMMON_INTB_INTB21_MASK)
#define DMA_COMMON_INTB_INTB22_MASK              (0x400000U)
#define DMA_COMMON_INTB_INTB22_SHIFT             (22U)
/*! INTB22 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB22(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB22_SHIFT)) & DMA_COMMON_INTB_INTB22_MASK)
#define DMA_COMMON_INTB_INTB23_MASK              (0x800000U)
#define DMA_COMMON_INTB_INTB23_SHIFT             (23U)
/*! INTB23 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB23(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB23_SHIFT)) & DMA_COMMON_INTB_INTB23_MASK)
#define DMA_COMMON_INTB_INTB24_MASK              (0x1000000U)
#define DMA_COMMON_INTB_INTB24_SHIFT             (24U)
/*! INTB24 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB24(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB24_SHIFT)) & DMA_COMMON_INTB_INTB24_MASK)
#define DMA_COMMON_INTB_INTB25_MASK              (0x2000000U)
#define DMA_COMMON_INTB_INTB25_SHIFT             (25U)
/*! INTB25 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB25(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB25_SHIFT)) & DMA_COMMON_INTB_INTB25_MASK)
#define DMA_COMMON_INTB_INTB26_MASK              (0x4000000U)
#define DMA_COMMON_INTB_INTB26_SHIFT             (26U)
/*! INTB26 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB26(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB26_SHIFT)) & DMA_COMMON_INTB_INTB26_MASK)
#define DMA_COMMON_INTB_INTB27_MASK              (0x8000000U)
#define DMA_COMMON_INTB_INTB27_SHIFT             (27U)
/*! INTB27 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB27(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB27_SHIFT)) & DMA_COMMON_INTB_INTB27_MASK)
#define DMA_COMMON_INTB_INTB28_MASK              (0x10000000U)
#define DMA_COMMON_INTB_INTB28_SHIFT             (28U)
/*! INTB28 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB28(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB28_SHIFT)) & DMA_COMMON_INTB_INTB28_MASK)
#define DMA_COMMON_INTB_INTB29_MASK              (0x20000000U)
#define DMA_COMMON_INTB_INTB29_SHIFT             (29U)
/*! INTB29 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB29(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB29_SHIFT)) & DMA_COMMON_INTB_INTB29_MASK)
#define DMA_COMMON_INTB_INTB30_MASK              (0x40000000U)
#define DMA_COMMON_INTB_INTB30_SHIFT             (30U)
/*! INTB30 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB30(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB30_SHIFT)) & DMA_COMMON_INTB_INTB30_MASK)
#define DMA_COMMON_INTB_INTB31_MASK              (0x80000000U)
#define DMA_COMMON_INTB_INTB31_SHIFT             (31U)
/*! INTB31 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB_INTB31(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_INTB31_SHIFT)) & DMA_COMMON_INTB_INTB31_MASK)
/*! @} */

/* The count of DMA_COMMON_INTB */
#define DMA_COMMON_INTB_COUNT                    (1U)

/*! @name COMMON_INTB1 - Interrupt B status for all DMA channels */
/*! @{ */
#define DMA_COMMON_INTB1_INTB0_MASK              (0x1U)
#define DMA_COMMON_INTB1_INTB0_SHIFT             (0U)
/*! INTB0 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB0(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB0_SHIFT)) & DMA_COMMON_INTB1_INTB0_MASK)
#define DMA_COMMON_INTB1_INTB1_MASK              (0x2U)
#define DMA_COMMON_INTB1_INTB1_SHIFT             (1U)
/*! INTB1 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB1(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB1_SHIFT)) & DMA_COMMON_INTB1_INTB1_MASK)
#define DMA_COMMON_INTB1_INTB2_MASK              (0x4U)
#define DMA_COMMON_INTB1_INTB2_SHIFT             (2U)
/*! INTB2 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB2(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB2_SHIFT)) & DMA_COMMON_INTB1_INTB2_MASK)
#define DMA_COMMON_INTB1_INTB3_MASK              (0x8U)
#define DMA_COMMON_INTB1_INTB3_SHIFT             (3U)
/*! INTB3 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB3(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB3_SHIFT)) & DMA_COMMON_INTB1_INTB3_MASK)
#define DMA_COMMON_INTB1_INTB4_MASK              (0x10U)
#define DMA_COMMON_INTB1_INTB4_SHIFT             (4U)
/*! INTB4 - Interrupt B status for DMA channel.
 *  0b0..The DMA channel interrupt B is not active.
 *  0b1..The DMA channel interrupt B is active.
 */
#define DMA_COMMON_INTB1_INTB4(x)                (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB1_INTB4_SHIFT)) & DMA_COMMON_INTB1_INTB4_MASK)
/*! @} */

/* The count of DMA_COMMON_INTB1 */
#define DMA_COMMON_INTB1_COUNT                   (1U)

/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels */
/*! @{ */
#define DMA_COMMON_SETVALID_SETVALID0_MASK       (0x1U)
#define DMA_COMMON_SETVALID_SETVALID0_SHIFT      (0U)
/*! SETVALID0 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID0(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID0_SHIFT)) & DMA_COMMON_SETVALID_SETVALID0_MASK)
#define DMA_COMMON_SETVALID_SETVALID1_MASK       (0x2U)
#define DMA_COMMON_SETVALID_SETVALID1_SHIFT      (1U)
/*! SETVALID1 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID1(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID1_SHIFT)) & DMA_COMMON_SETVALID_SETVALID1_MASK)
#define DMA_COMMON_SETVALID_SETVALID2_MASK       (0x4U)
#define DMA_COMMON_SETVALID_SETVALID2_SHIFT      (2U)
/*! SETVALID2 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID2(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID2_SHIFT)) & DMA_COMMON_SETVALID_SETVALID2_MASK)
#define DMA_COMMON_SETVALID_SETVALID3_MASK       (0x8U)
#define DMA_COMMON_SETVALID_SETVALID3_SHIFT      (3U)
/*! SETVALID3 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID3(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID3_SHIFT)) & DMA_COMMON_SETVALID_SETVALID3_MASK)
#define DMA_COMMON_SETVALID_SETVALID4_MASK       (0x10U)
#define DMA_COMMON_SETVALID_SETVALID4_SHIFT      (4U)
/*! SETVALID4 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID4(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID4_SHIFT)) & DMA_COMMON_SETVALID_SETVALID4_MASK)
#define DMA_COMMON_SETVALID_SETVALID5_MASK       (0x20U)
#define DMA_COMMON_SETVALID_SETVALID5_SHIFT      (5U)
/*! SETVALID5 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID5(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID5_SHIFT)) & DMA_COMMON_SETVALID_SETVALID5_MASK)
#define DMA_COMMON_SETVALID_SETVALID6_MASK       (0x40U)
#define DMA_COMMON_SETVALID_SETVALID6_SHIFT      (6U)
/*! SETVALID6 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID6(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID6_SHIFT)) & DMA_COMMON_SETVALID_SETVALID6_MASK)
#define DMA_COMMON_SETVALID_SETVALID7_MASK       (0x80U)
#define DMA_COMMON_SETVALID_SETVALID7_SHIFT      (7U)
/*! SETVALID7 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID7(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID7_SHIFT)) & DMA_COMMON_SETVALID_SETVALID7_MASK)
#define DMA_COMMON_SETVALID_SETVALID8_MASK       (0x100U)
#define DMA_COMMON_SETVALID_SETVALID8_SHIFT      (8U)
/*! SETVALID8 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID8(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID8_SHIFT)) & DMA_COMMON_SETVALID_SETVALID8_MASK)
#define DMA_COMMON_SETVALID_SETVALID9_MASK       (0x200U)
#define DMA_COMMON_SETVALID_SETVALID9_SHIFT      (9U)
/*! SETVALID9 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID9(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID9_SHIFT)) & DMA_COMMON_SETVALID_SETVALID9_MASK)
#define DMA_COMMON_SETVALID_SETVALID10_MASK      (0x400U)
#define DMA_COMMON_SETVALID_SETVALID10_SHIFT     (10U)
/*! SETVALID10 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID10(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID10_SHIFT)) & DMA_COMMON_SETVALID_SETVALID10_MASK)
#define DMA_COMMON_SETVALID_SETVALID11_MASK      (0x800U)
#define DMA_COMMON_SETVALID_SETVALID11_SHIFT     (11U)
/*! SETVALID11 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID11(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID11_SHIFT)) & DMA_COMMON_SETVALID_SETVALID11_MASK)
#define DMA_COMMON_SETVALID_SETVALID12_MASK      (0x1000U)
#define DMA_COMMON_SETVALID_SETVALID12_SHIFT     (12U)
/*! SETVALID12 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID12(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID12_SHIFT)) & DMA_COMMON_SETVALID_SETVALID12_MASK)
#define DMA_COMMON_SETVALID_SETVALID13_MASK      (0x2000U)
#define DMA_COMMON_SETVALID_SETVALID13_SHIFT     (13U)
/*! SETVALID13 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID13(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID13_SHIFT)) & DMA_COMMON_SETVALID_SETVALID13_MASK)
#define DMA_COMMON_SETVALID_SETVALID14_MASK      (0x4000U)
#define DMA_COMMON_SETVALID_SETVALID14_SHIFT     (14U)
/*! SETVALID14 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID14(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID14_SHIFT)) & DMA_COMMON_SETVALID_SETVALID14_MASK)
#define DMA_COMMON_SETVALID_SETVALID15_MASK      (0x8000U)
#define DMA_COMMON_SETVALID_SETVALID15_SHIFT     (15U)
/*! SETVALID15 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID15(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID15_SHIFT)) & DMA_COMMON_SETVALID_SETVALID15_MASK)
#define DMA_COMMON_SETVALID_SETVALID16_MASK      (0x10000U)
#define DMA_COMMON_SETVALID_SETVALID16_SHIFT     (16U)
/*! SETVALID16 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID16(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID16_SHIFT)) & DMA_COMMON_SETVALID_SETVALID16_MASK)
#define DMA_COMMON_SETVALID_SETVALID17_MASK      (0x20000U)
#define DMA_COMMON_SETVALID_SETVALID17_SHIFT     (17U)
/*! SETVALID17 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID17(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID17_SHIFT)) & DMA_COMMON_SETVALID_SETVALID17_MASK)
#define DMA_COMMON_SETVALID_SETVALID18_MASK      (0x40000U)
#define DMA_COMMON_SETVALID_SETVALID18_SHIFT     (18U)
/*! SETVALID18 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID18(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID18_SHIFT)) & DMA_COMMON_SETVALID_SETVALID18_MASK)
#define DMA_COMMON_SETVALID_SETVALID19_MASK      (0x80000U)
#define DMA_COMMON_SETVALID_SETVALID19_SHIFT     (19U)
/*! SETVALID19 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID19(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID19_SHIFT)) & DMA_COMMON_SETVALID_SETVALID19_MASK)
#define DMA_COMMON_SETVALID_SETVALID20_MASK      (0x100000U)
#define DMA_COMMON_SETVALID_SETVALID20_SHIFT     (20U)
/*! SETVALID20 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID20(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID20_SHIFT)) & DMA_COMMON_SETVALID_SETVALID20_MASK)
#define DMA_COMMON_SETVALID_SETVALID21_MASK      (0x200000U)
#define DMA_COMMON_SETVALID_SETVALID21_SHIFT     (21U)
/*! SETVALID21 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID21(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID21_SHIFT)) & DMA_COMMON_SETVALID_SETVALID21_MASK)
#define DMA_COMMON_SETVALID_SETVALID22_MASK      (0x400000U)
#define DMA_COMMON_SETVALID_SETVALID22_SHIFT     (22U)
/*! SETVALID22 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID22(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID22_SHIFT)) & DMA_COMMON_SETVALID_SETVALID22_MASK)
#define DMA_COMMON_SETVALID_SETVALID23_MASK      (0x800000U)
#define DMA_COMMON_SETVALID_SETVALID23_SHIFT     (23U)
/*! SETVALID23 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID23(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID23_SHIFT)) & DMA_COMMON_SETVALID_SETVALID23_MASK)
#define DMA_COMMON_SETVALID_SETVALID24_MASK      (0x1000000U)
#define DMA_COMMON_SETVALID_SETVALID24_SHIFT     (24U)
/*! SETVALID24 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID24(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID24_SHIFT)) & DMA_COMMON_SETVALID_SETVALID24_MASK)
#define DMA_COMMON_SETVALID_SETVALID25_MASK      (0x2000000U)
#define DMA_COMMON_SETVALID_SETVALID25_SHIFT     (25U)
/*! SETVALID25 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID25(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID25_SHIFT)) & DMA_COMMON_SETVALID_SETVALID25_MASK)
#define DMA_COMMON_SETVALID_SETVALID26_MASK      (0x4000000U)
#define DMA_COMMON_SETVALID_SETVALID26_SHIFT     (26U)
/*! SETVALID26 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID26(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID26_SHIFT)) & DMA_COMMON_SETVALID_SETVALID26_MASK)
#define DMA_COMMON_SETVALID_SETVALID27_MASK      (0x8000000U)
#define DMA_COMMON_SETVALID_SETVALID27_SHIFT     (27U)
/*! SETVALID27 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID27(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID27_SHIFT)) & DMA_COMMON_SETVALID_SETVALID27_MASK)
#define DMA_COMMON_SETVALID_SETVALID28_MASK      (0x10000000U)
#define DMA_COMMON_SETVALID_SETVALID28_SHIFT     (28U)
/*! SETVALID28 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID28(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID28_SHIFT)) & DMA_COMMON_SETVALID_SETVALID28_MASK)
#define DMA_COMMON_SETVALID_SETVALID29_MASK      (0x20000000U)
#define DMA_COMMON_SETVALID_SETVALID29_SHIFT     (29U)
/*! SETVALID29 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID29(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID29_SHIFT)) & DMA_COMMON_SETVALID_SETVALID29_MASK)
#define DMA_COMMON_SETVALID_SETVALID30_MASK      (0x40000000U)
#define DMA_COMMON_SETVALID_SETVALID30_SHIFT     (30U)
/*! SETVALID30 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID30(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID30_SHIFT)) & DMA_COMMON_SETVALID_SETVALID30_MASK)
#define DMA_COMMON_SETVALID_SETVALID31_MASK      (0x80000000U)
#define DMA_COMMON_SETVALID_SETVALID31_SHIFT     (31U)
/*! SETVALID31 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID_SETVALID31(x)        (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SETVALID31_SHIFT)) & DMA_COMMON_SETVALID_SETVALID31_MASK)
/*! @} */

/* The count of DMA_COMMON_SETVALID */
#define DMA_COMMON_SETVALID_COUNT                (1U)

/*! @name COMMON_SETVALID1 - Set ValidPending control bits for all DMA channels */
/*! @{ */
#define DMA_COMMON_SETVALID1_SETVALID32_MASK     (0x1U)
#define DMA_COMMON_SETVALID1_SETVALID32_SHIFT    (0U)
/*! SETVALID32 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID32(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID32_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID32_MASK)
#define DMA_COMMON_SETVALID1_SETVALID33_MASK     (0x2U)
#define DMA_COMMON_SETVALID1_SETVALID33_SHIFT    (1U)
/*! SETVALID33 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID33(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID33_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID33_MASK)
#define DMA_COMMON_SETVALID1_SETVALID34_MASK     (0x4U)
#define DMA_COMMON_SETVALID1_SETVALID34_SHIFT    (2U)
/*! SETVALID34 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID34(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID34_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID34_MASK)
#define DMA_COMMON_SETVALID1_SETVALID35_MASK     (0x8U)
#define DMA_COMMON_SETVALID1_SETVALID35_SHIFT    (3U)
/*! SETVALID35 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID35(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID35_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID35_MASK)
#define DMA_COMMON_SETVALID1_SETVALID36_MASK     (0x10U)
#define DMA_COMMON_SETVALID1_SETVALID36_SHIFT    (4U)
/*! SETVALID36 - SetValid control for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the ValidPending control bit for DMA channel.
 */
#define DMA_COMMON_SETVALID1_SETVALID36(x)       (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID1_SETVALID36_SHIFT)) & DMA_COMMON_SETVALID1_SETVALID36_MASK)
/*! @} */

/* The count of DMA_COMMON_SETVALID1 */
#define DMA_COMMON_SETVALID1_COUNT               (1U)

/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels */
/*! @{ */
#define DMA_COMMON_SETTRIG_SETTRIG0_MASK         (0x1U)
#define DMA_COMMON_SETTRIG_SETTRIG0_SHIFT        (0U)
/*! SETTRIG0 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG0(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG0_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG0_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG1_MASK         (0x2U)
#define DMA_COMMON_SETTRIG_SETTRIG1_SHIFT        (1U)
/*! SETTRIG1 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG1(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG1_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG1_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG2_MASK         (0x4U)
#define DMA_COMMON_SETTRIG_SETTRIG2_SHIFT        (2U)
/*! SETTRIG2 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG2(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG2_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG2_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG3_MASK         (0x8U)
#define DMA_COMMON_SETTRIG_SETTRIG3_SHIFT        (3U)
/*! SETTRIG3 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG3(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG3_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG3_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG4_MASK         (0x10U)
#define DMA_COMMON_SETTRIG_SETTRIG4_SHIFT        (4U)
/*! SETTRIG4 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG4(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG4_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG4_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG5_MASK         (0x20U)
#define DMA_COMMON_SETTRIG_SETTRIG5_SHIFT        (5U)
/*! SETTRIG5 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG5(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG5_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG5_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG6_MASK         (0x40U)
#define DMA_COMMON_SETTRIG_SETTRIG6_SHIFT        (6U)
/*! SETTRIG6 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG6(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG6_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG6_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG7_MASK         (0x80U)
#define DMA_COMMON_SETTRIG_SETTRIG7_SHIFT        (7U)
/*! SETTRIG7 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG7(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG7_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG7_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG8_MASK         (0x100U)
#define DMA_COMMON_SETTRIG_SETTRIG8_SHIFT        (8U)
/*! SETTRIG8 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG8(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG8_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG8_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG9_MASK         (0x200U)
#define DMA_COMMON_SETTRIG_SETTRIG9_SHIFT        (9U)
/*! SETTRIG9 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG9(x)           (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG9_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG9_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG10_MASK        (0x400U)
#define DMA_COMMON_SETTRIG_SETTRIG10_SHIFT       (10U)
/*! SETTRIG10 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG10(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG10_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG10_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG11_MASK        (0x800U)
#define DMA_COMMON_SETTRIG_SETTRIG11_SHIFT       (11U)
/*! SETTRIG11 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG11(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG11_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG11_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG12_MASK        (0x1000U)
#define DMA_COMMON_SETTRIG_SETTRIG12_SHIFT       (12U)
/*! SETTRIG12 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG12(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG12_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG12_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG13_MASK        (0x2000U)
#define DMA_COMMON_SETTRIG_SETTRIG13_SHIFT       (13U)
/*! SETTRIG13 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG13(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG13_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG13_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG14_MASK        (0x4000U)
#define DMA_COMMON_SETTRIG_SETTRIG14_SHIFT       (14U)
/*! SETTRIG14 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG14(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG14_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG14_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG15_MASK        (0x8000U)
#define DMA_COMMON_SETTRIG_SETTRIG15_SHIFT       (15U)
/*! SETTRIG15 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG15(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG15_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG15_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG16_MASK        (0x10000U)
#define DMA_COMMON_SETTRIG_SETTRIG16_SHIFT       (16U)
/*! SETTRIG16 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG16(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG16_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG16_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG17_MASK        (0x20000U)
#define DMA_COMMON_SETTRIG_SETTRIG17_SHIFT       (17U)
/*! SETTRIG17 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG17(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG17_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG17_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG18_MASK        (0x40000U)
#define DMA_COMMON_SETTRIG_SETTRIG18_SHIFT       (18U)
/*! SETTRIG18 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG18(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG18_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG18_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG19_MASK        (0x80000U)
#define DMA_COMMON_SETTRIG_SETTRIG19_SHIFT       (19U)
/*! SETTRIG19 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG19(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG19_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG19_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG20_MASK        (0x100000U)
#define DMA_COMMON_SETTRIG_SETTRIG20_SHIFT       (20U)
/*! SETTRIG20 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG20(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG20_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG20_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG21_MASK        (0x200000U)
#define DMA_COMMON_SETTRIG_SETTRIG21_SHIFT       (21U)
/*! SETTRIG21 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG21(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG21_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG21_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG22_MASK        (0x400000U)
#define DMA_COMMON_SETTRIG_SETTRIG22_SHIFT       (22U)
/*! SETTRIG22 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG22(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG22_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG22_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG23_MASK        (0x800000U)
#define DMA_COMMON_SETTRIG_SETTRIG23_SHIFT       (23U)
/*! SETTRIG23 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG23(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG23_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG23_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG24_MASK        (0x1000000U)
#define DMA_COMMON_SETTRIG_SETTRIG24_SHIFT       (24U)
/*! SETTRIG24 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG24(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG24_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG24_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG25_MASK        (0x2000000U)
#define DMA_COMMON_SETTRIG_SETTRIG25_SHIFT       (25U)
/*! SETTRIG25 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG25(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG25_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG25_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG26_MASK        (0x4000000U)
#define DMA_COMMON_SETTRIG_SETTRIG26_SHIFT       (26U)
/*! SETTRIG26 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG26(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG26_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG26_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG27_MASK        (0x8000000U)
#define DMA_COMMON_SETTRIG_SETTRIG27_SHIFT       (27U)
/*! SETTRIG27 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG27(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG27_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG27_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG28_MASK        (0x10000000U)
#define DMA_COMMON_SETTRIG_SETTRIG28_SHIFT       (28U)
/*! SETTRIG28 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG28(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG28_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG28_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG29_MASK        (0x20000000U)
#define DMA_COMMON_SETTRIG_SETTRIG29_SHIFT       (29U)
/*! SETTRIG29 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG29(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG29_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG29_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG30_MASK        (0x40000000U)
#define DMA_COMMON_SETTRIG_SETTRIG30_SHIFT       (30U)
/*! SETTRIG30 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG30(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG30_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG30_MASK)
#define DMA_COMMON_SETTRIG_SETTRIG31_MASK        (0x80000000U)
#define DMA_COMMON_SETTRIG_SETTRIG31_SHIFT       (31U)
/*! SETTRIG31 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG_SETTRIG31(x)          (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_SETTRIG31_SHIFT)) & DMA_COMMON_SETTRIG_SETTRIG31_MASK)
/*! @} */

/* The count of DMA_COMMON_SETTRIG */
#define DMA_COMMON_SETTRIG_COUNT                 (1U)

/*! @name COMMON_SETTRIG1 - Set Trigger control bits for all DMA channels */
/*! @{ */
#define DMA_COMMON_SETTRIG1_SETTRIG32_MASK       (0x1U)
#define DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT      (0U)
/*! SETTRIG32 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG32(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG32_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG32_MASK)
#define DMA_COMMON_SETTRIG1_SETTRIG33_MASK       (0x2U)
#define DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT      (1U)
/*! SETTRIG33 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG33(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG33_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG33_MASK)
#define DMA_COMMON_SETTRIG1_SETTRIG34_MASK       (0x4U)
#define DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT      (2U)
/*! SETTRIG34 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG34(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG34_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG34_MASK)
#define DMA_COMMON_SETTRIG1_SETTRIG35_MASK       (0x8U)
#define DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT      (3U)
/*! SETTRIG35 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG35(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG35_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG35_MASK)
#define DMA_COMMON_SETTRIG1_SETTRIG36_MASK       (0x10U)
#define DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT      (4U)
/*! SETTRIG36 - Set Trigger control bit for DMA channel.
 *  0b0..No effect.
 *  0b1..Sets the Trig bit for DMA channel.
 */
#define DMA_COMMON_SETTRIG1_SETTRIG36(x)         (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG1_SETTRIG36_SHIFT)) & DMA_COMMON_SETTRIG1_SETTRIG36_MASK)
/*! @} */

/* The count of DMA_COMMON_SETTRIG1 */
#define DMA_COMMON_SETTRIG1_COUNT                (1U)

/*! @name COMMON_ABORT - Channel Abort control for all DMA channels */
/*! @{ */
#define DMA_COMMON_ABORT_ABORT0_MASK             (0x1U)
#define DMA_COMMON_ABORT_ABORT0_SHIFT            (0U)
/*! ABORT0 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT0(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT0_SHIFT)) & DMA_COMMON_ABORT_ABORT0_MASK)
#define DMA_COMMON_ABORT_ABORT1_MASK             (0x2U)
#define DMA_COMMON_ABORT_ABORT1_SHIFT            (1U)
/*! ABORT1 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT1(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT1_SHIFT)) & DMA_COMMON_ABORT_ABORT1_MASK)
#define DMA_COMMON_ABORT_ABORT2_MASK             (0x4U)
#define DMA_COMMON_ABORT_ABORT2_SHIFT            (2U)
/*! ABORT2 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT2(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT2_SHIFT)) & DMA_COMMON_ABORT_ABORT2_MASK)
#define DMA_COMMON_ABORT_ABORT3_MASK             (0x8U)
#define DMA_COMMON_ABORT_ABORT3_SHIFT            (3U)
/*! ABORT3 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT3(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT3_SHIFT)) & DMA_COMMON_ABORT_ABORT3_MASK)
#define DMA_COMMON_ABORT_ABORT4_MASK             (0x10U)
#define DMA_COMMON_ABORT_ABORT4_SHIFT            (4U)
/*! ABORT4 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT4(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT4_SHIFT)) & DMA_COMMON_ABORT_ABORT4_MASK)
#define DMA_COMMON_ABORT_ABORT5_MASK             (0x20U)
#define DMA_COMMON_ABORT_ABORT5_SHIFT            (5U)
/*! ABORT5 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT5(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT5_SHIFT)) & DMA_COMMON_ABORT_ABORT5_MASK)
#define DMA_COMMON_ABORT_ABORT6_MASK             (0x40U)
#define DMA_COMMON_ABORT_ABORT6_SHIFT            (6U)
/*! ABORT6 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT6(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT6_SHIFT)) & DMA_COMMON_ABORT_ABORT6_MASK)
#define DMA_COMMON_ABORT_ABORT7_MASK             (0x80U)
#define DMA_COMMON_ABORT_ABORT7_SHIFT            (7U)
/*! ABORT7 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT7(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT7_SHIFT)) & DMA_COMMON_ABORT_ABORT7_MASK)
#define DMA_COMMON_ABORT_ABORT8_MASK             (0x100U)
#define DMA_COMMON_ABORT_ABORT8_SHIFT            (8U)
/*! ABORT8 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT8(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT8_SHIFT)) & DMA_COMMON_ABORT_ABORT8_MASK)
#define DMA_COMMON_ABORT_ABORT9_MASK             (0x200U)
#define DMA_COMMON_ABORT_ABORT9_SHIFT            (9U)
/*! ABORT9 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT9(x)               (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT9_SHIFT)) & DMA_COMMON_ABORT_ABORT9_MASK)
#define DMA_COMMON_ABORT_ABORT10_MASK            (0x400U)
#define DMA_COMMON_ABORT_ABORT10_SHIFT           (10U)
/*! ABORT10 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT10(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT10_SHIFT)) & DMA_COMMON_ABORT_ABORT10_MASK)
#define DMA_COMMON_ABORT_ABORT11_MASK            (0x800U)
#define DMA_COMMON_ABORT_ABORT11_SHIFT           (11U)
/*! ABORT11 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT11(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT11_SHIFT)) & DMA_COMMON_ABORT_ABORT11_MASK)
#define DMA_COMMON_ABORT_ABORT12_MASK            (0x1000U)
#define DMA_COMMON_ABORT_ABORT12_SHIFT           (12U)
/*! ABORT12 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT12(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT12_SHIFT)) & DMA_COMMON_ABORT_ABORT12_MASK)
#define DMA_COMMON_ABORT_ABORT13_MASK            (0x2000U)
#define DMA_COMMON_ABORT_ABORT13_SHIFT           (13U)
/*! ABORT13 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT13(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT13_SHIFT)) & DMA_COMMON_ABORT_ABORT13_MASK)
#define DMA_COMMON_ABORT_ABORT14_MASK            (0x4000U)
#define DMA_COMMON_ABORT_ABORT14_SHIFT           (14U)
/*! ABORT14 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT14(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT14_SHIFT)) & DMA_COMMON_ABORT_ABORT14_MASK)
#define DMA_COMMON_ABORT_ABORT15_MASK            (0x8000U)
#define DMA_COMMON_ABORT_ABORT15_SHIFT           (15U)
/*! ABORT15 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT15(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT15_SHIFT)) & DMA_COMMON_ABORT_ABORT15_MASK)
#define DMA_COMMON_ABORT_ABORT16_MASK            (0x10000U)
#define DMA_COMMON_ABORT_ABORT16_SHIFT           (16U)
/*! ABORT16 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT16(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT16_SHIFT)) & DMA_COMMON_ABORT_ABORT16_MASK)
#define DMA_COMMON_ABORT_ABORT17_MASK            (0x20000U)
#define DMA_COMMON_ABORT_ABORT17_SHIFT           (17U)
/*! ABORT17 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT17(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT17_SHIFT)) & DMA_COMMON_ABORT_ABORT17_MASK)
#define DMA_COMMON_ABORT_ABORT18_MASK            (0x40000U)
#define DMA_COMMON_ABORT_ABORT18_SHIFT           (18U)
/*! ABORT18 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT18(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT18_SHIFT)) & DMA_COMMON_ABORT_ABORT18_MASK)
#define DMA_COMMON_ABORT_ABORT19_MASK            (0x80000U)
#define DMA_COMMON_ABORT_ABORT19_SHIFT           (19U)
/*! ABORT19 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT19(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT19_SHIFT)) & DMA_COMMON_ABORT_ABORT19_MASK)
#define DMA_COMMON_ABORT_ABORT20_MASK            (0x100000U)
#define DMA_COMMON_ABORT_ABORT20_SHIFT           (20U)
/*! ABORT20 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT20(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT20_SHIFT)) & DMA_COMMON_ABORT_ABORT20_MASK)
#define DMA_COMMON_ABORT_ABORT21_MASK            (0x200000U)
#define DMA_COMMON_ABORT_ABORT21_SHIFT           (21U)
/*! ABORT21 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT21(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT21_SHIFT)) & DMA_COMMON_ABORT_ABORT21_MASK)
#define DMA_COMMON_ABORT_ABORT22_MASK            (0x400000U)
#define DMA_COMMON_ABORT_ABORT22_SHIFT           (22U)
/*! ABORT22 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT22(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT22_SHIFT)) & DMA_COMMON_ABORT_ABORT22_MASK)
#define DMA_COMMON_ABORT_ABORT23_MASK            (0x800000U)
#define DMA_COMMON_ABORT_ABORT23_SHIFT           (23U)
/*! ABORT23 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT23(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT23_SHIFT)) & DMA_COMMON_ABORT_ABORT23_MASK)
#define DMA_COMMON_ABORT_ABORT24_MASK            (0x1000000U)
#define DMA_COMMON_ABORT_ABORT24_SHIFT           (24U)
/*! ABORT24 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT24(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT24_SHIFT)) & DMA_COMMON_ABORT_ABORT24_MASK)
#define DMA_COMMON_ABORT_ABORT25_MASK            (0x2000000U)
#define DMA_COMMON_ABORT_ABORT25_SHIFT           (25U)
/*! ABORT25 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT25(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT25_SHIFT)) & DMA_COMMON_ABORT_ABORT25_MASK)
#define DMA_COMMON_ABORT_ABORT26_MASK            (0x4000000U)
#define DMA_COMMON_ABORT_ABORT26_SHIFT           (26U)
/*! ABORT26 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT26(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT26_SHIFT)) & DMA_COMMON_ABORT_ABORT26_MASK)
#define DMA_COMMON_ABORT_ABORT27_MASK            (0x8000000U)
#define DMA_COMMON_ABORT_ABORT27_SHIFT           (27U)
/*! ABORT27 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT27(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT27_SHIFT)) & DMA_COMMON_ABORT_ABORT27_MASK)
#define DMA_COMMON_ABORT_ABORT28_MASK            (0x10000000U)
#define DMA_COMMON_ABORT_ABORT28_SHIFT           (28U)
/*! ABORT28 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT28(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT28_SHIFT)) & DMA_COMMON_ABORT_ABORT28_MASK)
#define DMA_COMMON_ABORT_ABORT29_MASK            (0x20000000U)
#define DMA_COMMON_ABORT_ABORT29_SHIFT           (29U)
/*! ABORT29 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT29(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT29_SHIFT)) & DMA_COMMON_ABORT_ABORT29_MASK)
#define DMA_COMMON_ABORT_ABORT30_MASK            (0x40000000U)
#define DMA_COMMON_ABORT_ABORT30_SHIFT           (30U)
/*! ABORT30 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT30(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT30_SHIFT)) & DMA_COMMON_ABORT_ABORT30_MASK)
#define DMA_COMMON_ABORT_ABORT31_MASK            (0x80000000U)
#define DMA_COMMON_ABORT_ABORT31_SHIFT           (31U)
/*! ABORT31 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT_ABORT31(x)              (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORT31_SHIFT)) & DMA_COMMON_ABORT_ABORT31_MASK)
/*! @} */

/* The count of DMA_COMMON_ABORT */
#define DMA_COMMON_ABORT_COUNT                   (1U)

/*! @name COMMON_ABORT1 - Channel Abort control for all DMA channels */
/*! @{ */
#define DMA_COMMON_ABORT1_ABORT32_MASK           (0x1U)
#define DMA_COMMON_ABORT1_ABORT32_SHIFT          (0U)
/*! ABORT32 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT32(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT32_SHIFT)) & DMA_COMMON_ABORT1_ABORT32_MASK)
#define DMA_COMMON_ABORT1_ABORT33_MASK           (0x2U)
#define DMA_COMMON_ABORT1_ABORT33_SHIFT          (1U)
/*! ABORT33 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT33(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT33_SHIFT)) & DMA_COMMON_ABORT1_ABORT33_MASK)
#define DMA_COMMON_ABORT1_ABORT34_MASK           (0x4U)
#define DMA_COMMON_ABORT1_ABORT34_SHIFT          (2U)
/*! ABORT34 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT34(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT34_SHIFT)) & DMA_COMMON_ABORT1_ABORT34_MASK)
#define DMA_COMMON_ABORT1_ABORT35_MASK           (0x8U)
#define DMA_COMMON_ABORT1_ABORT35_SHIFT          (3U)
/*! ABORT35 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT35(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT35_SHIFT)) & DMA_COMMON_ABORT1_ABORT35_MASK)
#define DMA_COMMON_ABORT1_ABORT36_MASK           (0x10U)
#define DMA_COMMON_ABORT1_ABORT36_SHIFT          (4U)
/*! ABORT36 - Abort control for DMA channel.
 *  0b0..No effect.
 *  0b1..Aborts DMA operations on channel.
 */
#define DMA_COMMON_ABORT1_ABORT36(x)             (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT1_ABORT36_SHIFT)) & DMA_COMMON_ABORT1_ABORT36_MASK)
/*! @} */

/* The count of DMA_COMMON_ABORT1 */
#define DMA_COMMON_ABORT1_COUNT                  (1U)

/*! @name CHANNEL_CFG - Configuration register for DMA channel */
/*! @{ */
#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK         (0x1U)
#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT        (0U)
/*! PERIPHREQEN - Peripheral request Enable.
 *  0b0..Peripheral DMA requests disabled.
 *  0b1..Peripheral DMA requests enabled.
 */
#define DMA_CHANNEL_CFG_PERIPHREQEN(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
#define DMA_CHANNEL_CFG_HWTRIGEN_MASK            (0x2U)
#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT           (1U)
/*! HWTRIGEN - Hardware Triggering Enable for channel.
 *  0b0..Hardware triggering not used for channel.
 *  0b1..Hardware triggering used for channel.
 */
#define DMA_CHANNEL_CFG_HWTRIGEN(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
#define DMA_CHANNEL_CFG_TRIGPOL_MASK             (0x10U)
#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT            (4U)
/*! TRIGPOL - Trigger Polarity.
 *  0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
 *  0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
 */
#define DMA_CHANNEL_CFG_TRIGPOL(x)               (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
#define DMA_CHANNEL_CFG_TRIGTYPE_MASK            (0x20U)
#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT           (5U)
/*! TRIGTYPE - Trigger Type.
 *  0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
 *  0b1..Level.
 */
#define DMA_CHANNEL_CFG_TRIGTYPE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
#define DMA_CHANNEL_CFG_TRIGBURST_MASK           (0x40U)
#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT          (6U)
/*! TRIGBURST - Trigger Burst.
 *  0b0..Single transfer.
 *  0b1..Burst transfer.
 */
#define DMA_CHANNEL_CFG_TRIGBURST(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
#define DMA_CHANNEL_CFG_BURSTPOWER_MASK          (0xF00U)
#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT         (8U)
/*! BURSTPOWER - Burst Power.
 */
#define DMA_CHANNEL_CFG_BURSTPOWER(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK        (0x4000U)
#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT       (14U)
/*! SRCBURSTWRAP - Source Burst Wrap.
 *  0b0..Disabled.
 *  0b1..Enabled.
 */
#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK        (0x8000U)
#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT       (15U)
/*! DSTBURSTWRAP - Destination Burst Wrap.
 *  0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
 *  0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
 */
#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
#define DMA_CHANNEL_CFG_CHPRIORITY_MASK          (0x70000U)
#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT         (16U)
/*! CHPRIORITY - Priority of channel when multiple DMA requests are pending.
 */
#define DMA_CHANNEL_CFG_CHPRIORITY(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
/*! @} */

/* The count of DMA_CHANNEL_CFG */
#define DMA_CHANNEL_CFG_COUNT                    (37U)

/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel */
/*! @{ */
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK    (0x1U)
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT   (0U)
/*! VALIDPENDING - Valid pending flag for this channel.
 *  0b0..No effect on DMA operation.
 *  0b1..Valid pending.
 */
#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x)      (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
#define DMA_CHANNEL_CTLSTAT_TRIG_MASK            (0x4U)
#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT           (2U)
/*! TRIG - Trigger flag.
 *  0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
 *  0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
 */
#define DMA_CHANNEL_CTLSTAT_TRIG(x)              (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
/*! @} */

/* The count of DMA_CHANNEL_CTLSTAT */
#define DMA_CHANNEL_CTLSTAT_COUNT                (37U)

/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel */
/*! @{ */
#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK        (0x1U)
#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT       (0U)
/*! CFGVALID - Configuration Valid flag.
 *  0b0..Not valid.
 *  0b1..Valid.
 */
#define DMA_CHANNEL_XFERCFG_CFGVALID(x)          (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
#define DMA_CHANNEL_XFERCFG_RELOAD_MASK          (0x2U)
#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT         (1U)
/*! RELOAD - Reload.
 *  0b0..Disabled. The channels' control structure should not be reloaded when the current descriptor is exhausted.
 *  0b1..Enabled. The channels' control structure should be reloaded when the current descriptor is exhausted.
 */
#define DMA_CHANNEL_XFERCFG_RELOAD(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK          (0x4U)
#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT         (2U)
/*! SWTRIG - Software Trigger.
 *  0b0..Not set.
 *  0b1..Set.
 */
#define DMA_CHANNEL_XFERCFG_SWTRIG(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK         (0x8U)
#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT        (3U)
/*! CLRTRIG - Clear Trigger.
 *  0b0..Not cleared.
 *  0b1..Cleared.
 */
#define DMA_CHANNEL_XFERCFG_CLRTRIG(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
#define DMA_CHANNEL_XFERCFG_SETINTA_MASK         (0x10U)
#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT        (4U)
/*! SETINTA - Set Interrupt flag A for channel.
 *  0b0..No effect.
 *  0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
 */
#define DMA_CHANNEL_XFERCFG_SETINTA(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
#define DMA_CHANNEL_XFERCFG_SETINTB_MASK         (0x20U)
#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT        (5U)
/*! SETINTB - Set Interrupt flag B for channel.
 *  0b0..No effect.
 *  0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
 */
#define DMA_CHANNEL_XFERCFG_SETINTB(x)           (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
#define DMA_CHANNEL_XFERCFG_WIDTH_MASK           (0x300U)
#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT          (8U)
/*! WIDTH - Transfer width used for this DMA channel.
 *  0b00..8-bit.
 *  0b01..16-bit.
 *  0b10..32-bit.
 *  0b11..Reserved.
 */
#define DMA_CHANNEL_XFERCFG_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
#define DMA_CHANNEL_XFERCFG_SRCINC_MASK          (0x3000U)
#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT         (12U)
/*! SRCINC - Source address increment
 *  0b00..No increment.
 *  0b01..1 x width.
 *  0b10..2 x width.
 *  0b11..4 x width.
 */
#define DMA_CHANNEL_XFERCFG_SRCINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
#define DMA_CHANNEL_XFERCFG_DSTINC_MASK          (0xC000U)
#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT         (14U)
/*! DSTINC - Destination address increment
 *  0b00..No increment.
 *  0b01..1 x width.
 *  0b10..2 x width.
 *  0b11..4 x width.
 */
#define DMA_CHANNEL_XFERCFG_DSTINC(x)            (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK       (0x3FF0000U)
#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT      (16U)
/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded.
 */
#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
/*! @} */

/* The count of DMA_CHANNEL_XFERCFG */
#define DMA_CHANNEL_XFERCFG_COUNT                (37U)


/*!
 * @}
 */ /* end of group DMA_Register_Masks */


/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE                                (0x40104000u)
/** Peripheral DMA0 base pointer */
#define DMA0                                     ((DMA_Type *)DMA0_BASE)
/** Peripheral DMA1 base address */
#define DMA1_BASE                                (0x40105000u)
/** Peripheral DMA1 base pointer */
#define DMA1                                     ((DMA_Type *)DMA1_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS                           { DMA0_BASE, DMA1_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS                            { DMA0, DMA1 }
/** Interrupt vectors for the DMA peripheral type */
#define DMA_IRQS                                 { DMA0_IRQn, DMA1_IRQn }

/*!
 * @}
 */ /* end of group DMA_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- DMIC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
 * @{
 */

/** DMIC - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x100 */
    __IO uint32_t OSR;                               /**< Oversample Rate, array offset: 0x0, array step: 0x100 */
    __IO uint32_t DIVHFCLK;                          /**< DMIC Clock, array offset: 0x4, array step: 0x100 */
    __IO uint32_t PREAC2FSCOEF;                      /**< Compensation Filter for 2 FS, array offset: 0x8, array step: 0x100 */
    __IO uint32_t PREAC4FSCOEF;                      /**< Compensation Filter for 4 FS, array offset: 0xC, array step: 0x100 */
    __IO uint32_t GAINSHIFT;                         /**< Decimator Gain Shift, array offset: 0x10, array step: 0x100 */
         uint8_t RESERVED_0[108];
    __IO uint32_t FIFO_CTRL;                         /**< FIFO Control, array offset: 0x80, array step: 0x100 */
    __IO uint32_t FIFO_STATUS;                       /**< FIFO Status, array offset: 0x84, array step: 0x100 */
    __I  uint32_t FIFO_DATA;                         /**< FIFO Data, array offset: 0x88, array step: 0x100 */
    __IO uint32_t PHY_CTRL;                          /**< Physical Control, array offset: 0x8C, array step: 0x100 */
    __IO uint32_t DC_CTRL;                           /**< DC Filter Control, array offset: 0x90, array step: 0x100 */
         uint8_t RESERVED_1[108];
  } CHANNEL[8];
       uint8_t RESERVED_0[1792];
  __IO uint32_t CHANEN;                            /**< Channel Enable, offset: 0xF00 */
       uint8_t RESERVED_1[12];
  __IO uint32_t USE2FS;                            /**< Use 2 FS register, offset: 0xF10 */
       uint8_t RESERVED_2[108];
  __IO uint32_t HWVADGAIN;                         /**< HWVAD Input Gain, offset: 0xF80 */
  __IO uint32_t HWVADHPFS;                         /**< HWVAD Filter Control, offset: 0xF84 */
  __IO uint32_t HWVADST10;                         /**< HWVAD Control, offset: 0xF88 */
  __IO uint32_t HWVADRSTT;                         /**< HWVAD Filter Reset, offset: 0xF8C */
  __IO uint32_t HWVADTHGN;                         /**< HWVAD Noise Estimator Gain, offset: 0xF90 */
  __IO uint32_t HWVADTHGS;                         /**< HWVAD Signal Estimator Gain, offset: 0xF94 */
  __I  uint32_t HWVADLOWZ;                         /**< HWVAD Noise Envelope Estimator, offset: 0xF98 */
} DMIC_Type;

/* ----------------------------------------------------------------------------
   -- DMIC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup DMIC_Register_Masks DMIC Register Masks
 * @{
 */

/*! @name CHANNEL_OSR - Oversample Rate */
/*! @{ */
#define DMIC_CHANNEL_OSR_OSR_MASK                (0xFFU)
#define DMIC_CHANNEL_OSR_OSR_SHIFT               (0U)
/*! OSR - Oversample Rate
 */
#define DMIC_CHANNEL_OSR_OSR(x)                  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_OSR */
#define DMIC_CHANNEL_OSR_COUNT                   (8U)

/*! @name CHANNEL_DIVHFCLK - DMIC Clock */
/*! @{ */
#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK        (0xFU)
#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT       (0U)
/*! PDMDIV - PDM Clock Divider Value
 *  0b0000..Divide by 1
 *  0b0001..Divide by 2
 *  0b0010..Divide by 3
 *  0b0011..Divide by 4
 *  0b0100..Divide by 6
 *  0b0101..Divide by 8
 *  0b0110..Divide by 12
 *  0b0111..Divide by 16
 *  0b1000..Divide by 24
 *  0b1001..Divide by 32
 *  0b1010..Divide by 48
 *  0b1011..Divide by 64
 *  0b1100..Divide by 96
 *  0b1101..Divide by 128
 *  0b1110-0b1111..Reserved
 */
#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_DIVHFCLK */
#define DMIC_CHANNEL_DIVHFCLK_COUNT              (8U)

/*! @name CHANNEL_PREAC2FSCOEF - Compensation Filter for 2 FS */
/*! @{ */
#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK      (0x3U)
#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT     (0U)
/*! COMP - Compensation value
 *  0b00..Compensation = 0. This is the recommended setting.
 *  0b01..Compensation = -0.16
 *  0b10..Compensation = -0.15
 *  0b11..Compensation = -0.13
 */
#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT          (8U)

/*! @name CHANNEL_PREAC4FSCOEF - Compensation Filter for 4 FS */
/*! @{ */
#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK      (0x3U)
#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT     (0U)
/*! COMP - Compensation value
 *  0b00..Compensation = 0. This is the recommended setting.
 *  0b01..Compensation = -0.16
 *  0b10..Compensation = -0.15
 *  0b11..Compensation = -0.13
 */
#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT          (8U)

/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift */
/*! @{ */
#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK         (0x3FU)
#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT        (0U)
/*! GAIN - Gain
 */
#define DMIC_CHANNEL_GAINSHIFT_GAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_GAINSHIFT */
#define DMIC_CHANNEL_GAINSHIFT_COUNT             (8U)

/*! @name CHANNEL_FIFO_CTRL - FIFO Control */
/*! @{ */
#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK       (0x1U)
#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT      (0U)
/*! ENABLE - FIFO Enable.
 *  0b0..FIFO is not enabled. Enabling a DMIC channel with the FIFO disabled could be useful while data is being
 *       streamed to the I2S, or in order to avoid a filter settling delay when a channel is re-enabled after a
 *       period when the data was not needed.
 *  0b1..FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data from the DMIC via the FIFODATA register.
 */
#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK       (0x2U)
#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT      (1U)
/*! RESETN - FIFO Reset
 *  0b0..Reset the FIFO. This must be cleared before resuming operation.
 *  0b1..Normal operation
 */
#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x)         (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK        (0x4U)
#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT       (2U)
/*! INTEN - Interrupt Enable.
 *  0b0..FIFO level interrupts are not enabled.
 *  0b1..FIFO level interrupts are enabled.
 */
#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK        (0x8U)
#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT       (3U)
/*! DMAEN - DMA Enable
 *  0b0..DMA requests are not enabled.
 *  0b1..DMA requests based on FIFO level are enabled.
 */
#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK      (0x1F0000U)
#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT     (16U)
/*! TRIGLVL - FIFO Trigger Level for Interrupt
 *  0b00000..Trigger when the FIFO has received one entry (is no longer empty).
 *  0b00001..Trigger when the FIFO has received two entries.
 *  0b01110..Trigger when the FIFO has received 15 entries.
 *  0b01111..Trigger when the FIFO has received 16 entries (has become full).
 */
#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_FIFO_CTRL */
#define DMIC_CHANNEL_FIFO_CTRL_COUNT             (8U)

/*! @name CHANNEL_FIFO_STATUS - FIFO Status */
/*! @{ */
#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK        (0x1U)
#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT       (0U)
/*! INT - Status of Interrupt (write 1 to clear)
 */
#define DMIC_CHANNEL_FIFO_STATUS_INT(x)          (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK    (0x2U)
#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT   (1U)
/*! OVERRUN - Overrun Detected (write 1 to clear)
 */
#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x)      (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK   (0x4U)
#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT  (2U)
/*! UNDERRUN - Underrun Detected (write 1 to clear)
 */
#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x)     (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_FIFO_STATUS */
#define DMIC_CHANNEL_FIFO_STATUS_COUNT           (8U)

/*! @name CHANNEL_FIFO_DATA - FIFO Data */
/*! @{ */
#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK         (0xFFFFFFU)
#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT        (0U)
/*! DATA - PCM Data
 */
#define DMIC_CHANNEL_FIFO_DATA_DATA(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_FIFO_DATA */
#define DMIC_CHANNEL_FIFO_DATA_COUNT             (8U)

/*! @name CHANNEL_PHY_CTRL - Physical Control */
/*! @{ */
#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK      (0x1U)
#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT     (0U)
/*! PHY_FALL - Capture DMIC on Falling edge (0 means on rising)
 *  0b0..Capture PDM_DATA on the rising edge of PDM_CLK.
 *  0b1..Capture PDM_DATA on the falling edge of PDM_CLK.
 */
#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK      (0x2U)
#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT     (1U)
/*! PHY_HALF - Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)
 *  0b0..Standard half rate sampling. The clock to the DMIC is sent at the same rate as the decimator is providing.
 *  0b1..Use half rate sampling. The clock to the DMIC is sent at half the rate that the decimator is providing.
 */
#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x)        (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_PHY_CTRL */
#define DMIC_CHANNEL_PHY_CTRL_COUNT              (8U)

/*! @name CHANNEL_DC_CTRL - DC Filter Control */
/*! @{ */
#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK         (0x3U)
#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT        (0U)
/*! DCPOLE - DC Block Filter
 *  0b00..Flat Response, no filter
 *  0b01..155 Hz
 *  0b10..78 Hz
 *  0b11..39 Hz
 */
#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK         (0xF0U)
#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT        (4U)
/*! DCGAIN - DC Gain
 */
#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x)           (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
/*! SATURATEAT16BIT - Saturate at 16 Bit
 *  0b0..Do not Saturate. Results roll over if out range and do not saturate.
 *  0b1..Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0x8000 for negative overflow.
 */
#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x)  (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK     (0x200U)
#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT    (9U)
/*! SIGNEXTEND - Sign Extend
 *  0b0..The top byte of the FIFODATA register is always 0.
 *  0b1..The top byte of the FIFODATA register is sign extended.
 */
#define DMIC_CHANNEL_DC_CTRL_SIGNEXTEND(x)       (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SIGNEXTEND_MASK)
/*! @} */

/* The count of DMIC_CHANNEL_DC_CTRL */
#define DMIC_CHANNEL_DC_CTRL_COUNT               (8U)

/*! @name CHANEN - Channel Enable */
/*! @{ */
#define DMIC_CHANEN_EN_CH0_MASK                  (0x1U)
#define DMIC_CHANEN_EN_CH0_SHIFT                 (0U)
/*! EN_CH0 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH0(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
#define DMIC_CHANEN_EN_CH1_MASK                  (0x2U)
#define DMIC_CHANEN_EN_CH1_SHIFT                 (1U)
/*! EN_CH1 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH1(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
#define DMIC_CHANEN_EN_CH2_MASK                  (0x4U)
#define DMIC_CHANEN_EN_CH2_SHIFT                 (2U)
/*! EN_CH2 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH2(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH2_SHIFT)) & DMIC_CHANEN_EN_CH2_MASK)
#define DMIC_CHANEN_EN_CH3_MASK                  (0x8U)
#define DMIC_CHANEN_EN_CH3_SHIFT                 (3U)
/*! EN_CH3 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH3(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH3_SHIFT)) & DMIC_CHANEN_EN_CH3_MASK)
#define DMIC_CHANEN_EN_CH4_MASK                  (0x10U)
#define DMIC_CHANEN_EN_CH4_SHIFT                 (4U)
/*! EN_CH4 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH4(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH4_SHIFT)) & DMIC_CHANEN_EN_CH4_MASK)
#define DMIC_CHANEN_EN_CH5_MASK                  (0x20U)
#define DMIC_CHANEN_EN_CH5_SHIFT                 (5U)
/*! EN_CH5 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH5(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH5_SHIFT)) & DMIC_CHANEN_EN_CH5_MASK)
#define DMIC_CHANEN_EN_CH6_MASK                  (0x40U)
#define DMIC_CHANEN_EN_CH6_SHIFT                 (6U)
/*! EN_CH6 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH6(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH6_SHIFT)) & DMIC_CHANEN_EN_CH6_MASK)
#define DMIC_CHANEN_EN_CH7_MASK                  (0x80U)
#define DMIC_CHANEN_EN_CH7_SHIFT                 (7U)
/*! EN_CH7 - Enable Channel n
 *  0b0..PDM channel n is disabled.
 *  0b1..PDM channel n is enabled.
 */
#define DMIC_CHANEN_EN_CH7(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH7_SHIFT)) & DMIC_CHANEN_EN_CH7_MASK)
/*! @} */

/*! @name USE2FS - Use 2 FS register */
/*! @{ */
#define DMIC_USE2FS_USE2FS_MASK                  (0x1U)
#define DMIC_USE2FS_USE2FS_SHIFT                 (0U)
/*! USE2FS - Use 2FS register
 *  0b0..Use 1 FS output for PCM data.
 *  0b1..Use 2 FS output for PCM data.
 */
#define DMIC_USE2FS_USE2FS(x)                    (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
/*! @} */

/*! @name HWVADGAIN - HWVAD Input Gain */
/*! @{ */
#define DMIC_HWVADGAIN_INPUTGAIN_MASK            (0xFU)
#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT           (0U)
/*! INPUTGAIN
 *  0b0000..-10 bits
 *  0b0001..-8 bits
 *  0b0010..-6 bits
 *  0b0011..-4 bits
 *  0b0100..-2 bits
 *  0b0101..0 bits (default)
 *  0b0110..+2 bits
 *  0b0111..+4 bits
 *  0b1000..+6 bits
 *  0b1001..+8 bits
 *  0b1010..+10 bits
 *  0b1011..+12 bits
 *  0b1100..+14 bits
 *  0b1101-0b1111..Reserved
 */
#define DMIC_HWVADGAIN_INPUTGAIN(x)              (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
/*! @} */

/*! @name HWVADHPFS - HWVAD Filter Control */
/*! @{ */
#define DMIC_HWVADHPFS_HPFS_MASK                 (0x3U)
#define DMIC_HWVADHPFS_HPFS_SHIFT                (0U)
/*! HPFS - The HPFS field chooses the High Pass filter in first part of HWVAD.
 *  0b00..BYPASS. First filter by-pass.
 *  0b01..HIGH_PASS_1750HZ. High pass filter with -3dB cut-off at 1750 Hz.
 *  0b10..HIGH_PASS_215HZ. High pass filter with -3dB cut-off at 215 Hz.
 *  0b11..Reserved
 */
#define DMIC_HWVADHPFS_HPFS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
/*! @} */

/*! @name HWVADST10 - HWVAD Control */
/*! @{ */
#define DMIC_HWVADST10_ST10_MASK                 (0x1U)
#define DMIC_HWVADST10_ST10_SHIFT                (0U)
/*! ST10 - STAGE 1
 *  0b0..Normal operation, waiting for HWVAD trigger event (stage 0).
 *  0b1..Reset internal interrupt flag by writing a '1' (stage 1) pulse.
 */
#define DMIC_HWVADST10_ST10(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
/*! @} */

/*! @name HWVADRSTT - HWVAD Filter Reset */
/*! @{ */
#define DMIC_HWVADRSTT_RSST_MASK                 (0x1U)
#define DMIC_HWVADRSTT_RSST_SHIFT                (0U)
/*! RSST - Reset HWVAD
 */
#define DMIC_HWVADRSTT_RSST(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSST_SHIFT)) & DMIC_HWVADRSTT_RSST_MASK)
/*! @} */

/*! @name HWVADTHGN - HWVAD Noise Estimator Gain */
/*! @{ */
#define DMIC_HWVADTHGN_THGN_MASK                 (0xFU)
#define DMIC_HWVADTHGN_THGN_SHIFT                (0U)
/*! THGN - Gain Factor for Noise Estimator
 */
#define DMIC_HWVADTHGN_THGN(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
/*! @} */

/*! @name HWVADTHGS - HWVAD Signal Estimator Gain */
/*! @{ */
#define DMIC_HWVADTHGS_THGS_MASK                 (0xFU)
#define DMIC_HWVADTHGS_THGS_SHIFT                (0U)
/*! THGS - Signal Gain Factor
 */
#define DMIC_HWVADTHGS_THGS(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
/*! @} */

/*! @name HWVADLOWZ - HWVAD Noise Envelope Estimator */
/*! @{ */
#define DMIC_HWVADLOWZ_LOWZ_MASK                 (0xFFFFU)
#define DMIC_HWVADLOWZ_LOWZ_SHIFT                (0U)
/*! LOWZ - Average Noise-floor Value
 */
#define DMIC_HWVADLOWZ_LOWZ(x)                   (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group DMIC_Register_Masks */


/* DMIC - Peripheral instance base addresses */
/** Peripheral DMIC0 base address */
#define DMIC0_BASE                               (0x40121000u)
/** Peripheral DMIC0 base pointer */
#define DMIC0                                    ((DMIC_Type *)DMIC0_BASE)
/** Array initializer of DMIC peripheral base addresses */
#define DMIC_BASE_ADDRS                          { DMIC0_BASE }
/** Array initializer of DMIC peripheral base pointers */
#define DMIC_BASE_PTRS                           { DMIC0 }
/** Interrupt vectors for the DMIC peripheral type */
#define DMIC_IRQS                                { DMIC0_IRQn }
#define DMIC_HWVAD_IRQS                          { HWVAD_IRQn }

/*!
 * @}
 */ /* end of group DMIC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXCOMM Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
 * @{
 */

/** FLEXCOMM - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4088];
  __IO uint32_t PSELID;                            /**< Peripheral Select and Flexcomm module ID, offset: 0xFF8 */
  __I  uint32_t PID;                               /**< Peripheral Identification, offset: 0xFFC */
} FLEXCOMM_Type;

/* ----------------------------------------------------------------------------
   -- FLEXCOMM Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
 * @{
 */

/*! @name PSELID - Peripheral Select and Flexcomm module ID */
/*! @{ */
#define FLEXCOMM_PSELID_PERSEL_MASK              (0x7U)
#define FLEXCOMM_PSELID_PERSEL_SHIFT             (0U)
/*! PERSEL - Peripheral Select
 *  0b000..No peripheral selected.
 *  0b001..USART function selected
 *  0b010..SPI function selected
 *  0b011..I2C function selected
 *  0b100..I2S transmit function selected
 *  0b101..I2S receive function selected
 *  0b110..Reserved
 *  0b111..Reserved
 */
#define FLEXCOMM_PSELID_PERSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
#define FLEXCOMM_PSELID_LOCK_MASK                (0x8U)
#define FLEXCOMM_PSELID_LOCK_SHIFT               (3U)
/*! LOCK - Lock the peripheral select.
 *  0b0..Peripheral select can be changed by software.
 *  0b1..Peripheral select is locked and cannot be changed until this Flexcomm module or the entire device is reset.
 */
#define FLEXCOMM_PSELID_LOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
#define FLEXCOMM_PSELID_USARTPRESENT_MASK        (0x10U)
#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT       (4U)
/*! USARTPRESENT - USART present indicator
 *  0b0..This Flexcomm module does not include the USART function.
 *  0b1..This Flexcomm module includes the USART function.
 */
#define FLEXCOMM_PSELID_USARTPRESENT(x)          (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
#define FLEXCOMM_PSELID_SPIPRESENT_MASK          (0x20U)
#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT         (5U)
/*! SPIPRESENT - SPI present indicator
 *  0b0..This Flexcomm module does not include the SPI function.
 *  0b1..This Flexcomm module includes the SPI function.
 */
#define FLEXCOMM_PSELID_SPIPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
#define FLEXCOMM_PSELID_I2CPRESENT_MASK          (0x40U)
#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT         (6U)
/*! I2CPRESENT
 *  0b0..This Flexcomm module does not include the I2C function.
 *  0b1..This Flexcomm module includes the I2C function.
 */
#define FLEXCOMM_PSELID_I2CPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
#define FLEXCOMM_PSELID_I2SPRESENT_MASK          (0x80U)
#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT         (7U)
/*! I2SPRESENT
 *  0b0..This Flexcomm module does not include the I2S function.
 *  0b1..This Flexcomm module includes the I2S function.
 */
#define FLEXCOMM_PSELID_I2SPRESENT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
#define FLEXCOMM_PSELID_ID_MASK                  (0xFFFFF000U)
#define FLEXCOMM_PSELID_ID_SHIFT                 (12U)
/*! ID - Flexcomm ID
 */
#define FLEXCOMM_PSELID_ID(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
/*! @} */

/*! @name PID - Peripheral Identification */
/*! @{ */
#define FLEXCOMM_PID_Minor_Rev_MASK              (0xF00U)
#define FLEXCOMM_PID_Minor_Rev_SHIFT             (8U)
/*! Minor_Rev - Minor revision of module implementation
 */
#define FLEXCOMM_PID_Minor_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
#define FLEXCOMM_PID_Major_Rev_MASK              (0xF000U)
#define FLEXCOMM_PID_Major_Rev_SHIFT             (12U)
/*! Major_Rev - Major revision of module implementation
 */
#define FLEXCOMM_PID_Major_Rev(x)                (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
#define FLEXCOMM_PID_ID_MASK                     (0xFFFF0000U)
#define FLEXCOMM_PID_ID_SHIFT                    (16U)
/*! ID - Module identifier for the selected function
 */
#define FLEXCOMM_PID_ID(x)                       (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FLEXCOMM_Register_Masks */


/* FLEXCOMM - Peripheral instance base addresses */
/** Peripheral FLEXCOMM0 base address */
#define FLEXCOMM0_BASE                           (0x40106000u)
/** Peripheral FLEXCOMM0 base pointer */
#define FLEXCOMM0                                ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
/** Peripheral FLEXCOMM1 base address */
#define FLEXCOMM1_BASE                           (0x40107000u)
/** Peripheral FLEXCOMM1 base pointer */
#define FLEXCOMM1                                ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
/** Peripheral FLEXCOMM2 base address */
#define FLEXCOMM2_BASE                           (0x40108000u)
/** Peripheral FLEXCOMM2 base pointer */
#define FLEXCOMM2                                ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
/** Peripheral FLEXCOMM3 base address */
#define FLEXCOMM3_BASE                           (0x40109000u)
/** Peripheral FLEXCOMM3 base pointer */
#define FLEXCOMM3                                ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
/** Peripheral FLEXCOMM4 base address */
#define FLEXCOMM4_BASE                           (0x40122000u)
/** Peripheral FLEXCOMM4 base pointer */
#define FLEXCOMM4                                ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
/** Peripheral FLEXCOMM5 base address */
#define FLEXCOMM5_BASE                           (0x40123000u)
/** Peripheral FLEXCOMM5 base pointer */
#define FLEXCOMM5                                ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
/** Peripheral FLEXCOMM6 base address */
#define FLEXCOMM6_BASE                           (0x40124000u)
/** Peripheral FLEXCOMM6 base pointer */
#define FLEXCOMM6                                ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
/** Peripheral FLEXCOMM7 base address */
#define FLEXCOMM7_BASE                           (0x40125000u)
/** Peripheral FLEXCOMM7 base pointer */
#define FLEXCOMM7                                ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
/** Peripheral FLEXCOMM8 base address */
#define FLEXCOMM8_BASE                           (0x40209000u)
/** Peripheral FLEXCOMM8 base pointer */
#define FLEXCOMM8                                ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
/** Peripheral FLEXCOMM9 base address */
#define FLEXCOMM9_BASE                           (0x4020A000u)
/** Peripheral FLEXCOMM9 base pointer */
#define FLEXCOMM9                                ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
/** Peripheral FLEXCOMM10 base address */
#define FLEXCOMM10_BASE                          (0x4020B000u)
/** Peripheral FLEXCOMM10 base pointer */
#define FLEXCOMM10                               ((FLEXCOMM_Type *)FLEXCOMM10_BASE)
/** Peripheral FLEXCOMM11 base address */
#define FLEXCOMM11_BASE                          (0x4020C000u)
/** Peripheral FLEXCOMM11 base pointer */
#define FLEXCOMM11                               ((FLEXCOMM_Type *)FLEXCOMM11_BASE)
/** Peripheral FLEXCOMM12 base address */
#define FLEXCOMM12_BASE                          (0x4020D000u)
/** Peripheral FLEXCOMM12 base pointer */
#define FLEXCOMM12                               ((FLEXCOMM_Type *)FLEXCOMM12_BASE)
/** Peripheral FLEXCOMM13 base address */
#define FLEXCOMM13_BASE                          (0x4020E000u)
/** Peripheral FLEXCOMM13 base pointer */
#define FLEXCOMM13                               ((FLEXCOMM_Type *)FLEXCOMM13_BASE)
/** Peripheral FLEXCOMM14 base address */
#define FLEXCOMM14_BASE                          (0x40126000u)
/** Peripheral FLEXCOMM14 base pointer */
#define FLEXCOMM14                               ((FLEXCOMM_Type *)FLEXCOMM14_BASE)
/** Peripheral FLEXCOMM15 base address */
#define FLEXCOMM15_BASE                          (0x40127000u)
/** Peripheral FLEXCOMM15 base pointer */
#define FLEXCOMM15                               ((FLEXCOMM_Type *)FLEXCOMM15_BASE)
/** Peripheral FLEXCOMM16 base address */
#define FLEXCOMM16_BASE                          (0x40128000u)
/** Peripheral FLEXCOMM16 base pointer */
#define FLEXCOMM16                               ((FLEXCOMM_Type *)FLEXCOMM16_BASE)
/** Array initializer of FLEXCOMM peripheral base addresses */
#define FLEXCOMM_BASE_ADDRS                      { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE, FLEXCOMM10_BASE, FLEXCOMM11_BASE, FLEXCOMM12_BASE, FLEXCOMM13_BASE, FLEXCOMM14_BASE, FLEXCOMM15_BASE, FLEXCOMM16_BASE }
/** Array initializer of FLEXCOMM peripheral base pointers */
#define FLEXCOMM_BASE_PTRS                       { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9, FLEXCOMM10, FLEXCOMM11, FLEXCOMM12, FLEXCOMM13, FLEXCOMM14, FLEXCOMM15, FLEXCOMM16 }
/** Interrupt vectors for the FLEXCOMM peripheral type */
#define FLEXCOMM_IRQS                            { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, FLEXCOMM14_IRQn, NotAvail_IRQn, FLEXCOMM16_IRQn }

/*!
 * @}
 */ /* end of group FLEXCOMM_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
 * @{
 */

/** FLEXIO - Register Layout Typedef */
typedef struct {
  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
  __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
  __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
  __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
  __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
  __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
       uint8_t RESERVED_0[4];
  __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
  __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
  __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
       uint8_t RESERVED_1[4];
  __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
       uint8_t RESERVED_2[4];
  __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
       uint8_t RESERVED_3[4];
  __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
       uint8_t RESERVED_4[4];
  __IO uint32_t TRGSTAT;                           /**< Trigger Status Register, offset: 0x48 */
  __IO uint32_t TRIGIEN;                           /**< External Trigger Interrupt Enable Register, offset: 0x4C */
  __IO uint32_t PINSTAT;                           /**< Pin Status Register, offset: 0x50 */
  __IO uint32_t PINIEN;                            /**< Pin Interrupt Enable Register, offset: 0x54 */
  __IO uint32_t PINREN;                            /**< Pin Rising Edge Enable Register, offset: 0x58 */
  __IO uint32_t PINFEN;                            /**< Pin Falling Edge Enable Register, offset: 0x5C */
  __IO uint32_t PINOUTD;                           /**< Pin Output Data Register, offset: 0x60 */
  __IO uint32_t PINOUTE;                           /**< Pin Output Enable Register, offset: 0x64 */
  __O  uint32_t PINOUTDIS;                         /**< Pin Output Disable Register, offset: 0x68 */
  __O  uint32_t PINOUTCLR;                         /**< Pin Output Clear Register, offset: 0x6C */
  __O  uint32_t PINOUTSET;                         /**< Pin Output Set Register, offset: 0x70 */
  __O  uint32_t PINOUTTOG;                         /**< Pin Output Toggle Register, offset: 0x74 */
       uint8_t RESERVED_5[8];
  __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_6[96];
  __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_7[224];
  __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_8[96];
  __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
       uint8_t RESERVED_9[96];
  __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_10[96];
  __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
       uint8_t RESERVED_11[96];
  __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_12[96];
  __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
       uint8_t RESERVED_13[96];
  __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_14[352];
  __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
       uint8_t RESERVED_15[96];
  __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
       uint8_t RESERVED_16[96];
  __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
       uint8_t RESERVED_17[96];
  __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
       uint8_t RESERVED_18[96];
  __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
} FLEXIO_Type;

/* ----------------------------------------------------------------------------
   -- FLEXIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
 * @{
 */

/*! @name VERID - Version ID Register */
/*! @{ */
#define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT               (0U)
/*! FEATURE - Feature Specification Number
 *  0b0000000000000000..Standard features implemented.
 *  0b0000000000000001..Supports state, logic and parallel modes.
 *  0b0000000000000010..Supports pin control registers.
 *  0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
 */
#define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT                 (16U)
/*! MINOR - Minor Version Number
 */
#define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
/*! MAJOR - Major Version Number
 */
#define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @} */

/*! @name PARAM - Parameter Register */
/*! @{ */
#define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
/*! SHIFTER - Shifter Number
 */
#define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
/*! TIMER - Timer Number
 */
#define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT                   (16U)
/*! PIN - Pin Number
 */
#define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
/*! TRIGGER - Trigger Number
 */
#define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @} */

/*! @name CTRL - FlexIO Control Register */
/*! @{ */
#define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
/*! FLEXEN - FlexIO Enable
 *  0b0..FlexIO module is disabled.
 *  0b1..FlexIO module is enabled.
 */
#define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
/*! SWRST - Software Reset
 *  0b0..Software reset is disabled
 *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
 */
#define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
/*! FASTACC - Fast Access
 *  0b0..Configures for normal register accesses to FlexIO
 *  0b1..Configures for fast register accesses to FlexIO
 */
#define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
/*! DBGE - Debug Enable
 *  0b0..FlexIO is disabled in debug modes.
 *  0b1..FlexIO is enabled in debug modes
 */
#define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
/*! DOZEN - Doze Enable
 *  0b0..FlexIO enabled in Doze modes.
 *  0b1..FlexIO disabled in Doze modes.
 */
#define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @} */

/*! @name PIN - Pin State Register */
/*! @{ */
#define FLEXIO_PIN_PDI_MASK                      (0xFFFFU)
#define FLEXIO_PIN_PDI_SHIFT                     (0U)
/*! PDI - Pin Data Input
 */
#define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @} */

/*! @name SHIFTSTAT - Shifter Status Register */
/*! @{ */
#define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
/*! SSF - Shifter Status Flag
 */
#define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @} */

/*! @name SHIFTERR - Shifter Error Register */
/*! @{ */
#define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
/*! SEF - Shifter Error Flags
 */
#define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @} */

/*! @name TIMSTAT - Timer Status Register */
/*! @{ */
#define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
/*! TSF - Timer Status Flags
 */
#define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @} */

/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
/*! @{ */
#define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
/*! SSIE - Shifter Status Interrupt Enable
 */
#define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @} */

/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
/*! @{ */
#define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
/*! SEIE - Shifter Error Interrupt Enable
 */
#define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @} */

/*! @name TIMIEN - Timer Interrupt Enable Register */
/*! @{ */
#define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
/*! TEIE - Timer Status Interrupt Enable
 */
#define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @} */

/*! @name SHIFTSDEN - Shifter Status DMA Enable */
/*! @{ */
#define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
/*! SSDE - Shifter Status DMA Enable
 */
#define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @} */

/*! @name TIMERSDEN - Timer Status DMA Enable */
/*! @{ */
#define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
#define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
/*! TSDE - Timer Status DMA Enable
 */
#define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
/*! @} */

/*! @name SHIFTSTATE - Shifter State Register */
/*! @{ */
#define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
/*! STATE - Current State Pointer
 */
#define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @} */

/*! @name TRGSTAT - Trigger Status Register */
/*! @{ */
#define FLEXIO_TRGSTAT_ETSF_MASK                 (0xFFFFU)
#define FLEXIO_TRGSTAT_ETSF_SHIFT                (0U)
/*! ETSF - External Trigger Status Flags
 */
#define FLEXIO_TRGSTAT_ETSF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK)
/*! @} */

/*! @name TRIGIEN - External Trigger Interrupt Enable Register */
/*! @{ */
#define FLEXIO_TRIGIEN_TRIE_MASK                 (0xFFFFU)
#define FLEXIO_TRIGIEN_TRIE_SHIFT                (0U)
/*! TRIE - External Trigger Interrupt Enable
 */
#define FLEXIO_TRIGIEN_TRIE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK)
/*! @} */

/*! @name PINSTAT - Pin Status Register */
/*! @{ */
#define FLEXIO_PINSTAT_PSF_MASK                  (0xFFFFU)
#define FLEXIO_PINSTAT_PSF_SHIFT                 (0U)
/*! PSF - Pin Status Flags
 */
#define FLEXIO_PINSTAT_PSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK)
/*! @} */

/*! @name PINIEN - Pin Interrupt Enable Register */
/*! @{ */
#define FLEXIO_PINIEN_PSIE_MASK                  (0xFFFFU)
#define FLEXIO_PINIEN_PSIE_SHIFT                 (0U)
/*! PSIE - Pin Status Interrupt Enable
 */
#define FLEXIO_PINIEN_PSIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK)
/*! @} */

/*! @name PINREN - Pin Rising Edge Enable Register */
/*! @{ */
#define FLEXIO_PINREN_PRE_MASK                   (0xFFFFU)
#define FLEXIO_PINREN_PRE_SHIFT                  (0U)
/*! PRE - Pin Rising Edge
 */
#define FLEXIO_PINREN_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK)
/*! @} */

/*! @name PINFEN - Pin Falling Edge Enable Register */
/*! @{ */
#define FLEXIO_PINFEN_PFE_MASK                   (0xFFFFU)
#define FLEXIO_PINFEN_PFE_SHIFT                  (0U)
/*! PFE - Pin Falling Edge
 */
#define FLEXIO_PINFEN_PFE(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK)
/*! @} */

/*! @name PINOUTD - Pin Output Data Register */
/*! @{ */
#define FLEXIO_PINOUTD_OUTD_MASK                 (0xFFFFU)
#define FLEXIO_PINOUTD_OUTD_SHIFT                (0U)
/*! OUTD - Output Data
 */
#define FLEXIO_PINOUTD_OUTD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK)
/*! @} */

/*! @name PINOUTE - Pin Output Enable Register */
/*! @{ */
#define FLEXIO_PINOUTE_OUTE_MASK                 (0xFFFFU)
#define FLEXIO_PINOUTE_OUTE_SHIFT                (0U)
/*! OUTE - Output Enable
 */
#define FLEXIO_PINOUTE_OUTE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK)
/*! @} */

/*! @name PINOUTDIS - Pin Output Disable Register */
/*! @{ */
#define FLEXIO_PINOUTDIS_OUTDIS_MASK             (0xFFFFU)
#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT            (0U)
/*! OUTDIS - Output Disable
 */
#define FLEXIO_PINOUTDIS_OUTDIS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK)
/*! @} */

/*! @name PINOUTCLR - Pin Output Clear Register */
/*! @{ */
#define FLEXIO_PINOUTCLR_OUTCLR_MASK             (0xFFFFU)
#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT            (0U)
/*! OUTCLR - Output Clear
 */
#define FLEXIO_PINOUTCLR_OUTCLR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK)
/*! @} */

/*! @name PINOUTSET - Pin Output Set Register */
/*! @{ */
#define FLEXIO_PINOUTSET_OUTSET_MASK             (0xFFFFU)
#define FLEXIO_PINOUTSET_OUTSET_SHIFT            (0U)
/*! OUTSET - Output Set
 */
#define FLEXIO_PINOUTSET_OUTSET(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK)
/*! @} */

/*! @name PINOUTTOG - Pin Output Toggle Register */
/*! @{ */
#define FLEXIO_PINOUTTOG_OUTTOG_MASK             (0xFFFFU)
#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT            (0U)
/*! OUTTOG - Output Toggle
 */
#define FLEXIO_PINOUTTOG_OUTTOG(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK)
/*! @} */

/*! @name SHIFTCTL - Shifter Control N Register */
/*! @{ */
#define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
/*! SMOD - Shifter Mode
 *  0b000..Disabled.
 *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
 *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
 *  0b011..Reserved.
 *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
 *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
 *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
 *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
 */
#define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
/*! PINPOL - Shifter Pin Polarity
 *  0b0..Pin is active high
 *  0b1..Pin is active low
 */
#define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define FLEXIO_SHIFTCTL_PINSEL_MASK              (0xF00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
/*! PINSEL - Shifter Pin Select
 */
#define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
#define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
/*! PINCFG - Shifter Pin Configuration
 *  0b00..Shifter pin output disabled
 *  0b01..Shifter pin open drain or bidirectional output enable
 *  0b10..Shifter pin bidirectional output data
 *  0b11..Shifter pin output
 */
#define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
/*! TIMPOL - Timer Polarity
 *  0b0..Shift on posedge of Shift clock
 *  0b1..Shift on negedge of Shift clock
 */
#define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
/*! TIMSEL - Timer Select
 */
#define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT                    (8U)

/*! @name SHIFTCFG - Shifter Configuration N Register */
/*! @{ */
#define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
/*! SSTART - Shifter Start bit
 *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
 *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
 *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
 *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
 */
#define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
/*! SSTOP - Shifter Stop bit
 *  0b00..Stop bit disabled for transmitter/receiver/match store
 *  0b01..Reserved for transmitter/receiver/match store
 *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
 *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
 */
#define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
/*! INSRC - Input Source
 *  0b0..Pin
 *  0b1..Shifter N+1 Output
 */
#define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
#define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
/*! LATST - Late Store
 *  0b0..Shift register will store the pre-shift register state.
 *  0b1..Shift register will store the post-shift register state.
 */
#define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
#define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0xF0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
/*! PWIDTH - Parallel Width
 */
#define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT                    (8U)

/*! @name SHIFTBUF - Shifter Buffer N Register */
/*! @{ */
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
/*! SHIFTBUF - Shift Buffer
 */
#define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT                    (8U)

/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
/*! SHIFTBUFBIS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)

/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
/*! SHIFTBUFBYS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)

/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
/*! SHIFTBUFBBS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)

/*! @name TIMCTL - Timer Control N Register */
/*! @{ */
#define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
/*! TIMOD - Timer Mode
 *  0b000..Timer Disabled.
 *  0b001..Dual 8-bit counters baud mode.
 *  0b010..Dual 8-bit counters PWM high mode.
 *  0b011..Single 16-bit counter mode.
 *  0b100..Single 16-bit counter disable mode.
 *  0b101..Dual 8-bit counters word mode.
 *  0b110..Dual 8-bit counters PWM low mode.
 *  0b111..Single 16-bit input capture mode.
 */
#define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
#define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
/*! ONETIM - Timer One Time Operation
 *  0b0..The timer enable event is generated as normal.
 *  0b1..The timer enable event is blocked unless timer status flag is clear.
 */
#define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
#define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
#define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
/*! PININS - Timer Pin Input Select
 *  0b0..Timer pin input and output are selected by PINSEL.
 *  0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
 */
#define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
#define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
/*! PINPOL - Timer Pin Polarity
 *  0b0..Pin is active high
 *  0b1..Pin is active low
 */
#define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define FLEXIO_TIMCTL_PINSEL_MASK                (0xF00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
/*! PINSEL - Timer Pin Select
 */
#define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
#define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
/*! PINCFG - Timer Pin Configuration
 *  0b00..Timer pin output disabled
 *  0b01..Timer pin open drain or bidirectional output enable
 *  0b10..Timer pin bidirectional output data
 *  0b11..Timer pin output
 */
#define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
/*! TRGSRC - Trigger Source
 *  0b0..External trigger selected
 *  0b1..Internal trigger selected
 */
#define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
/*! TRGPOL - Trigger Polarity
 *  0b0..Trigger active high
 *  0b1..Trigger active low
 */
#define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define FLEXIO_TIMCTL_TRGSEL_MASK                (0x1F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
/*! TRGSEL - Trigger Select
 */
#define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/*! @} */

/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT                      (8U)

/*! @name TIMCFG - Timer Configuration N Register */
/*! @{ */
#define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
/*! TSTART - Timer Start Bit
 *  0b0..Start bit disabled
 *  0b1..Start bit enabled
 */
#define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
/*! TSTOP - Timer Stop Bit
 *  0b00..Stop bit disabled
 *  0b01..Stop bit is enabled on timer compare
 *  0b10..Stop bit is enabled on timer disable
 *  0b11..Stop bit is enabled on timer compare and timer disable
 */
#define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
/*! TIMENA - Timer Enable
 *  0b000..Timer always enabled
 *  0b001..Timer enabled on Timer N-1 enable
 *  0b010..Timer enabled on Trigger high
 *  0b011..Timer enabled on Trigger high and Pin high
 *  0b100..Timer enabled on Pin rising edge
 *  0b101..Timer enabled on Pin rising edge and Trigger high
 *  0b110..Timer enabled on Trigger rising edge
 *  0b111..Timer enabled on Trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
/*! TIMDIS - Timer Disable
 *  0b000..Timer never disabled
 *  0b001..Timer disabled on Timer N-1 disable
 *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
 *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
 *  0b100..Timer disabled on Pin rising or falling edge
 *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
 *  0b110..Timer disabled on Trigger falling edge
 *  0b111..Reserved
 */
#define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
/*! TIMRST - Timer Reset
 *  0b000..Timer never reset
 *  0b001..Timer reset on Timer Output high.
 *  0b010..Timer reset on Timer Pin equal to Timer Output
 *  0b011..Timer reset on Timer Trigger equal to Timer Output
 *  0b100..Timer reset on Timer Pin rising edge
 *  0b101..Reserved
 *  0b110..Timer reset on Trigger rising edge
 *  0b111..Timer reset on Trigger rising or falling edge
 */
#define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
/*! TIMDEC - Timer Decrement
 *  0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
 *  0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
 *  0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
 *  0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
 *  0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
 *  0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
 *  0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
 *  0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
 */
#define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
/*! TIMOUT - Timer Output
 *  0b00..Timer output is logic one when enabled and is not affected by timer reset
 *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
 *  0b10..Timer output is logic one when enabled and on timer reset
 *  0b11..Timer output is logic zero when enabled and on timer reset
 */
#define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/*! @} */

/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT                      (8U)

/*! @name TIMCMP - Timer Compare N Register */
/*! @{ */
#define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
/*! CMP - Timer Compare Value
 */
#define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/*! @} */

/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT                      (8U)

/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
/*! SHIFTBUFNBS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)

/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
/*! SHIFTBUFHWS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)

/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
/*! SHIFTBUFNIS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)

/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
/*! SHIFTBUFOES - Shift Buffer
 */
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFOES */
#define FLEXIO_SHIFTBUFOES_COUNT                 (8U)

/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
/*! SHIFTBUFEOS - Shift Buffer
 */
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
/*! @} */

/* The count of FLEXIO_SHIFTBUFEOS */
#define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)


/*!
 * @}
 */ /* end of group FLEXIO_Register_Masks */


/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO0 base address */
#define FLEXIO0_BASE                             (0x40032000u)
/** Peripheral FLEXIO0 base pointer */
#define FLEXIO0                                  ((FLEXIO_Type *)FLEXIO0_BASE)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS                        { FLEXIO0_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS                         { FLEXIO0 }

/*!
 * @}
 */ /* end of group FLEXIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FLEXSPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
 * @{
 */

/** FLEXSPI - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCR0;                              /**< Module Control Register 0, offset: 0x0 */
  __IO uint32_t MCR1;                              /**< Module Control Register 1, offset: 0x4 */
  __IO uint32_t MCR2;                              /**< Module Control Register 2, offset: 0x8 */
  __IO uint32_t AHBCR;                             /**< AHB Bus Control Register, offset: 0xC */
  __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x10 */
  __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x14 */
  __IO uint32_t LUTKEY;                            /**< LUT Key Register, offset: 0x18 */
  __IO uint32_t LUTCR;                             /**< LUT Control Register, offset: 0x1C */
  __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_0[32];
  __IO uint32_t FLSHCR0[4];                        /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
  __IO uint32_t FLSHCR1[4];                        /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
  __IO uint32_t FLSHCR2[4];                        /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_1[4];
  __IO uint32_t FLSHCR4;                           /**< Flash Control Register 4, offset: 0x94 */
       uint8_t RESERVED_2[8];
  __IO uint32_t IPCR0;                             /**< IP Control Register 0, offset: 0xA0 */
  __IO uint32_t IPCR1;                             /**< IP Control Register 1, offset: 0xA4 */
       uint8_t RESERVED_3[8];
  __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0xB0 */
  __IO uint32_t DLPR;                              /**< Data Learn Pattern Register, offset: 0xB4 */
  __IO uint32_t IPRXFCR;                           /**< IP RX FIFO Control Register, offset: 0xB8 */
  __IO uint32_t IPTXFCR;                           /**< IP TX FIFO Control Register, offset: 0xBC */
  __IO uint32_t DLLCR[2];                          /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
       uint8_t RESERVED_4[24];
  __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xE0 */
  __I  uint32_t STS1;                              /**< Status Register 1, offset: 0xE4 */
  __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xE8 */
  __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status Register, offset: 0xEC */
  __I  uint32_t IPRXFSTS;                          /**< IP RX FIFO Status Register, offset: 0xF0 */
  __I  uint32_t IPTXFSTS;                          /**< IP TX FIFO Status Register, offset: 0xF4 */
       uint8_t RESERVED_5[8];
  __I  uint32_t RFDR[32];                          /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
  __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
  __IO uint32_t LUT[64];                           /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
} FLEXSPI_Type;

/* ----------------------------------------------------------------------------
   -- FLEXSPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
 * @{
 */

/*! @name MCR0 - Module Control Register 0 */
/*! @{ */
#define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
/*! SWRESET - Software Reset
 */
#define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
#define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
/*! MDIS - Module Disable
 */
#define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
#define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
 *  0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
 *  0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
 *  0b10..Reserved
 *  0b11..Flash provided Read strobe and input from DQS pad
 */
#define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
#define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
#define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter for more details on clocking.
 *  0b000..Divided by 1
 *  0b001..Divided by 2
 *  0b010..Divided by 3
 *  0b011..Divided by 4
 *  0b100..Divided by 5
 *  0b101..Divided by 6
 *  0b110..Divided by 7
 *  0b111..Divided by 8
 */
#define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
#define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
/*! HSEN - Half Speed Serial Flash access Enable.
 *  0b0..Disable divide by 2 of serial flash clock for half speed commands.
 *  0b1..Enable divide by 2 of serial flash clock for half speed commands.
 */
#define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
#define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
/*! DOZEEN - Doze mode enable bit
 *  0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
 *  0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
 */
#define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
#define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
 *    external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
 *    enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
#define FLEXSPI_MCR0_LEARNEN_MASK                (0x8000U)
#define FLEXSPI_MCR0_LEARNEN_SHIFT               (15U)
/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
 *    disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
 *    is correctly executed.
 *  0b0..Disable.
 *  0b1..Enable.
 */
#define FLEXSPI_MCR0_LEARNEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
/*! IPGRANTWAIT - Time out wait cycle for IP command grant.
 */
#define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
 */
#define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */

/*! @name MCR1 - Module Control Register 1 */
/*! @{ */
#define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
#define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
#define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
#define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */

/*! @name MCR2 - Module Control Register 2 */
/*! @{ */
#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
 *    automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
 *    AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
 *    mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
 *  0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
 *  0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
 */
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK          (0x4000U)
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT         (14U)
/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
 *    written with 0x1. This bit will be auto-cleared immediately.
 */
#define FLEXSPI_MCR2_CLRLEARNPHASE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
 *  0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
 *       A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
 *       FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
 *       ignored.
 *  0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
 */
#define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
 *    A_SCLK). In this case, port B flash access is not available. After changing the value of this
 *    field, MCR0[SWRESET] should be set.
 *  0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
 *  0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
 */
#define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
#define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
 */
#define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */

/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */
#define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
#define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
 *  0b0..Flash will be accessed in Individual mode.
 *  0b1..Flash will be accessed in Parallel mode.
 */
#define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
#define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
/*! CACHABLEEN - Enable AHB bus cachable read access support.
 *  0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
 *  0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
 */
#define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
 *    of AHB write access, refer for more details about AHB bufferable write.
 *  0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
 *       ready after all data is transmitted to External device and AHB command finished.
 *  0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
 *       granted by arbitrator and will not wait for AHB command finished.
 */
#define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
#define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
/*! PREFETCHEN - AHB Read Prefetch Enable.
 */
#define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
#define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
 *  0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
 *  0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
 *       burst required to meet the alignment requirement.
 */
#define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
#define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
#define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
/*! READSZALIGN - AHB Read Size Alignment
 *  0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...
 *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
 */
#define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
/*! @} */

/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
#define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
 */
#define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
#define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
 */
#define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
#define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
 */
#define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
#define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
 */
#define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
#define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
 */
#define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK       (0x80U)
#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT      (7U)
/*! DATALEARNFAILEN - Data Learning failed interrupt enable.
 */
#define FLEXSPI_INTEN_DATALEARNFAILEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
 */
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
 */
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
#define FLEXSPI_INTEN_AHBBUSERROREN_MASK         (0x400U)
#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT        (10U)
/*! AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
 */
#define FLEXSPI_INTEN_AHBBUSERROREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK       (0x400U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT      (10U)
/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
 */
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
 */
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
#define FLEXSPI_INTEN_KEYDONEEN_MASK             (0x1000U)
#define FLEXSPI_INTEN_KEYDONEEN_SHIFT            (12U)
/*! KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
 */
#define FLEXSPI_INTEN_KEYDONEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
#define FLEXSPI_INTEN_KEYERROREN_MASK            (0x2000U)
#define FLEXSPI_INTEN_KEYERROREN_SHIFT           (13U)
/*! KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
 */
#define FLEXSPI_INTEN_KEYERROREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
/*! @} */

/*! @name INTR - Interrupt Register */
/*! @{ */
#define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
 *    generated when there is IPCMDGE or IPCMDERR interrupt generated.
 */
#define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
#define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
 */
#define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
#define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
 */
#define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
#define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
 *    IP command, this command will be ignored and not executed at all.
 */
#define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
#define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
 *    AHB command, this command will be ignored and not executed at all.
 */
#define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
#define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
/*! IPRXWA - IP RX FIFO watermark available interrupt.
 */
#define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
#define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
/*! IPTXWE - IP TX FIFO watermark empty interrupt.
 */
#define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
#define FLEXSPI_INTR_DATALEARNFAIL_MASK          (0x80U)
#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT         (7U)
/*! DATALEARNFAIL - Data Learning failed interrupt.
 */
#define FLEXSPI_INTR_DATALEARNFAIL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
 */
#define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
 */
#define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
#define FLEXSPI_INTR_AHBBUSERROR_MASK            (0x400U)
#define FLEXSPI_INTR_AHBBUSERROR_SHIFT           (10U)
/*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
 */
#define FLEXSPI_INTR_AHBBUSERROR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK          (0x400U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT         (10U)
/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
 */
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
#define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
/*! SEQTIMEOUT - Sequence execution timeout interrupt.
 */
#define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
#define FLEXSPI_INTR_KEYDONE_MASK                (0x1000U)
#define FLEXSPI_INTR_KEYDONE_SHIFT               (12U)
/*! KEYDONE - OTFAD key blob processing done interrupt.
 */
#define FLEXSPI_INTR_KEYDONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
#define FLEXSPI_INTR_KEYERROR_MASK               (0x2000U)
#define FLEXSPI_INTR_KEYERROR_SHIFT              (13U)
/*! KEYERROR - OTFAD key blob processing error interrupt.
 */
#define FLEXSPI_INTR_KEYERROR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
/*! @} */

/*! @name LUTKEY - LUT Key Register */
/*! @{ */
#define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
/*! KEY - The Key to lock or unlock LUT.
 */
#define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */

/*! @name LUTCR - LUT Control Register */
/*! @{ */
#define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
/*! LOCK - Lock LUT
 */
#define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
#define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
/*! UNLOCK - Unlock LUT
 */
#define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
/*! @} */

/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
/*! @{ */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x1FFU)  /* Merged from fields with different position or width, of widths (8, 9), largest definition used */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
/*! BUFSZ - AHB RX Buffer Size in 64 bits.
 */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)  /* Merged from fields with different position or width, of widths (8, 9), largest definition used */
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
 */
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
 */
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
 */
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */

/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)

/*! @name FLSHCR0 - Flash Control Register 0 */
/*! @{ */
#define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
/*! FLSHSZ - Flash Size in KByte.
 */
#define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT                    (4U)

/*! @name FLSHCR1 - Flash Control Register 1 */
/*! @{ */
#define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
/*! TCSS - Serial Flash CS setup time.
 */
#define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
#define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
/*! TCSH - Serial Flash CS Hold time.
 */
#define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
#define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
/*! WA - Word Addressable.
 */
#define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
#define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
/*! CAS - Column Address Size.
 */
#define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
/*! CSINTERVALUNIT - CS interval unit
 *  0b0..The CS interval unit is 1 serial clock cycle
 *  0b1..The CS interval unit is 256 serial clock cycle
 */
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
 *    deassertion and flash device Chip selection assertion. If external flash has a limitation on
 *    the interval between command sequences, this field should be set accordingly. If there is no
 *    limitation, set this field with value 0x0.
 */
#define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT                    (4U)

/*! @name FLSHCR2 - Flash Control Register 2 */
/*! @{ */
#define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
 */
#define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
 */
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
/*! AWRSEQID - Sequence Index for AHB Write triggered Command.
 */
#define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
 */
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
#define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
/*! AWRWAITUNIT - AWRWAIT unit
 *  0b000..The AWRWAIT unit is 2 ahb clock cycle
 *  0b001..The AWRWAIT unit is 8 ahb clock cycle
 *  0b010..The AWRWAIT unit is 32 ahb clock cycle
 *  0b011..The AWRWAIT unit is 128 ahb clock cycle
 *  0b100..The AWRWAIT unit is 512 ahb clock cycle
 *  0b101..The AWRWAIT unit is 2048 ahb clock cycle
 *  0b110..The AWRWAIT unit is 8192 ahb clock cycle
 *  0b111..The AWRWAIT unit is 32768 ahb clock cycle
 */
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
 *    Refer Programmable Sequence Engine for details.
 */
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */

/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT                    (4U)

/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */
#define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
 *  0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
 *       burst start address alignment when flash is accessed in individual mode.
 *  0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
 *       burst start address alignment when flash is accessed in individual mode.
 */
#define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
#define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
 *    memory device on port A, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
#define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
#define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
 *    memory device on port B, this bit must be set.
 *  0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
 *  0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
 */
#define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
/*! @} */

/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */
#define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
/*! SFAR - Serial Flash Address for IP command.
 */
#define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */

/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */
#define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
 */
#define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
#define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
/*! ISEQID - Sequence Index in LUT for IP command.
 */
#define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
#define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
 */
#define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
#define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
#define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
/*! IPAREN - Parallel mode Enabled for IP command.
 *  0b0..Flash will be accessed in Individual mode.
 *  0b1..Flash will be accessed in Parallel mode.
 */
#define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
/*! @} */

/*! @name IPCMD - IP Command Register */
/*! @{ */
#define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
/*! TRG - Setting this bit will trigger an IP Command.
 */
#define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */

/*! @name DLPR - Data Learn Pattern Register */
/*! @{ */
#define FLEXSPI_DLPR_DLP_MASK                    (0xFFFFFFFFU)
#define FLEXSPI_DLPR_DLP_SHIFT                   (0U)
/*! DLP - Data Learning Pattern.
 */
#define FLEXSPI_DLPR_DLP(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
/*! @} */

/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
 */
#define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
 *  0b0..IP RX FIFO would be read by processor.
 *  0b1..IP RX FIFO would be read by DMA.
 */
#define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
#define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
 */
#define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */

/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
 */
#define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
#define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
 *  0b0..IP TX FIFO would be filled by processor.
 *  0b1..IP TX FIFO would be filled by DMA.
 */
#define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
#define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x1FCU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
 */
#define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */

/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */
#define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
/*! DLLEN - DLL calibration enable.
 */
#define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
#define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
 *    DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
 *    action is edge triggered, so software need to clear this bit after set this bit (no delay
 *    limitation).
 */
#define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
 *    of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
 *    OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
 */
#define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
#define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
/*! OVRDEN - Slave clock delay line delay cell number selection override enable.
 */
#define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
#define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
/*! OVRDVAL - Slave clock delay line delay cell number selection override value.
 */
#define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
/*! @} */

/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT                      (2U)

/*! @name STS0 - Status Register 0 */
/*! @{ */
#define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
 *    sequence executing on FlexSPI interface.
 */
#define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
#define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
 *    sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
 *    (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
 *    this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
 */
#define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
#define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
 *    by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
 *  0b00..Triggered by AHB read command (triggered by AHB read).
 *  0b01..Triggered by AHB write command (triggered by AHB Write).
 *  0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
 *  0b11..Triggered by suspended command (resumed).
 */
#define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
#define FLEXSPI_STS0_DATALEARNPHASEA_MASK        (0xF0U)
#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT       (4U)
/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning.
 */
#define FLEXSPI_STS0_DATALEARNPHASEA(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
#define FLEXSPI_STS0_DATALEARNPHASEB_MASK        (0xF00U)
#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT       (8U)
/*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning.
 */
#define FLEXSPI_STS0_DATALEARNPHASEB(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
/*! @} */

/*! @name STS1 - Status Register 1 */
/*! @{ */
#define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
 *    will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 */
#define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
 *    cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b1110..Sequence execution timeout.
 */
#define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
#define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
 *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
 */
#define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
#define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
 *    cleared when INTR[IPCMDERR] is write-1-clear(w1c).
 *  0b0000..No error.
 *  0b0010..IP command with JMP_ON_CS instruction used in the sequence.
 *  0b0011..There is unknown instruction opcode in the sequence.
 *  0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
 *  0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
 *  0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
 *  0b1110..Sequence execution timeout.
 *  0b1111..Flash boundary crossed.
 */
#define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */

/*! @name STS2 - Status Register 2 */
/*! @{ */
#define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
/*! ASLVLOCK - Flash A sample clock slave delay line locked.
 */
#define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
#define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
/*! AREFLOCK - Flash A sample clock reference delay line locked.
 */
#define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
#define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
 */
#define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
#define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
 */
#define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
#define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
#define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
/*! BSLVLOCK - Flash B sample clock slave delay line locked.
 */
#define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
#define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
#define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
/*! BREFLOCK - Flash B sample clock reference delay line locked.
 */
#define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
#define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
#define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
 */
#define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
#define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
#define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
 */
#define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
/*! @} */

/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */
#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
 */
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
/*! BUFID - AHB RX BUF ID for suspended command sequence.
 */
#define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
/*! DATLFT - Left Data size for suspended command sequence (in byte).
 */
#define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */

/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
/*! FILL - Fill level of IP RX FIFO.
 */
#define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
 */
#define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */

/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
/*! FILL - Fill level of IP TX FIFO.
 */
#define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
 */
#define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */

/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
/*! RXDATA - RX Data
 */
#define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT                       (32U)

/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
/*! TXDATA - TX Data
 */
#define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */

/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT                       (32U)

/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
/*! OPERAND0 - OPERAND0
 */
#define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
/*! NUM_PADS0 - NUM_PADS0
 */
#define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
/*! OPCODE0 - OPCODE
 */
#define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
/*! OPERAND1 - OPERAND1
 */
#define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
/*! NUM_PADS1 - NUM_PADS1
 */
#define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
/*! OPCODE1 - OPCODE1
 */
#define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */

/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT                        (64U)


/*!
 * @}
 */ /* end of group FLEXSPI_Register_Masks */


/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral FLEXSPI0 base address */
#define FLEXSPI0_BASE                            (0x40134000u)
/** Peripheral FLEXSPI0 base pointer */
#define FLEXSPI0                                 ((FLEXSPI_Type *)FLEXSPI0_BASE)
/** Peripheral FLEXSPI1 base address */
#define FLEXSPI1_BASE                            (0x4013C000u)
/** Peripheral FLEXSPI1 base pointer */
#define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS                       { FLEXSPI0_BASE, FLEXSPI1_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS                        { FLEXSPI0, FLEXSPI1 }
/* FlexSPI0 AMBA address. */
#define FlexSPI0_AMBA_BASE                       (0x08000000U)
/* FlexSPI1 AMBA address. */
#define FlexSPI1_AMBA_BASE                       (0x28000000U)


/*!
 * @}
 */ /* end of group FLEXSPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- FREQME Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer
 * @{
 */

/** FREQME - Register Layout Typedef */
typedef struct {
  union {                                          /* offset: 0x0 */
    __I  uint32_t FREQMECTRL_R;                      /**< Frequency Measurement (in Read mode), offset: 0x0 */
    __O  uint32_t FREQMECTRL_W;                      /**< Frequency Measurement (in Write mode), offset: 0x0 */
  };
} FREQME_Type;

/* ----------------------------------------------------------------------------
   -- FREQME Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup FREQME_Register_Masks FREQME Register Masks
 * @{
 */

/*! @name FREQMECTRL_R - Frequency Measurement (in Read mode) */
/*! @{ */
#define FREQME_FREQMECTRL_R_RESULT_MASK          (0x7FFFFFFFU)
#define FREQME_FREQMECTRL_R_RESULT_SHIFT         (0U)
/*! RESULT - Result
 */
#define FREQME_FREQMECTRL_R_RESULT(x)            (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_RESULT_SHIFT)) & FREQME_FREQMECTRL_R_RESULT_MASK)
#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U)
#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U)
/*! MEASURE_IN_PROGRESS - Measure in Progress
 *  0b0..Process complete. Measurement cycle is complete. The results are ready in the RESULT field.
 *  0b1..In Progress. Measurement cycle is in progress.
 */
#define FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_R_MEASURE_IN_PROGRESS_MASK)
/*! @} */

/*! @name FREQMECTRL_W - Frequency Measurement (in Write mode) */
/*! @{ */
#define FREQME_FREQMECTRL_W_REF_SCALE_MASK       (0x1FU)
#define FREQME_FREQMECTRL_W_REF_SCALE_SHIFT      (0U)
/*! REF_SCALE - Reference Clock Scaling Factor
 *  0b00000..Count cycle = 2^0 = 1
 *  0b00001..Count cycle = 2^1 = 2
 *  0b00010..Count cycle = 2^4 = 4
 *  0b11111..Count cycle = 2^31 = 2,147,483,648
 */
#define FREQME_FREQMECTRL_W_REF_SCALE(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_REF_SCALE_SHIFT)) & FREQME_FREQMECTRL_W_REF_SCALE_MASK)
#define FREQME_FREQMECTRL_W_PULSE_MODE_MASK      (0x100U)
#define FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT     (8U)
/*! PULSE_MODE - Pulse Width Measurement mode select
 *  0b0..Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the measurement starts
 *       (real count start is aligned at rising edge arrival on reference clock), the target counter increments by
 *       the target clock until the reference counter running by the reference clock reaches the count end point
 *       selected by REF_SCALE.
 *  0b1..Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, measuring the high or
 *       low period of reference clock input selected by PULSE_POL. The target counter starts incrementing by the
 *       target clock once a corresponding trigger edge (rising edge for high period measurement and falling edge for
 *       low period) occurs.
 */
#define FREQME_FREQMECTRL_W_PULSE_MODE(x)        (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_MODE_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_MODE_MASK)
#define FREQME_FREQMECTRL_W_PULSE_POL_MASK       (0x200U)
#define FREQME_FREQMECTRL_W_PULSE_POL_SHIFT      (9U)
/*! PULSE_POL - Pulse Polarity
 *  0b0..High Period. High period of reference clock is measured in Pulse Width Measurement mode triggered by the
 *       rising edge on the reference clock input.
 *  0b1..Low Period. Low period of reference clock is measured in Pulse Width Measurement mode triggered by the
 *       falling edge on the reference clock input.
 */
#define FREQME_FREQMECTRL_W_PULSE_POL(x)         (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_PULSE_POL_SHIFT)) & FREQME_FREQMECTRL_W_PULSE_POL_MASK)
#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U)
#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U)
/*! MEASURE_IN_PROGRESS - Measure in Progress
 *  0b0..Force Terminate. Forces the termination of any measurement cycle currently in progress and resets RESULT or just resets RESULT if in idle.
 *  0b1..Initiates Measurement Cycle. Initiates frequency or pulse width measurement process. Hardware clears the
 *       MEASURE_IN_PROGRESS bit when the measurement cycle completes. A new measurement starts if there is an
 *       active measurement in progress.
 */
#define FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_FREQMECTRL_W_MEASURE_IN_PROGRESS_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group FREQME_Register_Masks */


/* FREQME - Peripheral instance base addresses */
/** Peripheral FREQME base address */
#define FREQME_BASE                              (0x4002F000u)
/** Peripheral FREQME base pointer */
#define FREQME                                   ((FREQME_Type *)FREQME_BASE)
/** Array initializer of FREQME peripheral base addresses */
#define FREQME_BASE_ADDRS                        { FREQME_BASE }
/** Array initializer of FREQME peripheral base pointers */
#define FREQME_BASE_PTRS                         { FREQME }

/*!
 * @}
 */ /* end of group FREQME_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- GPIO Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 * @{
 */

/** GPIO - Register Layout Typedef */
typedef struct {
  __IO uint8_t B[8][32];                           /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
       uint8_t RESERVED_0[3840];
  __IO uint32_t W[8][32];                          /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
       uint8_t RESERVED_1[3072];
  __O  uint32_t DIR[8];                            /**< Port direction, array offset: 0x2000, array step: 0x4 */
       uint8_t RESERVED_2[96];
  __IO uint32_t MASK[8];                           /**< Port mask, array offset: 0x2080, array step: 0x4 */
       uint8_t RESERVED_3[96];
  __IO uint32_t PIN[8];                            /**< Port pin, array offset: 0x2100, array step: 0x4 */
       uint8_t RESERVED_4[96];
  __IO uint32_t MPIN[8];                           /**< Masked Port Pin, array offset: 0x2180, array step: 0x4 */
       uint8_t RESERVED_5[96];
  __IO uint32_t SET[8];                            /**< Port set, array offset: 0x2200, array step: 0x4 */
       uint8_t RESERVED_6[96];
  __IO uint32_t CLR[8];                            /**< Port clear, array offset: 0x2280, array step: 0x4 */
       uint8_t RESERVED_7[96];
  __O  uint32_t NOT[8];                            /**< Port toggle, array offset: 0x2300, array step: 0x4 */
       uint8_t RESERVED_8[96];
  __O  uint32_t DIRSET[8];                         /**< Port direction set, array offset: 0x2380, array step: 0x4 */
       uint8_t RESERVED_9[96];
  __IO uint32_t DIRCLR[8];                         /**< Port direction clear, array offset: 0x2400, array step: 0x4 */
       uint8_t RESERVED_10[96];
  __O  uint32_t DIRNOT[8];                         /**< Port direction toggle, array offset: 0x2480, array step: 0x4 */
       uint8_t RESERVED_11[96];
  __IO uint32_t INTENA[8];                         /**< Interrupt A enable control, array offset: 0x2500, array step: 0x4 */
       uint8_t RESERVED_12[96];
  __IO uint32_t INTENB[8];                         /**< Interrupt B enable control, array offset: 0x2580, array step: 0x4 */
       uint8_t RESERVED_13[96];
  __IO uint32_t INTPOL[8];                         /**< Interupt polarity control, array offset: 0x2600, array step: 0x4 */
       uint8_t RESERVED_14[96];
  __IO uint32_t INTEDG[8];                         /**< Interrupt edge select, array offset: 0x2680, array step: 0x4 */
       uint8_t RESERVED_15[96];
  __IO uint32_t INTSTATA[8];                       /**< Interrupt status for interrupt A, array offset: 0x2700, array step: 0x4 */
       uint8_t RESERVED_16[96];
  __IO uint32_t INTSTATB[8];                       /**< Interrupt status for interrupt B, array offset: 0x2780, array step: 0x4 */
} GPIO_Type;

/* ----------------------------------------------------------------------------
   -- GPIO Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup GPIO_Register_Masks GPIO Register Masks
 * @{
 */

/*! @name B - Byte pin registers for all port GPIO pins */
/*! @{ */
#define GPIO_B_PBYTE_MASK                        (0x1U)
#define GPIO_B_PBYTE_SHIFT                       (0U)
/*! PBYTE - Port Byte
 */
#define GPIO_B_PBYTE(x)                          (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
/*! @} */

/* The count of GPIO_B */
#define GPIO_B_COUNT                             (8U)

/* The count of GPIO_B */
#define GPIO_B_COUNT2                            (32U)

/*! @name W - Word pin registers for all port GPIO pins */
/*! @{ */
#define GPIO_W_PWORD_MASK                        (0xFFFFFFFFU)
#define GPIO_W_PWORD_SHIFT                       (0U)
/*! PWORD - Read 0- pin PIOa_b is LOW. Write 0- clear output bit. Read 0xFFFF FFFF- pin PIOa_b is
 *    HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF- sets output bit. Only 0 or 0xFFFF FFFF can be
 *    read. Writing any value other than 0 will set the output bit.
 */
#define GPIO_W_PWORD(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
/*! @} */

/* The count of GPIO_W */
#define GPIO_W_COUNT                             (8U)

/* The count of GPIO_W */
#define GPIO_W_COUNT2                            (32U)

/*! @name DIR - Port direction */
/*! @{ */
#define GPIO_DIR_DIRP0_MASK                      (0x1U)
#define GPIO_DIR_DIRP0_SHIFT                     (0U)
/*! DIRP0 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP0_SHIFT)) & GPIO_DIR_DIRP0_MASK)
#define GPIO_DIR_DIRP1_MASK                      (0x2U)
#define GPIO_DIR_DIRP1_SHIFT                     (1U)
/*! DIRP1 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP1_SHIFT)) & GPIO_DIR_DIRP1_MASK)
#define GPIO_DIR_DIRP2_MASK                      (0x4U)
#define GPIO_DIR_DIRP2_SHIFT                     (2U)
/*! DIRP2 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP2_SHIFT)) & GPIO_DIR_DIRP2_MASK)
#define GPIO_DIR_DIRP3_MASK                      (0x8U)
#define GPIO_DIR_DIRP3_SHIFT                     (3U)
/*! DIRP3 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP3_SHIFT)) & GPIO_DIR_DIRP3_MASK)
#define GPIO_DIR_DIRP4_MASK                      (0x10U)
#define GPIO_DIR_DIRP4_SHIFT                     (4U)
/*! DIRP4 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP4_SHIFT)) & GPIO_DIR_DIRP4_MASK)
#define GPIO_DIR_DIRP5_MASK                      (0x20U)
#define GPIO_DIR_DIRP5_SHIFT                     (5U)
/*! DIRP5 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP5_SHIFT)) & GPIO_DIR_DIRP5_MASK)
#define GPIO_DIR_DIRP6_MASK                      (0x40U)
#define GPIO_DIR_DIRP6_SHIFT                     (6U)
/*! DIRP6 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP6_SHIFT)) & GPIO_DIR_DIRP6_MASK)
#define GPIO_DIR_DIRP7_MASK                      (0x80U)
#define GPIO_DIR_DIRP7_SHIFT                     (7U)
/*! DIRP7 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP7_SHIFT)) & GPIO_DIR_DIRP7_MASK)
#define GPIO_DIR_DIRP8_MASK                      (0x100U)
#define GPIO_DIR_DIRP8_SHIFT                     (8U)
/*! DIRP8 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP8_SHIFT)) & GPIO_DIR_DIRP8_MASK)
#define GPIO_DIR_DIRP9_MASK                      (0x200U)
#define GPIO_DIR_DIRP9_SHIFT                     (9U)
/*! DIRP9 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP9_SHIFT)) & GPIO_DIR_DIRP9_MASK)
#define GPIO_DIR_DIRP10_MASK                     (0x400U)
#define GPIO_DIR_DIRP10_SHIFT                    (10U)
/*! DIRP10 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP10_SHIFT)) & GPIO_DIR_DIRP10_MASK)
#define GPIO_DIR_DIRP11_MASK                     (0x800U)
#define GPIO_DIR_DIRP11_SHIFT                    (11U)
/*! DIRP11 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP11_SHIFT)) & GPIO_DIR_DIRP11_MASK)
#define GPIO_DIR_DIRP12_MASK                     (0x1000U)
#define GPIO_DIR_DIRP12_SHIFT                    (12U)
/*! DIRP12 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP12_SHIFT)) & GPIO_DIR_DIRP12_MASK)
#define GPIO_DIR_DIRP13_MASK                     (0x2000U)
#define GPIO_DIR_DIRP13_SHIFT                    (13U)
/*! DIRP13 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP13_SHIFT)) & GPIO_DIR_DIRP13_MASK)
#define GPIO_DIR_DIRP14_MASK                     (0x4000U)
#define GPIO_DIR_DIRP14_SHIFT                    (14U)
/*! DIRP14 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP14_SHIFT)) & GPIO_DIR_DIRP14_MASK)
#define GPIO_DIR_DIRP15_MASK                     (0x8000U)
#define GPIO_DIR_DIRP15_SHIFT                    (15U)
/*! DIRP15 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP15_SHIFT)) & GPIO_DIR_DIRP15_MASK)
#define GPIO_DIR_DIRP16_MASK                     (0x10000U)
#define GPIO_DIR_DIRP16_SHIFT                    (16U)
/*! DIRP16 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP16_SHIFT)) & GPIO_DIR_DIRP16_MASK)
#define GPIO_DIR_DIRP17_MASK                     (0x20000U)
#define GPIO_DIR_DIRP17_SHIFT                    (17U)
/*! DIRP17 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP17_SHIFT)) & GPIO_DIR_DIRP17_MASK)
#define GPIO_DIR_DIRP18_MASK                     (0x40000U)
#define GPIO_DIR_DIRP18_SHIFT                    (18U)
/*! DIRP18 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP18_SHIFT)) & GPIO_DIR_DIRP18_MASK)
#define GPIO_DIR_DIRP19_MASK                     (0x80000U)
#define GPIO_DIR_DIRP19_SHIFT                    (19U)
/*! DIRP19 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP19_SHIFT)) & GPIO_DIR_DIRP19_MASK)
#define GPIO_DIR_DIRP20_MASK                     (0x100000U)
#define GPIO_DIR_DIRP20_SHIFT                    (20U)
/*! DIRP20 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP20_SHIFT)) & GPIO_DIR_DIRP20_MASK)
#define GPIO_DIR_DIRP21_MASK                     (0x200000U)
#define GPIO_DIR_DIRP21_SHIFT                    (21U)
/*! DIRP21 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP21_SHIFT)) & GPIO_DIR_DIRP21_MASK)
#define GPIO_DIR_DIRP22_MASK                     (0x400000U)
#define GPIO_DIR_DIRP22_SHIFT                    (22U)
/*! DIRP22 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP22_SHIFT)) & GPIO_DIR_DIRP22_MASK)
#define GPIO_DIR_DIRP23_MASK                     (0x800000U)
#define GPIO_DIR_DIRP23_SHIFT                    (23U)
/*! DIRP23 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP23_SHIFT)) & GPIO_DIR_DIRP23_MASK)
#define GPIO_DIR_DIRP24_MASK                     (0x1000000U)
#define GPIO_DIR_DIRP24_SHIFT                    (24U)
/*! DIRP24 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP24_SHIFT)) & GPIO_DIR_DIRP24_MASK)
#define GPIO_DIR_DIRP25_MASK                     (0x2000000U)
#define GPIO_DIR_DIRP25_SHIFT                    (25U)
/*! DIRP25 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP25_SHIFT)) & GPIO_DIR_DIRP25_MASK)
#define GPIO_DIR_DIRP26_MASK                     (0x4000000U)
#define GPIO_DIR_DIRP26_SHIFT                    (26U)
/*! DIRP26 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP26_SHIFT)) & GPIO_DIR_DIRP26_MASK)
#define GPIO_DIR_DIRP27_MASK                     (0x8000000U)
#define GPIO_DIR_DIRP27_SHIFT                    (27U)
/*! DIRP27 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP27_SHIFT)) & GPIO_DIR_DIRP27_MASK)
#define GPIO_DIR_DIRP28_MASK                     (0x10000000U)
#define GPIO_DIR_DIRP28_SHIFT                    (28U)
/*! DIRP28 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP28_SHIFT)) & GPIO_DIR_DIRP28_MASK)
#define GPIO_DIR_DIRP29_MASK                     (0x20000000U)
#define GPIO_DIR_DIRP29_SHIFT                    (29U)
/*! DIRP29 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP29_SHIFT)) & GPIO_DIR_DIRP29_MASK)
#define GPIO_DIR_DIRP30_MASK                     (0x40000000U)
#define GPIO_DIR_DIRP30_SHIFT                    (30U)
/*! DIRP30 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP30_SHIFT)) & GPIO_DIR_DIRP30_MASK)
#define GPIO_DIR_DIRP31_MASK                     (0x80000000U)
#define GPIO_DIR_DIRP31_SHIFT                    (31U)
/*! DIRP31 - Selects pin direction for pin PIOa_b.
 *  0b0..Input
 *  0b1..Output
 */
#define GPIO_DIR_DIRP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP31_SHIFT)) & GPIO_DIR_DIRP31_MASK)
/*! @} */

/* The count of GPIO_DIR */
#define GPIO_DIR_COUNT                           (8U)

/*! @name MASK - Port mask */
/*! @{ */
#define GPIO_MASK_MASKP0_MASK                    (0x1U)
#define GPIO_MASK_MASKP0_SHIFT                   (0U)
/*! MASKP0 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP0(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP0_SHIFT)) & GPIO_MASK_MASKP0_MASK)
#define GPIO_MASK_MASKP1_MASK                    (0x2U)
#define GPIO_MASK_MASKP1_SHIFT                   (1U)
/*! MASKP1 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP1(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP1_SHIFT)) & GPIO_MASK_MASKP1_MASK)
#define GPIO_MASK_MASKP2_MASK                    (0x4U)
#define GPIO_MASK_MASKP2_SHIFT                   (2U)
/*! MASKP2 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP2(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP2_SHIFT)) & GPIO_MASK_MASKP2_MASK)
#define GPIO_MASK_MASKP3_MASK                    (0x8U)
#define GPIO_MASK_MASKP3_SHIFT                   (3U)
/*! MASKP3 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP3(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP3_SHIFT)) & GPIO_MASK_MASKP3_MASK)
#define GPIO_MASK_MASKP4_MASK                    (0x10U)
#define GPIO_MASK_MASKP4_SHIFT                   (4U)
/*! MASKP4 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP4(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP4_SHIFT)) & GPIO_MASK_MASKP4_MASK)
#define GPIO_MASK_MASKP5_MASK                    (0x20U)
#define GPIO_MASK_MASKP5_SHIFT                   (5U)
/*! MASKP5 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP5(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP5_SHIFT)) & GPIO_MASK_MASKP5_MASK)
#define GPIO_MASK_MASKP6_MASK                    (0x40U)
#define GPIO_MASK_MASKP6_SHIFT                   (6U)
/*! MASKP6 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP6(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP6_SHIFT)) & GPIO_MASK_MASKP6_MASK)
#define GPIO_MASK_MASKP7_MASK                    (0x80U)
#define GPIO_MASK_MASKP7_SHIFT                   (7U)
/*! MASKP7 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP7(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP7_SHIFT)) & GPIO_MASK_MASKP7_MASK)
#define GPIO_MASK_MASKP8_MASK                    (0x100U)
#define GPIO_MASK_MASKP8_SHIFT                   (8U)
/*! MASKP8 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP8(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP8_SHIFT)) & GPIO_MASK_MASKP8_MASK)
#define GPIO_MASK_MASKP9_MASK                    (0x200U)
#define GPIO_MASK_MASKP9_SHIFT                   (9U)
/*! MASKP9 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP9(x)                      (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP9_SHIFT)) & GPIO_MASK_MASKP9_MASK)
#define GPIO_MASK_MASKP10_MASK                   (0x400U)
#define GPIO_MASK_MASKP10_SHIFT                  (10U)
/*! MASKP10 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP10(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP10_SHIFT)) & GPIO_MASK_MASKP10_MASK)
#define GPIO_MASK_MASKP11_MASK                   (0x800U)
#define GPIO_MASK_MASKP11_SHIFT                  (11U)
/*! MASKP11 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP11(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP11_SHIFT)) & GPIO_MASK_MASKP11_MASK)
#define GPIO_MASK_MASKP12_MASK                   (0x1000U)
#define GPIO_MASK_MASKP12_SHIFT                  (12U)
/*! MASKP12 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP12(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP12_SHIFT)) & GPIO_MASK_MASKP12_MASK)
#define GPIO_MASK_MASKP13_MASK                   (0x2000U)
#define GPIO_MASK_MASKP13_SHIFT                  (13U)
/*! MASKP13 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP13(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP13_SHIFT)) & GPIO_MASK_MASKP13_MASK)
#define GPIO_MASK_MASKP14_MASK                   (0x4000U)
#define GPIO_MASK_MASKP14_SHIFT                  (14U)
/*! MASKP14 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP14(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP14_SHIFT)) & GPIO_MASK_MASKP14_MASK)
#define GPIO_MASK_MASKP15_MASK                   (0x8000U)
#define GPIO_MASK_MASKP15_SHIFT                  (15U)
/*! MASKP15 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP15(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP15_SHIFT)) & GPIO_MASK_MASKP15_MASK)
#define GPIO_MASK_MASKP16_MASK                   (0x10000U)
#define GPIO_MASK_MASKP16_SHIFT                  (16U)
/*! MASKP16 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP16(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP16_SHIFT)) & GPIO_MASK_MASKP16_MASK)
#define GPIO_MASK_MASKP17_MASK                   (0x20000U)
#define GPIO_MASK_MASKP17_SHIFT                  (17U)
/*! MASKP17 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP17(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP17_SHIFT)) & GPIO_MASK_MASKP17_MASK)
#define GPIO_MASK_MASKP18_MASK                   (0x40000U)
#define GPIO_MASK_MASKP18_SHIFT                  (18U)
/*! MASKP18 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP18(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP18_SHIFT)) & GPIO_MASK_MASKP18_MASK)
#define GPIO_MASK_MASKP19_MASK                   (0x80000U)
#define GPIO_MASK_MASKP19_SHIFT                  (19U)
/*! MASKP19 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP19(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP19_SHIFT)) & GPIO_MASK_MASKP19_MASK)
#define GPIO_MASK_MASKP20_MASK                   (0x100000U)
#define GPIO_MASK_MASKP20_SHIFT                  (20U)
/*! MASKP20 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP20(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP20_SHIFT)) & GPIO_MASK_MASKP20_MASK)
#define GPIO_MASK_MASKP21_MASK                   (0x200000U)
#define GPIO_MASK_MASKP21_SHIFT                  (21U)
/*! MASKP21 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP21(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP21_SHIFT)) & GPIO_MASK_MASKP21_MASK)
#define GPIO_MASK_MASKP22_MASK                   (0x400000U)
#define GPIO_MASK_MASKP22_SHIFT                  (22U)
/*! MASKP22 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP22(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP22_SHIFT)) & GPIO_MASK_MASKP22_MASK)
#define GPIO_MASK_MASKP23_MASK                   (0x800000U)
#define GPIO_MASK_MASKP23_SHIFT                  (23U)
/*! MASKP23 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP23(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP23_SHIFT)) & GPIO_MASK_MASKP23_MASK)
#define GPIO_MASK_MASKP24_MASK                   (0x1000000U)
#define GPIO_MASK_MASKP24_SHIFT                  (24U)
/*! MASKP24 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP24(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP24_SHIFT)) & GPIO_MASK_MASKP24_MASK)
#define GPIO_MASK_MASKP25_MASK                   (0x2000000U)
#define GPIO_MASK_MASKP25_SHIFT                  (25U)
/*! MASKP25 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP25(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP25_SHIFT)) & GPIO_MASK_MASKP25_MASK)
#define GPIO_MASK_MASKP26_MASK                   (0x4000000U)
#define GPIO_MASK_MASKP26_SHIFT                  (26U)
/*! MASKP26 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP26(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP26_SHIFT)) & GPIO_MASK_MASKP26_MASK)
#define GPIO_MASK_MASKP27_MASK                   (0x8000000U)
#define GPIO_MASK_MASKP27_SHIFT                  (27U)
/*! MASKP27 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP27(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP27_SHIFT)) & GPIO_MASK_MASKP27_MASK)
#define GPIO_MASK_MASKP28_MASK                   (0x10000000U)
#define GPIO_MASK_MASKP28_SHIFT                  (28U)
/*! MASKP28 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP28(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP28_SHIFT)) & GPIO_MASK_MASKP28_MASK)
#define GPIO_MASK_MASKP29_MASK                   (0x20000000U)
#define GPIO_MASK_MASKP29_SHIFT                  (29U)
/*! MASKP29 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP29(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP29_SHIFT)) & GPIO_MASK_MASKP29_MASK)
#define GPIO_MASK_MASKP30_MASK                   (0x40000000U)
#define GPIO_MASK_MASKP30_SHIFT                  (30U)
/*! MASKP30 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP30(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP30_SHIFT)) & GPIO_MASK_MASKP30_MASK)
#define GPIO_MASK_MASKP31_MASK                   (0x80000000U)
#define GPIO_MASK_MASKP31_SHIFT                  (31U)
/*! MASKP31 - Port Mask
 *  0b0..Read MPIN: pin state; write MPIN: load output bit
 *  0b1..Read MPIN: 0; write MPIN: output bit not affected
 */
#define GPIO_MASK_MASKP31(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP31_SHIFT)) & GPIO_MASK_MASKP31_MASK)
/*! @} */

/* The count of GPIO_MASK */
#define GPIO_MASK_COUNT                          (8U)

/*! @name PIN - Port pin */
/*! @{ */
#define GPIO_PIN_PORT0_MASK                      (0x1U)
#define GPIO_PIN_PORT0_SHIFT                     (0U)
/*! PORT0 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT0_SHIFT)) & GPIO_PIN_PORT0_MASK)
#define GPIO_PIN_PORT1_MASK                      (0x2U)
#define GPIO_PIN_PORT1_SHIFT                     (1U)
/*! PORT1 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT1_SHIFT)) & GPIO_PIN_PORT1_MASK)
#define GPIO_PIN_PORT2_MASK                      (0x4U)
#define GPIO_PIN_PORT2_SHIFT                     (2U)
/*! PORT2 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT2_SHIFT)) & GPIO_PIN_PORT2_MASK)
#define GPIO_PIN_PORT3_MASK                      (0x8U)
#define GPIO_PIN_PORT3_SHIFT                     (3U)
/*! PORT3 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT3_SHIFT)) & GPIO_PIN_PORT3_MASK)
#define GPIO_PIN_PORT4_MASK                      (0x10U)
#define GPIO_PIN_PORT4_SHIFT                     (4U)
/*! PORT4 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT4_SHIFT)) & GPIO_PIN_PORT4_MASK)
#define GPIO_PIN_PORT5_MASK                      (0x20U)
#define GPIO_PIN_PORT5_SHIFT                     (5U)
/*! PORT5 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT5_SHIFT)) & GPIO_PIN_PORT5_MASK)
#define GPIO_PIN_PORT6_MASK                      (0x40U)
#define GPIO_PIN_PORT6_SHIFT                     (6U)
/*! PORT6 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT6_SHIFT)) & GPIO_PIN_PORT6_MASK)
#define GPIO_PIN_PORT7_MASK                      (0x80U)
#define GPIO_PIN_PORT7_SHIFT                     (7U)
/*! PORT7 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT7_SHIFT)) & GPIO_PIN_PORT7_MASK)
#define GPIO_PIN_PORT8_MASK                      (0x100U)
#define GPIO_PIN_PORT8_SHIFT                     (8U)
/*! PORT8 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT8_SHIFT)) & GPIO_PIN_PORT8_MASK)
#define GPIO_PIN_PORT9_MASK                      (0x200U)
#define GPIO_PIN_PORT9_SHIFT                     (9U)
/*! PORT9 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT9_SHIFT)) & GPIO_PIN_PORT9_MASK)
#define GPIO_PIN_PORT10_MASK                     (0x400U)
#define GPIO_PIN_PORT10_SHIFT                    (10U)
/*! PORT10 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT10_SHIFT)) & GPIO_PIN_PORT10_MASK)
#define GPIO_PIN_PORT11_MASK                     (0x800U)
#define GPIO_PIN_PORT11_SHIFT                    (11U)
/*! PORT11 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT11_SHIFT)) & GPIO_PIN_PORT11_MASK)
#define GPIO_PIN_PORT12_MASK                     (0x1000U)
#define GPIO_PIN_PORT12_SHIFT                    (12U)
/*! PORT12 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT12_SHIFT)) & GPIO_PIN_PORT12_MASK)
#define GPIO_PIN_PORT13_MASK                     (0x2000U)
#define GPIO_PIN_PORT13_SHIFT                    (13U)
/*! PORT13 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT13_SHIFT)) & GPIO_PIN_PORT13_MASK)
#define GPIO_PIN_PORT14_MASK                     (0x4000U)
#define GPIO_PIN_PORT14_SHIFT                    (14U)
/*! PORT14 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT14_SHIFT)) & GPIO_PIN_PORT14_MASK)
#define GPIO_PIN_PORT15_MASK                     (0x8000U)
#define GPIO_PIN_PORT15_SHIFT                    (15U)
/*! PORT15 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT15_SHIFT)) & GPIO_PIN_PORT15_MASK)
#define GPIO_PIN_PORT16_MASK                     (0x10000U)
#define GPIO_PIN_PORT16_SHIFT                    (16U)
/*! PORT16 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT16_SHIFT)) & GPIO_PIN_PORT16_MASK)
#define GPIO_PIN_PORT17_MASK                     (0x20000U)
#define GPIO_PIN_PORT17_SHIFT                    (17U)
/*! PORT17 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT17_SHIFT)) & GPIO_PIN_PORT17_MASK)
#define GPIO_PIN_PORT18_MASK                     (0x40000U)
#define GPIO_PIN_PORT18_SHIFT                    (18U)
/*! PORT18 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT18_SHIFT)) & GPIO_PIN_PORT18_MASK)
#define GPIO_PIN_PORT19_MASK                     (0x80000U)
#define GPIO_PIN_PORT19_SHIFT                    (19U)
/*! PORT19 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT19_SHIFT)) & GPIO_PIN_PORT19_MASK)
#define GPIO_PIN_PORT20_MASK                     (0x100000U)
#define GPIO_PIN_PORT20_SHIFT                    (20U)
/*! PORT20 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT20_SHIFT)) & GPIO_PIN_PORT20_MASK)
#define GPIO_PIN_PORT21_MASK                     (0x200000U)
#define GPIO_PIN_PORT21_SHIFT                    (21U)
/*! PORT21 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT21_SHIFT)) & GPIO_PIN_PORT21_MASK)
#define GPIO_PIN_PORT22_MASK                     (0x400000U)
#define GPIO_PIN_PORT22_SHIFT                    (22U)
/*! PORT22 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT22_SHIFT)) & GPIO_PIN_PORT22_MASK)
#define GPIO_PIN_PORT23_MASK                     (0x800000U)
#define GPIO_PIN_PORT23_SHIFT                    (23U)
/*! PORT23 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT23_SHIFT)) & GPIO_PIN_PORT23_MASK)
#define GPIO_PIN_PORT24_MASK                     (0x1000000U)
#define GPIO_PIN_PORT24_SHIFT                    (24U)
/*! PORT24 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT24_SHIFT)) & GPIO_PIN_PORT24_MASK)
#define GPIO_PIN_PORT25_MASK                     (0x2000000U)
#define GPIO_PIN_PORT25_SHIFT                    (25U)
/*! PORT25 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT25_SHIFT)) & GPIO_PIN_PORT25_MASK)
#define GPIO_PIN_PORT26_MASK                     (0x4000000U)
#define GPIO_PIN_PORT26_SHIFT                    (26U)
/*! PORT26 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT26_SHIFT)) & GPIO_PIN_PORT26_MASK)
#define GPIO_PIN_PORT27_MASK                     (0x8000000U)
#define GPIO_PIN_PORT27_SHIFT                    (27U)
/*! PORT27 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT27_SHIFT)) & GPIO_PIN_PORT27_MASK)
#define GPIO_PIN_PORT28_MASK                     (0x10000000U)
#define GPIO_PIN_PORT28_SHIFT                    (28U)
/*! PORT28 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT28_SHIFT)) & GPIO_PIN_PORT28_MASK)
#define GPIO_PIN_PORT29_MASK                     (0x20000000U)
#define GPIO_PIN_PORT29_SHIFT                    (29U)
/*! PORT29 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT29_SHIFT)) & GPIO_PIN_PORT29_MASK)
#define GPIO_PIN_PORT30_MASK                     (0x40000000U)
#define GPIO_PIN_PORT30_SHIFT                    (30U)
/*! PORT30 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT30_SHIFT)) & GPIO_PIN_PORT30_MASK)
#define GPIO_PIN_PORT31_MASK                     (0x80000000U)
#define GPIO_PIN_PORT31_SHIFT                    (31U)
/*! PORT31 - Port pins
 *  0b0..Read- pin is low; Write- clear output bit
 *  0b1..Read- pin is high; Write- set output bit
 */
#define GPIO_PIN_PORT31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT31_SHIFT)) & GPIO_PIN_PORT31_MASK)
/*! @} */

/* The count of GPIO_PIN */
#define GPIO_PIN_COUNT                           (8U)

/*! @name MPIN - Masked Port Pin */
/*! @{ */
#define GPIO_MPIN_MPORTP0_MASK                   (0x1U)
#define GPIO_MPIN_MPORTP0_SHIFT                  (0U)
/*! MPORTP0 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP0(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP0_SHIFT)) & GPIO_MPIN_MPORTP0_MASK)
#define GPIO_MPIN_MPORTP1_MASK                   (0x2U)
#define GPIO_MPIN_MPORTP1_SHIFT                  (1U)
/*! MPORTP1 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP1(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP1_SHIFT)) & GPIO_MPIN_MPORTP1_MASK)
#define GPIO_MPIN_MPORTP2_MASK                   (0x4U)
#define GPIO_MPIN_MPORTP2_SHIFT                  (2U)
/*! MPORTP2 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP2(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP2_SHIFT)) & GPIO_MPIN_MPORTP2_MASK)
#define GPIO_MPIN_MPORTP3_MASK                   (0x8U)
#define GPIO_MPIN_MPORTP3_SHIFT                  (3U)
/*! MPORTP3 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP3(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP3_SHIFT)) & GPIO_MPIN_MPORTP3_MASK)
#define GPIO_MPIN_MPORTP4_MASK                   (0x10U)
#define GPIO_MPIN_MPORTP4_SHIFT                  (4U)
/*! MPORTP4 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP4(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP4_SHIFT)) & GPIO_MPIN_MPORTP4_MASK)
#define GPIO_MPIN_MPORTP5_MASK                   (0x20U)
#define GPIO_MPIN_MPORTP5_SHIFT                  (5U)
/*! MPORTP5 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP5(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP5_SHIFT)) & GPIO_MPIN_MPORTP5_MASK)
#define GPIO_MPIN_MPORTP6_MASK                   (0x40U)
#define GPIO_MPIN_MPORTP6_SHIFT                  (6U)
/*! MPORTP6 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP6(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP6_SHIFT)) & GPIO_MPIN_MPORTP6_MASK)
#define GPIO_MPIN_MPORTP7_MASK                   (0x80U)
#define GPIO_MPIN_MPORTP7_SHIFT                  (7U)
/*! MPORTP7 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP7(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP7_SHIFT)) & GPIO_MPIN_MPORTP7_MASK)
#define GPIO_MPIN_MPORTP8_MASK                   (0x100U)
#define GPIO_MPIN_MPORTP8_SHIFT                  (8U)
/*! MPORTP8 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP8(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP8_SHIFT)) & GPIO_MPIN_MPORTP8_MASK)
#define GPIO_MPIN_MPORTP9_MASK                   (0x200U)
#define GPIO_MPIN_MPORTP9_SHIFT                  (9U)
/*! MPORTP9 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP9(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP9_SHIFT)) & GPIO_MPIN_MPORTP9_MASK)
#define GPIO_MPIN_MPORTP10_MASK                  (0x400U)
#define GPIO_MPIN_MPORTP10_SHIFT                 (10U)
/*! MPORTP10 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP10(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP10_SHIFT)) & GPIO_MPIN_MPORTP10_MASK)
#define GPIO_MPIN_MPORTP11_MASK                  (0x800U)
#define GPIO_MPIN_MPORTP11_SHIFT                 (11U)
/*! MPORTP11 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP11(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP11_SHIFT)) & GPIO_MPIN_MPORTP11_MASK)
#define GPIO_MPIN_MPORTP12_MASK                  (0x1000U)
#define GPIO_MPIN_MPORTP12_SHIFT                 (12U)
/*! MPORTP12 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP12(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP12_SHIFT)) & GPIO_MPIN_MPORTP12_MASK)
#define GPIO_MPIN_MPORTP13_MASK                  (0x2000U)
#define GPIO_MPIN_MPORTP13_SHIFT                 (13U)
/*! MPORTP13 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP13(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP13_SHIFT)) & GPIO_MPIN_MPORTP13_MASK)
#define GPIO_MPIN_MPORTP14_MASK                  (0x4000U)
#define GPIO_MPIN_MPORTP14_SHIFT                 (14U)
/*! MPORTP14 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP14(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP14_SHIFT)) & GPIO_MPIN_MPORTP14_MASK)
#define GPIO_MPIN_MPORTP15_MASK                  (0x8000U)
#define GPIO_MPIN_MPORTP15_SHIFT                 (15U)
/*! MPORTP15 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP15(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP15_SHIFT)) & GPIO_MPIN_MPORTP15_MASK)
#define GPIO_MPIN_MPORTP16_MASK                  (0x10000U)
#define GPIO_MPIN_MPORTP16_SHIFT                 (16U)
/*! MPORTP16 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP16(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP16_SHIFT)) & GPIO_MPIN_MPORTP16_MASK)
#define GPIO_MPIN_MPORTP17_MASK                  (0x20000U)
#define GPIO_MPIN_MPORTP17_SHIFT                 (17U)
/*! MPORTP17 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP17(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP17_SHIFT)) & GPIO_MPIN_MPORTP17_MASK)
#define GPIO_MPIN_MPORTP18_MASK                  (0x40000U)
#define GPIO_MPIN_MPORTP18_SHIFT                 (18U)
/*! MPORTP18 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP18(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP18_SHIFT)) & GPIO_MPIN_MPORTP18_MASK)
#define GPIO_MPIN_MPORTP19_MASK                  (0x80000U)
#define GPIO_MPIN_MPORTP19_SHIFT                 (19U)
/*! MPORTP19 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP19(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP19_SHIFT)) & GPIO_MPIN_MPORTP19_MASK)
#define GPIO_MPIN_MPORTP20_MASK                  (0x100000U)
#define GPIO_MPIN_MPORTP20_SHIFT                 (20U)
/*! MPORTP20 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP20(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP20_SHIFT)) & GPIO_MPIN_MPORTP20_MASK)
#define GPIO_MPIN_MPORTP21_MASK                  (0x200000U)
#define GPIO_MPIN_MPORTP21_SHIFT                 (21U)
/*! MPORTP21 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP21(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP21_SHIFT)) & GPIO_MPIN_MPORTP21_MASK)
#define GPIO_MPIN_MPORTP22_MASK                  (0x400000U)
#define GPIO_MPIN_MPORTP22_SHIFT                 (22U)
/*! MPORTP22 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP22(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP22_SHIFT)) & GPIO_MPIN_MPORTP22_MASK)
#define GPIO_MPIN_MPORTP23_MASK                  (0x800000U)
#define GPIO_MPIN_MPORTP23_SHIFT                 (23U)
/*! MPORTP23 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP23(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP23_SHIFT)) & GPIO_MPIN_MPORTP23_MASK)
#define GPIO_MPIN_MPORTP24_MASK                  (0x1000000U)
#define GPIO_MPIN_MPORTP24_SHIFT                 (24U)
/*! MPORTP24 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP24(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP24_SHIFT)) & GPIO_MPIN_MPORTP24_MASK)
#define GPIO_MPIN_MPORTP25_MASK                  (0x2000000U)
#define GPIO_MPIN_MPORTP25_SHIFT                 (25U)
/*! MPORTP25 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP25(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP25_SHIFT)) & GPIO_MPIN_MPORTP25_MASK)
#define GPIO_MPIN_MPORTP26_MASK                  (0x4000000U)
#define GPIO_MPIN_MPORTP26_SHIFT                 (26U)
/*! MPORTP26 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP26(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP26_SHIFT)) & GPIO_MPIN_MPORTP26_MASK)
#define GPIO_MPIN_MPORTP27_MASK                  (0x8000000U)
#define GPIO_MPIN_MPORTP27_SHIFT                 (27U)
/*! MPORTP27 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP27(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP27_SHIFT)) & GPIO_MPIN_MPORTP27_MASK)
#define GPIO_MPIN_MPORTP28_MASK                  (0x10000000U)
#define GPIO_MPIN_MPORTP28_SHIFT                 (28U)
/*! MPORTP28 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP28(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP28_SHIFT)) & GPIO_MPIN_MPORTP28_MASK)
#define GPIO_MPIN_MPORTP29_MASK                  (0x20000000U)
#define GPIO_MPIN_MPORTP29_SHIFT                 (29U)
/*! MPORTP29 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP29(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP29_SHIFT)) & GPIO_MPIN_MPORTP29_MASK)
#define GPIO_MPIN_MPORTP30_MASK                  (0x40000000U)
#define GPIO_MPIN_MPORTP30_SHIFT                 (30U)
/*! MPORTP30 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP30(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP30_SHIFT)) & GPIO_MPIN_MPORTP30_MASK)
#define GPIO_MPIN_MPORTP31_MASK                  (0x80000000U)
#define GPIO_MPIN_MPORTP31_SHIFT                 (31U)
/*! MPORTP31 - Mask bits for port pins
 *  0b0..Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear output bit if the
 *       corresponding bit in the MASK register is 0
 *  0b1..Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set output bit if the
 *       corresponding bit in the MASK register is 0
 */
#define GPIO_MPIN_MPORTP31(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP31_SHIFT)) & GPIO_MPIN_MPORTP31_MASK)
/*! @} */

/* The count of GPIO_MPIN */
#define GPIO_MPIN_COUNT                          (8U)

/*! @name SET - Port set */
/*! @{ */
#define GPIO_SET_SETP_MASK                       (0xFFFFFFFFU)
#define GPIO_SET_SETP_SHIFT                      (0U)
/*! SETP - Read or set output bits
 *  0b00000000000000000000000000000000..Read- output bit; write- no operation
 *  0b00000000000000000000000000000001..Read- output bit; write- set output bit
 */
#define GPIO_SET_SETP(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
/*! @} */

/* The count of GPIO_SET */
#define GPIO_SET_COUNT                           (8U)

/*! @name CLR - Port clear */
/*! @{ */
#define GPIO_CLR_CLRP0_MASK                      (0x1U)
#define GPIO_CLR_CLRP0_SHIFT                     (0U)
/*! CLRP0 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP0_SHIFT)) & GPIO_CLR_CLRP0_MASK)
#define GPIO_CLR_CLRP1_MASK                      (0x2U)
#define GPIO_CLR_CLRP1_SHIFT                     (1U)
/*! CLRP1 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP1_SHIFT)) & GPIO_CLR_CLRP1_MASK)
#define GPIO_CLR_CLRP2_MASK                      (0x4U)
#define GPIO_CLR_CLRP2_SHIFT                     (2U)
/*! CLRP2 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP2_SHIFT)) & GPIO_CLR_CLRP2_MASK)
#define GPIO_CLR_CLRP3_MASK                      (0x8U)
#define GPIO_CLR_CLRP3_SHIFT                     (3U)
/*! CLRP3 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP3_SHIFT)) & GPIO_CLR_CLRP3_MASK)
#define GPIO_CLR_CLRP4_MASK                      (0x10U)
#define GPIO_CLR_CLRP4_SHIFT                     (4U)
/*! CLRP4 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP4_SHIFT)) & GPIO_CLR_CLRP4_MASK)
#define GPIO_CLR_CLRP5_MASK                      (0x20U)
#define GPIO_CLR_CLRP5_SHIFT                     (5U)
/*! CLRP5 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP5_SHIFT)) & GPIO_CLR_CLRP5_MASK)
#define GPIO_CLR_CLRP6_MASK                      (0x40U)
#define GPIO_CLR_CLRP6_SHIFT                     (6U)
/*! CLRP6 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP6_SHIFT)) & GPIO_CLR_CLRP6_MASK)
#define GPIO_CLR_CLRP7_MASK                      (0x80U)
#define GPIO_CLR_CLRP7_SHIFT                     (7U)
/*! CLRP7 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP7_SHIFT)) & GPIO_CLR_CLRP7_MASK)
#define GPIO_CLR_CLRP8_MASK                      (0x100U)
#define GPIO_CLR_CLRP8_SHIFT                     (8U)
/*! CLRP8 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP8_SHIFT)) & GPIO_CLR_CLRP8_MASK)
#define GPIO_CLR_CLRP9_MASK                      (0x200U)
#define GPIO_CLR_CLRP9_SHIFT                     (9U)
/*! CLRP9 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP9_SHIFT)) & GPIO_CLR_CLRP9_MASK)
#define GPIO_CLR_CLRP10_MASK                     (0x400U)
#define GPIO_CLR_CLRP10_SHIFT                    (10U)
/*! CLRP10 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP10_SHIFT)) & GPIO_CLR_CLRP10_MASK)
#define GPIO_CLR_CLRP11_MASK                     (0x800U)
#define GPIO_CLR_CLRP11_SHIFT                    (11U)
/*! CLRP11 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP11_SHIFT)) & GPIO_CLR_CLRP11_MASK)
#define GPIO_CLR_CLRP12_MASK                     (0x1000U)
#define GPIO_CLR_CLRP12_SHIFT                    (12U)
/*! CLRP12 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP12_SHIFT)) & GPIO_CLR_CLRP12_MASK)
#define GPIO_CLR_CLRP13_MASK                     (0x2000U)
#define GPIO_CLR_CLRP13_SHIFT                    (13U)
/*! CLRP13 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP13_SHIFT)) & GPIO_CLR_CLRP13_MASK)
#define GPIO_CLR_CLRP14_MASK                     (0x4000U)
#define GPIO_CLR_CLRP14_SHIFT                    (14U)
/*! CLRP14 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP14_SHIFT)) & GPIO_CLR_CLRP14_MASK)
#define GPIO_CLR_CLRP15_MASK                     (0x8000U)
#define GPIO_CLR_CLRP15_SHIFT                    (15U)
/*! CLRP15 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP15_SHIFT)) & GPIO_CLR_CLRP15_MASK)
#define GPIO_CLR_CLRP16_MASK                     (0x10000U)
#define GPIO_CLR_CLRP16_SHIFT                    (16U)
/*! CLRP16 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP16_SHIFT)) & GPIO_CLR_CLRP16_MASK)
#define GPIO_CLR_CLRP17_MASK                     (0x20000U)
#define GPIO_CLR_CLRP17_SHIFT                    (17U)
/*! CLRP17 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP17_SHIFT)) & GPIO_CLR_CLRP17_MASK)
#define GPIO_CLR_CLRP18_MASK                     (0x40000U)
#define GPIO_CLR_CLRP18_SHIFT                    (18U)
/*! CLRP18 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP18_SHIFT)) & GPIO_CLR_CLRP18_MASK)
#define GPIO_CLR_CLRP19_MASK                     (0x80000U)
#define GPIO_CLR_CLRP19_SHIFT                    (19U)
/*! CLRP19 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP19_SHIFT)) & GPIO_CLR_CLRP19_MASK)
#define GPIO_CLR_CLRP20_MASK                     (0x100000U)
#define GPIO_CLR_CLRP20_SHIFT                    (20U)
/*! CLRP20 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP20_SHIFT)) & GPIO_CLR_CLRP20_MASK)
#define GPIO_CLR_CLRP21_MASK                     (0x200000U)
#define GPIO_CLR_CLRP21_SHIFT                    (21U)
/*! CLRP21 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP21_SHIFT)) & GPIO_CLR_CLRP21_MASK)
#define GPIO_CLR_CLRP22_MASK                     (0x400000U)
#define GPIO_CLR_CLRP22_SHIFT                    (22U)
/*! CLRP22 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP22_SHIFT)) & GPIO_CLR_CLRP22_MASK)
#define GPIO_CLR_CLRP23_MASK                     (0x800000U)
#define GPIO_CLR_CLRP23_SHIFT                    (23U)
/*! CLRP23 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP23_SHIFT)) & GPIO_CLR_CLRP23_MASK)
#define GPIO_CLR_CLRP24_MASK                     (0x1000000U)
#define GPIO_CLR_CLRP24_SHIFT                    (24U)
/*! CLRP24 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP24_SHIFT)) & GPIO_CLR_CLRP24_MASK)
#define GPIO_CLR_CLRP25_MASK                     (0x2000000U)
#define GPIO_CLR_CLRP25_SHIFT                    (25U)
/*! CLRP25 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP25_SHIFT)) & GPIO_CLR_CLRP25_MASK)
#define GPIO_CLR_CLRP26_MASK                     (0x4000000U)
#define GPIO_CLR_CLRP26_SHIFT                    (26U)
/*! CLRP26 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP26_SHIFT)) & GPIO_CLR_CLRP26_MASK)
#define GPIO_CLR_CLRP27_MASK                     (0x8000000U)
#define GPIO_CLR_CLRP27_SHIFT                    (27U)
/*! CLRP27 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP27_SHIFT)) & GPIO_CLR_CLRP27_MASK)
#define GPIO_CLR_CLRP28_MASK                     (0x10000000U)
#define GPIO_CLR_CLRP28_SHIFT                    (28U)
/*! CLRP28 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP28_SHIFT)) & GPIO_CLR_CLRP28_MASK)
#define GPIO_CLR_CLRP29_MASK                     (0x20000000U)
#define GPIO_CLR_CLRP29_SHIFT                    (29U)
/*! CLRP29 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP29_SHIFT)) & GPIO_CLR_CLRP29_MASK)
#define GPIO_CLR_CLRP30_MASK                     (0x40000000U)
#define GPIO_CLR_CLRP30_SHIFT                    (30U)
/*! CLRP30 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP30_SHIFT)) & GPIO_CLR_CLRP30_MASK)
#define GPIO_CLR_CLRP31_MASK                     (0x80000000U)
#define GPIO_CLR_CLRP31_SHIFT                    (31U)
/*! CLRP31 - Clear output bits
 *  0b0..No operation
 *  0b1..Clears output bit
 */
#define GPIO_CLR_CLRP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP31_SHIFT)) & GPIO_CLR_CLRP31_MASK)
/*! @} */

/* The count of GPIO_CLR */
#define GPIO_CLR_COUNT                           (8U)

/*! @name NOT - Port toggle */
/*! @{ */
#define GPIO_NOT_NOTP0_MASK                      (0x1U)
#define GPIO_NOT_NOTP0_SHIFT                     (0U)
/*! NOTP0 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP0_SHIFT)) & GPIO_NOT_NOTP0_MASK)
#define GPIO_NOT_NOTP1_MASK                      (0x2U)
#define GPIO_NOT_NOTP1_SHIFT                     (1U)
/*! NOTP1 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP1_SHIFT)) & GPIO_NOT_NOTP1_MASK)
#define GPIO_NOT_NOTP2_MASK                      (0x4U)
#define GPIO_NOT_NOTP2_SHIFT                     (2U)
/*! NOTP2 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP2_SHIFT)) & GPIO_NOT_NOTP2_MASK)
#define GPIO_NOT_NOTP3_MASK                      (0x8U)
#define GPIO_NOT_NOTP3_SHIFT                     (3U)
/*! NOTP3 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP3_SHIFT)) & GPIO_NOT_NOTP3_MASK)
#define GPIO_NOT_NOTP4_MASK                      (0x10U)
#define GPIO_NOT_NOTP4_SHIFT                     (4U)
/*! NOTP4 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP4_SHIFT)) & GPIO_NOT_NOTP4_MASK)
#define GPIO_NOT_NOTP5_MASK                      (0x20U)
#define GPIO_NOT_NOTP5_SHIFT                     (5U)
/*! NOTP5 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP5_SHIFT)) & GPIO_NOT_NOTP5_MASK)
#define GPIO_NOT_NOTP6_MASK                      (0x40U)
#define GPIO_NOT_NOTP6_SHIFT                     (6U)
/*! NOTP6 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP6_SHIFT)) & GPIO_NOT_NOTP6_MASK)
#define GPIO_NOT_NOTP7_MASK                      (0x80U)
#define GPIO_NOT_NOTP7_SHIFT                     (7U)
/*! NOTP7 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP7_SHIFT)) & GPIO_NOT_NOTP7_MASK)
#define GPIO_NOT_NOTP8_MASK                      (0x100U)
#define GPIO_NOT_NOTP8_SHIFT                     (8U)
/*! NOTP8 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP8_SHIFT)) & GPIO_NOT_NOTP8_MASK)
#define GPIO_NOT_NOTP9_MASK                      (0x200U)
#define GPIO_NOT_NOTP9_SHIFT                     (9U)
/*! NOTP9 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP9_SHIFT)) & GPIO_NOT_NOTP9_MASK)
#define GPIO_NOT_NOTP10_MASK                     (0x400U)
#define GPIO_NOT_NOTP10_SHIFT                    (10U)
/*! NOTP10 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP10_SHIFT)) & GPIO_NOT_NOTP10_MASK)
#define GPIO_NOT_NOTP11_MASK                     (0x800U)
#define GPIO_NOT_NOTP11_SHIFT                    (11U)
/*! NOTP11 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP11_SHIFT)) & GPIO_NOT_NOTP11_MASK)
#define GPIO_NOT_NOTP12_MASK                     (0x1000U)
#define GPIO_NOT_NOTP12_SHIFT                    (12U)
/*! NOTP12 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP12_SHIFT)) & GPIO_NOT_NOTP12_MASK)
#define GPIO_NOT_NOTP13_MASK                     (0x2000U)
#define GPIO_NOT_NOTP13_SHIFT                    (13U)
/*! NOTP13 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP13_SHIFT)) & GPIO_NOT_NOTP13_MASK)
#define GPIO_NOT_NOTP14_MASK                     (0x4000U)
#define GPIO_NOT_NOTP14_SHIFT                    (14U)
/*! NOTP14 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP14_SHIFT)) & GPIO_NOT_NOTP14_MASK)
#define GPIO_NOT_NOTP15_MASK                     (0x8000U)
#define GPIO_NOT_NOTP15_SHIFT                    (15U)
/*! NOTP15 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP15_SHIFT)) & GPIO_NOT_NOTP15_MASK)
#define GPIO_NOT_NOTP16_MASK                     (0x10000U)
#define GPIO_NOT_NOTP16_SHIFT                    (16U)
/*! NOTP16 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP16_SHIFT)) & GPIO_NOT_NOTP16_MASK)
#define GPIO_NOT_NOTP17_MASK                     (0x20000U)
#define GPIO_NOT_NOTP17_SHIFT                    (17U)
/*! NOTP17 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP17_SHIFT)) & GPIO_NOT_NOTP17_MASK)
#define GPIO_NOT_NOTP18_MASK                     (0x40000U)
#define GPIO_NOT_NOTP18_SHIFT                    (18U)
/*! NOTP18 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP18_SHIFT)) & GPIO_NOT_NOTP18_MASK)
#define GPIO_NOT_NOTP19_MASK                     (0x80000U)
#define GPIO_NOT_NOTP19_SHIFT                    (19U)
/*! NOTP19 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP19_SHIFT)) & GPIO_NOT_NOTP19_MASK)
#define GPIO_NOT_NOTP20_MASK                     (0x100000U)
#define GPIO_NOT_NOTP20_SHIFT                    (20U)
/*! NOTP20 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP20_SHIFT)) & GPIO_NOT_NOTP20_MASK)
#define GPIO_NOT_NOTP21_MASK                     (0x200000U)
#define GPIO_NOT_NOTP21_SHIFT                    (21U)
/*! NOTP21 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP21_SHIFT)) & GPIO_NOT_NOTP21_MASK)
#define GPIO_NOT_NOTP22_MASK                     (0x400000U)
#define GPIO_NOT_NOTP22_SHIFT                    (22U)
/*! NOTP22 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP22_SHIFT)) & GPIO_NOT_NOTP22_MASK)
#define GPIO_NOT_NOTP23_MASK                     (0x800000U)
#define GPIO_NOT_NOTP23_SHIFT                    (23U)
/*! NOTP23 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP23_SHIFT)) & GPIO_NOT_NOTP23_MASK)
#define GPIO_NOT_NOTP24_MASK                     (0x1000000U)
#define GPIO_NOT_NOTP24_SHIFT                    (24U)
/*! NOTP24 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP24_SHIFT)) & GPIO_NOT_NOTP24_MASK)
#define GPIO_NOT_NOTP25_MASK                     (0x2000000U)
#define GPIO_NOT_NOTP25_SHIFT                    (25U)
/*! NOTP25 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP25_SHIFT)) & GPIO_NOT_NOTP25_MASK)
#define GPIO_NOT_NOTP26_MASK                     (0x4000000U)
#define GPIO_NOT_NOTP26_SHIFT                    (26U)
/*! NOTP26 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP26_SHIFT)) & GPIO_NOT_NOTP26_MASK)
#define GPIO_NOT_NOTP27_MASK                     (0x8000000U)
#define GPIO_NOT_NOTP27_SHIFT                    (27U)
/*! NOTP27 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP27_SHIFT)) & GPIO_NOT_NOTP27_MASK)
#define GPIO_NOT_NOTP28_MASK                     (0x10000000U)
#define GPIO_NOT_NOTP28_SHIFT                    (28U)
/*! NOTP28 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP28_SHIFT)) & GPIO_NOT_NOTP28_MASK)
#define GPIO_NOT_NOTP29_MASK                     (0x20000000U)
#define GPIO_NOT_NOTP29_SHIFT                    (29U)
/*! NOTP29 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP29_SHIFT)) & GPIO_NOT_NOTP29_MASK)
#define GPIO_NOT_NOTP30_MASK                     (0x40000000U)
#define GPIO_NOT_NOTP30_SHIFT                    (30U)
/*! NOTP30 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP30_SHIFT)) & GPIO_NOT_NOTP30_MASK)
#define GPIO_NOT_NOTP31_MASK                     (0x80000000U)
#define GPIO_NOT_NOTP31_SHIFT                    (31U)
/*! NOTP31 - Toggle output bits
 *  0b0..No operation
 *  0b1..Toggle output bit
 */
#define GPIO_NOT_NOTP31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP31_SHIFT)) & GPIO_NOT_NOTP31_MASK)
/*! @} */

/* The count of GPIO_NOT */
#define GPIO_NOT_COUNT                           (8U)

/*! @name DIRSET - Port direction set */
/*! @{ */
#define GPIO_DIRSET_DIRSETP0_MASK                (0x1U)
#define GPIO_DIRSET_DIRSETP0_SHIFT               (0U)
/*! DIRSETP0 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP0_SHIFT)) & GPIO_DIRSET_DIRSETP0_MASK)
#define GPIO_DIRSET_DIRSETP1_MASK                (0x2U)
#define GPIO_DIRSET_DIRSETP1_SHIFT               (1U)
/*! DIRSETP1 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP1_SHIFT)) & GPIO_DIRSET_DIRSETP1_MASK)
#define GPIO_DIRSET_DIRSETP2_MASK                (0x4U)
#define GPIO_DIRSET_DIRSETP2_SHIFT               (2U)
/*! DIRSETP2 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP2_SHIFT)) & GPIO_DIRSET_DIRSETP2_MASK)
#define GPIO_DIRSET_DIRSETP3_MASK                (0x8U)
#define GPIO_DIRSET_DIRSETP3_SHIFT               (3U)
/*! DIRSETP3 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP3_SHIFT)) & GPIO_DIRSET_DIRSETP3_MASK)
#define GPIO_DIRSET_DIRSETP4_MASK                (0x10U)
#define GPIO_DIRSET_DIRSETP4_SHIFT               (4U)
/*! DIRSETP4 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP4_SHIFT)) & GPIO_DIRSET_DIRSETP4_MASK)
#define GPIO_DIRSET_DIRSETP5_MASK                (0x20U)
#define GPIO_DIRSET_DIRSETP5_SHIFT               (5U)
/*! DIRSETP5 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP5_SHIFT)) & GPIO_DIRSET_DIRSETP5_MASK)
#define GPIO_DIRSET_DIRSETP6_MASK                (0x40U)
#define GPIO_DIRSET_DIRSETP6_SHIFT               (6U)
/*! DIRSETP6 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP6_SHIFT)) & GPIO_DIRSET_DIRSETP6_MASK)
#define GPIO_DIRSET_DIRSETP7_MASK                (0x80U)
#define GPIO_DIRSET_DIRSETP7_SHIFT               (7U)
/*! DIRSETP7 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP7_SHIFT)) & GPIO_DIRSET_DIRSETP7_MASK)
#define GPIO_DIRSET_DIRSETP8_MASK                (0x100U)
#define GPIO_DIRSET_DIRSETP8_SHIFT               (8U)
/*! DIRSETP8 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP8_SHIFT)) & GPIO_DIRSET_DIRSETP8_MASK)
#define GPIO_DIRSET_DIRSETP9_MASK                (0x200U)
#define GPIO_DIRSET_DIRSETP9_SHIFT               (9U)
/*! DIRSETP9 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP9_SHIFT)) & GPIO_DIRSET_DIRSETP9_MASK)
#define GPIO_DIRSET_DIRSETP10_MASK               (0x400U)
#define GPIO_DIRSET_DIRSETP10_SHIFT              (10U)
/*! DIRSETP10 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP10_SHIFT)) & GPIO_DIRSET_DIRSETP10_MASK)
#define GPIO_DIRSET_DIRSETP11_MASK               (0x800U)
#define GPIO_DIRSET_DIRSETP11_SHIFT              (11U)
/*! DIRSETP11 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP11_SHIFT)) & GPIO_DIRSET_DIRSETP11_MASK)
#define GPIO_DIRSET_DIRSETP12_MASK               (0x1000U)
#define GPIO_DIRSET_DIRSETP12_SHIFT              (12U)
/*! DIRSETP12 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP12_SHIFT)) & GPIO_DIRSET_DIRSETP12_MASK)
#define GPIO_DIRSET_DIRSETP13_MASK               (0x2000U)
#define GPIO_DIRSET_DIRSETP13_SHIFT              (13U)
/*! DIRSETP13 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP13_SHIFT)) & GPIO_DIRSET_DIRSETP13_MASK)
#define GPIO_DIRSET_DIRSETP14_MASK               (0x4000U)
#define GPIO_DIRSET_DIRSETP14_SHIFT              (14U)
/*! DIRSETP14 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP14_SHIFT)) & GPIO_DIRSET_DIRSETP14_MASK)
#define GPIO_DIRSET_DIRSETP15_MASK               (0x8000U)
#define GPIO_DIRSET_DIRSETP15_SHIFT              (15U)
/*! DIRSETP15 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP15_SHIFT)) & GPIO_DIRSET_DIRSETP15_MASK)
#define GPIO_DIRSET_DIRSETP16_MASK               (0x10000U)
#define GPIO_DIRSET_DIRSETP16_SHIFT              (16U)
/*! DIRSETP16 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP16_SHIFT)) & GPIO_DIRSET_DIRSETP16_MASK)
#define GPIO_DIRSET_DIRSETP17_MASK               (0x20000U)
#define GPIO_DIRSET_DIRSETP17_SHIFT              (17U)
/*! DIRSETP17 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP17_SHIFT)) & GPIO_DIRSET_DIRSETP17_MASK)
#define GPIO_DIRSET_DIRSETP18_MASK               (0x40000U)
#define GPIO_DIRSET_DIRSETP18_SHIFT              (18U)
/*! DIRSETP18 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP18_SHIFT)) & GPIO_DIRSET_DIRSETP18_MASK)
#define GPIO_DIRSET_DIRSETP19_MASK               (0x80000U)
#define GPIO_DIRSET_DIRSETP19_SHIFT              (19U)
/*! DIRSETP19 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP19_SHIFT)) & GPIO_DIRSET_DIRSETP19_MASK)
#define GPIO_DIRSET_DIRSETP20_MASK               (0x100000U)
#define GPIO_DIRSET_DIRSETP20_SHIFT              (20U)
/*! DIRSETP20 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP20_SHIFT)) & GPIO_DIRSET_DIRSETP20_MASK)
#define GPIO_DIRSET_DIRSETP21_MASK               (0x200000U)
#define GPIO_DIRSET_DIRSETP21_SHIFT              (21U)
/*! DIRSETP21 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP21_SHIFT)) & GPIO_DIRSET_DIRSETP21_MASK)
#define GPIO_DIRSET_DIRSETP22_MASK               (0x400000U)
#define GPIO_DIRSET_DIRSETP22_SHIFT              (22U)
/*! DIRSETP22 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP22_SHIFT)) & GPIO_DIRSET_DIRSETP22_MASK)
#define GPIO_DIRSET_DIRSETP23_MASK               (0x800000U)
#define GPIO_DIRSET_DIRSETP23_SHIFT              (23U)
/*! DIRSETP23 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP23_SHIFT)) & GPIO_DIRSET_DIRSETP23_MASK)
#define GPIO_DIRSET_DIRSETP24_MASK               (0x1000000U)
#define GPIO_DIRSET_DIRSETP24_SHIFT              (24U)
/*! DIRSETP24 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP24_SHIFT)) & GPIO_DIRSET_DIRSETP24_MASK)
#define GPIO_DIRSET_DIRSETP25_MASK               (0x2000000U)
#define GPIO_DIRSET_DIRSETP25_SHIFT              (25U)
/*! DIRSETP25 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP25_SHIFT)) & GPIO_DIRSET_DIRSETP25_MASK)
#define GPIO_DIRSET_DIRSETP26_MASK               (0x4000000U)
#define GPIO_DIRSET_DIRSETP26_SHIFT              (26U)
/*! DIRSETP26 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP26_SHIFT)) & GPIO_DIRSET_DIRSETP26_MASK)
#define GPIO_DIRSET_DIRSETP27_MASK               (0x8000000U)
#define GPIO_DIRSET_DIRSETP27_SHIFT              (27U)
/*! DIRSETP27 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP27_SHIFT)) & GPIO_DIRSET_DIRSETP27_MASK)
#define GPIO_DIRSET_DIRSETP28_MASK               (0x10000000U)
#define GPIO_DIRSET_DIRSETP28_SHIFT              (28U)
/*! DIRSETP28 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP28_SHIFT)) & GPIO_DIRSET_DIRSETP28_MASK)
#define GPIO_DIRSET_DIRSETP29_MASK               (0x20000000U)
#define GPIO_DIRSET_DIRSETP29_SHIFT              (29U)
/*! DIRSETP29 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP29_SHIFT)) & GPIO_DIRSET_DIRSETP29_MASK)
#define GPIO_DIRSET_DIRSETP30_MASK               (0x40000000U)
#define GPIO_DIRSET_DIRSETP30_SHIFT              (30U)
/*! DIRSETP30 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP30_SHIFT)) & GPIO_DIRSET_DIRSETP30_MASK)
#define GPIO_DIRSET_DIRSETP31_MASK               (0x80000000U)
#define GPIO_DIRSET_DIRSETP31_SHIFT              (31U)
/*! DIRSETP31 - Direction set bits for Port pins
 *  0b0..No operation
 *  0b1..Sets direction bit
 */
#define GPIO_DIRSET_DIRSETP31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP31_SHIFT)) & GPIO_DIRSET_DIRSETP31_MASK)
/*! @} */

/* The count of GPIO_DIRSET */
#define GPIO_DIRSET_COUNT                        (8U)

/*! @name DIRCLR - Port direction clear */
/*! @{ */
#define GPIO_DIRCLR_DIRCLRP0_MASK                (0x1U)
#define GPIO_DIRCLR_DIRCLRP0_SHIFT               (0U)
/*! DIRCLRP0 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP0_SHIFT)) & GPIO_DIRCLR_DIRCLRP0_MASK)
#define GPIO_DIRCLR_DIRCLRP1_MASK                (0x2U)
#define GPIO_DIRCLR_DIRCLRP1_SHIFT               (1U)
/*! DIRCLRP1 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP1_SHIFT)) & GPIO_DIRCLR_DIRCLRP1_MASK)
#define GPIO_DIRCLR_DIRCLRP2_MASK                (0x4U)
#define GPIO_DIRCLR_DIRCLRP2_SHIFT               (2U)
/*! DIRCLRP2 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP2_SHIFT)) & GPIO_DIRCLR_DIRCLRP2_MASK)
#define GPIO_DIRCLR_DIRCLRP3_MASK                (0x8U)
#define GPIO_DIRCLR_DIRCLRP3_SHIFT               (3U)
/*! DIRCLRP3 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP3_SHIFT)) & GPIO_DIRCLR_DIRCLRP3_MASK)
#define GPIO_DIRCLR_DIRCLRP4_MASK                (0x10U)
#define GPIO_DIRCLR_DIRCLRP4_SHIFT               (4U)
/*! DIRCLRP4 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP4_SHIFT)) & GPIO_DIRCLR_DIRCLRP4_MASK)
#define GPIO_DIRCLR_DIRCLRP5_MASK                (0x20U)
#define GPIO_DIRCLR_DIRCLRP5_SHIFT               (5U)
/*! DIRCLRP5 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP5_SHIFT)) & GPIO_DIRCLR_DIRCLRP5_MASK)
#define GPIO_DIRCLR_DIRCLRP6_MASK                (0x40U)
#define GPIO_DIRCLR_DIRCLRP6_SHIFT               (6U)
/*! DIRCLRP6 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP6_SHIFT)) & GPIO_DIRCLR_DIRCLRP6_MASK)
#define GPIO_DIRCLR_DIRCLRP7_MASK                (0x80U)
#define GPIO_DIRCLR_DIRCLRP7_SHIFT               (7U)
/*! DIRCLRP7 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP7_SHIFT)) & GPIO_DIRCLR_DIRCLRP7_MASK)
#define GPIO_DIRCLR_DIRCLRP8_MASK                (0x100U)
#define GPIO_DIRCLR_DIRCLRP8_SHIFT               (8U)
/*! DIRCLRP8 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP8_SHIFT)) & GPIO_DIRCLR_DIRCLRP8_MASK)
#define GPIO_DIRCLR_DIRCLRP9_MASK                (0x200U)
#define GPIO_DIRCLR_DIRCLRP9_SHIFT               (9U)
/*! DIRCLRP9 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP9_SHIFT)) & GPIO_DIRCLR_DIRCLRP9_MASK)
#define GPIO_DIRCLR_DIRCLRP10_MASK               (0x400U)
#define GPIO_DIRCLR_DIRCLRP10_SHIFT              (10U)
/*! DIRCLRP10 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP10_SHIFT)) & GPIO_DIRCLR_DIRCLRP10_MASK)
#define GPIO_DIRCLR_DIRCLRP11_MASK               (0x800U)
#define GPIO_DIRCLR_DIRCLRP11_SHIFT              (11U)
/*! DIRCLRP11 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP11_SHIFT)) & GPIO_DIRCLR_DIRCLRP11_MASK)
#define GPIO_DIRCLR_DIRCLRP12_MASK               (0x1000U)
#define GPIO_DIRCLR_DIRCLRP12_SHIFT              (12U)
/*! DIRCLRP12 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP12_SHIFT)) & GPIO_DIRCLR_DIRCLRP12_MASK)
#define GPIO_DIRCLR_DIRCLRP13_MASK               (0x2000U)
#define GPIO_DIRCLR_DIRCLRP13_SHIFT              (13U)
/*! DIRCLRP13 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP13_SHIFT)) & GPIO_DIRCLR_DIRCLRP13_MASK)
#define GPIO_DIRCLR_DIRCLRP14_MASK               (0x4000U)
#define GPIO_DIRCLR_DIRCLRP14_SHIFT              (14U)
/*! DIRCLRP14 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP14_SHIFT)) & GPIO_DIRCLR_DIRCLRP14_MASK)
#define GPIO_DIRCLR_DIRCLRP15_MASK               (0x8000U)
#define GPIO_DIRCLR_DIRCLRP15_SHIFT              (15U)
/*! DIRCLRP15 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP15_SHIFT)) & GPIO_DIRCLR_DIRCLRP15_MASK)
#define GPIO_DIRCLR_DIRCLRP16_MASK               (0x10000U)
#define GPIO_DIRCLR_DIRCLRP16_SHIFT              (16U)
/*! DIRCLRP16 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP16_SHIFT)) & GPIO_DIRCLR_DIRCLRP16_MASK)
#define GPIO_DIRCLR_DIRCLRP17_MASK               (0x20000U)
#define GPIO_DIRCLR_DIRCLRP17_SHIFT              (17U)
/*! DIRCLRP17 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP17_SHIFT)) & GPIO_DIRCLR_DIRCLRP17_MASK)
#define GPIO_DIRCLR_DIRCLRP18_MASK               (0x40000U)
#define GPIO_DIRCLR_DIRCLRP18_SHIFT              (18U)
/*! DIRCLRP18 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP18_SHIFT)) & GPIO_DIRCLR_DIRCLRP18_MASK)
#define GPIO_DIRCLR_DIRCLRP19_MASK               (0x80000U)
#define GPIO_DIRCLR_DIRCLRP19_SHIFT              (19U)
/*! DIRCLRP19 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP19_SHIFT)) & GPIO_DIRCLR_DIRCLRP19_MASK)
#define GPIO_DIRCLR_DIRCLRP20_MASK               (0x100000U)
#define GPIO_DIRCLR_DIRCLRP20_SHIFT              (20U)
/*! DIRCLRP20 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP20_SHIFT)) & GPIO_DIRCLR_DIRCLRP20_MASK)
#define GPIO_DIRCLR_DIRCLRP21_MASK               (0x200000U)
#define GPIO_DIRCLR_DIRCLRP21_SHIFT              (21U)
/*! DIRCLRP21 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP21_SHIFT)) & GPIO_DIRCLR_DIRCLRP21_MASK)
#define GPIO_DIRCLR_DIRCLRP22_MASK               (0x400000U)
#define GPIO_DIRCLR_DIRCLRP22_SHIFT              (22U)
/*! DIRCLRP22 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP22_SHIFT)) & GPIO_DIRCLR_DIRCLRP22_MASK)
#define GPIO_DIRCLR_DIRCLRP23_MASK               (0x800000U)
#define GPIO_DIRCLR_DIRCLRP23_SHIFT              (23U)
/*! DIRCLRP23 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP23_SHIFT)) & GPIO_DIRCLR_DIRCLRP23_MASK)
#define GPIO_DIRCLR_DIRCLRP24_MASK               (0x1000000U)
#define GPIO_DIRCLR_DIRCLRP24_SHIFT              (24U)
/*! DIRCLRP24 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP24_SHIFT)) & GPIO_DIRCLR_DIRCLRP24_MASK)
#define GPIO_DIRCLR_DIRCLRP25_MASK               (0x2000000U)
#define GPIO_DIRCLR_DIRCLRP25_SHIFT              (25U)
/*! DIRCLRP25 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP25_SHIFT)) & GPIO_DIRCLR_DIRCLRP25_MASK)
#define GPIO_DIRCLR_DIRCLRP26_MASK               (0x4000000U)
#define GPIO_DIRCLR_DIRCLRP26_SHIFT              (26U)
/*! DIRCLRP26 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP26_SHIFT)) & GPIO_DIRCLR_DIRCLRP26_MASK)
#define GPIO_DIRCLR_DIRCLRP27_MASK               (0x8000000U)
#define GPIO_DIRCLR_DIRCLRP27_SHIFT              (27U)
/*! DIRCLRP27 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP27_SHIFT)) & GPIO_DIRCLR_DIRCLRP27_MASK)
#define GPIO_DIRCLR_DIRCLRP28_MASK               (0x10000000U)
#define GPIO_DIRCLR_DIRCLRP28_SHIFT              (28U)
/*! DIRCLRP28 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP28_SHIFT)) & GPIO_DIRCLR_DIRCLRP28_MASK)
#define GPIO_DIRCLR_DIRCLRP29_MASK               (0x20000000U)
#define GPIO_DIRCLR_DIRCLRP29_SHIFT              (29U)
/*! DIRCLRP29 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP29_SHIFT)) & GPIO_DIRCLR_DIRCLRP29_MASK)
#define GPIO_DIRCLR_DIRCLRP30_MASK               (0x40000000U)
#define GPIO_DIRCLR_DIRCLRP30_SHIFT              (30U)
/*! DIRCLRP30 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP30_SHIFT)) & GPIO_DIRCLR_DIRCLRP30_MASK)
#define GPIO_DIRCLR_DIRCLRP31_MASK               (0x80000000U)
#define GPIO_DIRCLR_DIRCLRP31_SHIFT              (31U)
/*! DIRCLRP31 - Clear direction bits.
 *  0b0..No operation
 *  0b1..Clears direction bits
 */
#define GPIO_DIRCLR_DIRCLRP31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP31_SHIFT)) & GPIO_DIRCLR_DIRCLRP31_MASK)
/*! @} */

/* The count of GPIO_DIRCLR */
#define GPIO_DIRCLR_COUNT                        (8U)

/*! @name DIRNOT - Port direction toggle */
/*! @{ */
#define GPIO_DIRNOT_DIRNOTP_MASK                 (0x1FFFFFFFU)
#define GPIO_DIRNOT_DIRNOTP_SHIFT                (0U)
/*! DIRNOTP - Toggle direction bits.
 *  0b00000000000000000000000000000..No operation
 *  0b00000000000000000000000000001..Toggles direction bit
 */
#define GPIO_DIRNOT_DIRNOTP(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
/*! @} */

/* The count of GPIO_DIRNOT */
#define GPIO_DIRNOT_COUNT                        (8U)

/*! @name INTENA - Interrupt A enable control */
/*! @{ */
#define GPIO_INTENA_INT_EN0_MASK                 (0x1U)
#define GPIO_INTENA_INT_EN0_SHIFT                (0U)
/*! INT_EN0 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN0(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN0_SHIFT)) & GPIO_INTENA_INT_EN0_MASK)
#define GPIO_INTENA_INT_EN1_MASK                 (0x2U)
#define GPIO_INTENA_INT_EN1_SHIFT                (1U)
/*! INT_EN1 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN1(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN1_SHIFT)) & GPIO_INTENA_INT_EN1_MASK)
#define GPIO_INTENA_INT_EN2_MASK                 (0x4U)
#define GPIO_INTENA_INT_EN2_SHIFT                (2U)
/*! INT_EN2 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN2(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN2_SHIFT)) & GPIO_INTENA_INT_EN2_MASK)
#define GPIO_INTENA_INT_EN3_MASK                 (0x8U)
#define GPIO_INTENA_INT_EN3_SHIFT                (3U)
/*! INT_EN3 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN3(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN3_SHIFT)) & GPIO_INTENA_INT_EN3_MASK)
#define GPIO_INTENA_INT_EN4_MASK                 (0x10U)
#define GPIO_INTENA_INT_EN4_SHIFT                (4U)
/*! INT_EN4 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN4(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN4_SHIFT)) & GPIO_INTENA_INT_EN4_MASK)
#define GPIO_INTENA_INT_EN5_MASK                 (0x20U)
#define GPIO_INTENA_INT_EN5_SHIFT                (5U)
/*! INT_EN5 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN5(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN5_SHIFT)) & GPIO_INTENA_INT_EN5_MASK)
#define GPIO_INTENA_INT_EN6_MASK                 (0x40U)
#define GPIO_INTENA_INT_EN6_SHIFT                (6U)
/*! INT_EN6 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN6(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN6_SHIFT)) & GPIO_INTENA_INT_EN6_MASK)
#define GPIO_INTENA_INT_EN7_MASK                 (0x80U)
#define GPIO_INTENA_INT_EN7_SHIFT                (7U)
/*! INT_EN7 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN7(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN7_SHIFT)) & GPIO_INTENA_INT_EN7_MASK)
#define GPIO_INTENA_INT_EN8_MASK                 (0x100U)
#define GPIO_INTENA_INT_EN8_SHIFT                (8U)
/*! INT_EN8 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN8(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN8_SHIFT)) & GPIO_INTENA_INT_EN8_MASK)
#define GPIO_INTENA_INT_EN9_MASK                 (0x200U)
#define GPIO_INTENA_INT_EN9_SHIFT                (9U)
/*! INT_EN9 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN9(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN9_SHIFT)) & GPIO_INTENA_INT_EN9_MASK)
#define GPIO_INTENA_INT_EN10_MASK                (0x400U)
#define GPIO_INTENA_INT_EN10_SHIFT               (10U)
/*! INT_EN10 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN10(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN10_SHIFT)) & GPIO_INTENA_INT_EN10_MASK)
#define GPIO_INTENA_INT_EN11_MASK                (0x800U)
#define GPIO_INTENA_INT_EN11_SHIFT               (11U)
/*! INT_EN11 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN11(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN11_SHIFT)) & GPIO_INTENA_INT_EN11_MASK)
#define GPIO_INTENA_INT_EN12_MASK                (0x1000U)
#define GPIO_INTENA_INT_EN12_SHIFT               (12U)
/*! INT_EN12 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN12(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN12_SHIFT)) & GPIO_INTENA_INT_EN12_MASK)
#define GPIO_INTENA_INT_EN13_MASK                (0x2000U)
#define GPIO_INTENA_INT_EN13_SHIFT               (13U)
/*! INT_EN13 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN13(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN13_SHIFT)) & GPIO_INTENA_INT_EN13_MASK)
#define GPIO_INTENA_INT_EN14_MASK                (0x4000U)
#define GPIO_INTENA_INT_EN14_SHIFT               (14U)
/*! INT_EN14 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN14(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN14_SHIFT)) & GPIO_INTENA_INT_EN14_MASK)
#define GPIO_INTENA_INT_EN15_MASK                (0x8000U)
#define GPIO_INTENA_INT_EN15_SHIFT               (15U)
/*! INT_EN15 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN15(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN15_SHIFT)) & GPIO_INTENA_INT_EN15_MASK)
#define GPIO_INTENA_INT_EN16_MASK                (0x10000U)
#define GPIO_INTENA_INT_EN16_SHIFT               (16U)
/*! INT_EN16 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN16(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN16_SHIFT)) & GPIO_INTENA_INT_EN16_MASK)
#define GPIO_INTENA_INT_EN17_MASK                (0x20000U)
#define GPIO_INTENA_INT_EN17_SHIFT               (17U)
/*! INT_EN17 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN17(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN17_SHIFT)) & GPIO_INTENA_INT_EN17_MASK)
#define GPIO_INTENA_INT_EN18_MASK                (0x40000U)
#define GPIO_INTENA_INT_EN18_SHIFT               (18U)
/*! INT_EN18 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN18(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN18_SHIFT)) & GPIO_INTENA_INT_EN18_MASK)
#define GPIO_INTENA_INT_EN19_MASK                (0x80000U)
#define GPIO_INTENA_INT_EN19_SHIFT               (19U)
/*! INT_EN19 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN19(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN19_SHIFT)) & GPIO_INTENA_INT_EN19_MASK)
#define GPIO_INTENA_INT_EN20_MASK                (0x100000U)
#define GPIO_INTENA_INT_EN20_SHIFT               (20U)
/*! INT_EN20 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN20(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN20_SHIFT)) & GPIO_INTENA_INT_EN20_MASK)
#define GPIO_INTENA_INT_EN21_MASK                (0x200000U)
#define GPIO_INTENA_INT_EN21_SHIFT               (21U)
/*! INT_EN21 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN21(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN21_SHIFT)) & GPIO_INTENA_INT_EN21_MASK)
#define GPIO_INTENA_INT_EN22_MASK                (0x400000U)
#define GPIO_INTENA_INT_EN22_SHIFT               (22U)
/*! INT_EN22 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN22(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN22_SHIFT)) & GPIO_INTENA_INT_EN22_MASK)
#define GPIO_INTENA_INT_EN23_MASK                (0x800000U)
#define GPIO_INTENA_INT_EN23_SHIFT               (23U)
/*! INT_EN23 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN23(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN23_SHIFT)) & GPIO_INTENA_INT_EN23_MASK)
#define GPIO_INTENA_INT_EN24_MASK                (0x1000000U)
#define GPIO_INTENA_INT_EN24_SHIFT               (24U)
/*! INT_EN24 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN24(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN24_SHIFT)) & GPIO_INTENA_INT_EN24_MASK)
#define GPIO_INTENA_INT_EN25_MASK                (0x2000000U)
#define GPIO_INTENA_INT_EN25_SHIFT               (25U)
/*! INT_EN25 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN25(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN25_SHIFT)) & GPIO_INTENA_INT_EN25_MASK)
#define GPIO_INTENA_INT_EN26_MASK                (0x4000000U)
#define GPIO_INTENA_INT_EN26_SHIFT               (26U)
/*! INT_EN26 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN26(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN26_SHIFT)) & GPIO_INTENA_INT_EN26_MASK)
#define GPIO_INTENA_INT_EN27_MASK                (0x8000000U)
#define GPIO_INTENA_INT_EN27_SHIFT               (27U)
/*! INT_EN27 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN27(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN27_SHIFT)) & GPIO_INTENA_INT_EN27_MASK)
#define GPIO_INTENA_INT_EN28_MASK                (0x10000000U)
#define GPIO_INTENA_INT_EN28_SHIFT               (28U)
/*! INT_EN28 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN28(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN28_SHIFT)) & GPIO_INTENA_INT_EN28_MASK)
#define GPIO_INTENA_INT_EN29_MASK                (0x20000000U)
#define GPIO_INTENA_INT_EN29_SHIFT               (29U)
/*! INT_EN29 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN29(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN29_SHIFT)) & GPIO_INTENA_INT_EN29_MASK)
#define GPIO_INTENA_INT_EN30_MASK                (0x40000000U)
#define GPIO_INTENA_INT_EN30_SHIFT               (30U)
/*! INT_EN30 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN30(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN30_SHIFT)) & GPIO_INTENA_INT_EN30_MASK)
#define GPIO_INTENA_INT_EN31_MASK                (0x80000000U)
#define GPIO_INTENA_INT_EN31_SHIFT               (31U)
/*! INT_EN31 - Interrupt A enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt A
 *  0b1..Pin contributes to GPIO interrupt A
 */
#define GPIO_INTENA_INT_EN31(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENA_INT_EN31_SHIFT)) & GPIO_INTENA_INT_EN31_MASK)
/*! @} */

/* The count of GPIO_INTENA */
#define GPIO_INTENA_COUNT                        (8U)

/*! @name INTENB - Interrupt B enable control */
/*! @{ */
#define GPIO_INTENB_INT_EN0_MASK                 (0x1U)
#define GPIO_INTENB_INT_EN0_SHIFT                (0U)
/*! INT_EN0 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN0(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN0_SHIFT)) & GPIO_INTENB_INT_EN0_MASK)
#define GPIO_INTENB_INT_EN1_MASK                 (0x2U)
#define GPIO_INTENB_INT_EN1_SHIFT                (1U)
/*! INT_EN1 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN1(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN1_SHIFT)) & GPIO_INTENB_INT_EN1_MASK)
#define GPIO_INTENB_INT_EN2_MASK                 (0x4U)
#define GPIO_INTENB_INT_EN2_SHIFT                (2U)
/*! INT_EN2 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN2(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN2_SHIFT)) & GPIO_INTENB_INT_EN2_MASK)
#define GPIO_INTENB_INT_EN3_MASK                 (0x8U)
#define GPIO_INTENB_INT_EN3_SHIFT                (3U)
/*! INT_EN3 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN3(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN3_SHIFT)) & GPIO_INTENB_INT_EN3_MASK)
#define GPIO_INTENB_INT_EN4_MASK                 (0x10U)
#define GPIO_INTENB_INT_EN4_SHIFT                (4U)
/*! INT_EN4 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN4(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN4_SHIFT)) & GPIO_INTENB_INT_EN4_MASK)
#define GPIO_INTENB_INT_EN5_MASK                 (0x20U)
#define GPIO_INTENB_INT_EN5_SHIFT                (5U)
/*! INT_EN5 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN5(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN5_SHIFT)) & GPIO_INTENB_INT_EN5_MASK)
#define GPIO_INTENB_INT_EN6_MASK                 (0x40U)
#define GPIO_INTENB_INT_EN6_SHIFT                (6U)
/*! INT_EN6 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN6(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN6_SHIFT)) & GPIO_INTENB_INT_EN6_MASK)
#define GPIO_INTENB_INT_EN7_MASK                 (0x80U)
#define GPIO_INTENB_INT_EN7_SHIFT                (7U)
/*! INT_EN7 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN7(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN7_SHIFT)) & GPIO_INTENB_INT_EN7_MASK)
#define GPIO_INTENB_INT_EN8_MASK                 (0x100U)
#define GPIO_INTENB_INT_EN8_SHIFT                (8U)
/*! INT_EN8 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN8(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN8_SHIFT)) & GPIO_INTENB_INT_EN8_MASK)
#define GPIO_INTENB_INT_EN9_MASK                 (0x200U)
#define GPIO_INTENB_INT_EN9_SHIFT                (9U)
/*! INT_EN9 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN9(x)                   (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN9_SHIFT)) & GPIO_INTENB_INT_EN9_MASK)
#define GPIO_INTENB_INT_EN10_MASK                (0x400U)
#define GPIO_INTENB_INT_EN10_SHIFT               (10U)
/*! INT_EN10 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN10(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN10_SHIFT)) & GPIO_INTENB_INT_EN10_MASK)
#define GPIO_INTENB_INT_EN11_MASK                (0x800U)
#define GPIO_INTENB_INT_EN11_SHIFT               (11U)
/*! INT_EN11 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN11(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN11_SHIFT)) & GPIO_INTENB_INT_EN11_MASK)
#define GPIO_INTENB_INT_EN12_MASK                (0x1000U)
#define GPIO_INTENB_INT_EN12_SHIFT               (12U)
/*! INT_EN12 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN12(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN12_SHIFT)) & GPIO_INTENB_INT_EN12_MASK)
#define GPIO_INTENB_INT_EN13_MASK                (0x2000U)
#define GPIO_INTENB_INT_EN13_SHIFT               (13U)
/*! INT_EN13 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN13(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN13_SHIFT)) & GPIO_INTENB_INT_EN13_MASK)
#define GPIO_INTENB_INT_EN14_MASK                (0x4000U)
#define GPIO_INTENB_INT_EN14_SHIFT               (14U)
/*! INT_EN14 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN14(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN14_SHIFT)) & GPIO_INTENB_INT_EN14_MASK)
#define GPIO_INTENB_INT_EN15_MASK                (0x8000U)
#define GPIO_INTENB_INT_EN15_SHIFT               (15U)
/*! INT_EN15 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN15(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN15_SHIFT)) & GPIO_INTENB_INT_EN15_MASK)
#define GPIO_INTENB_INT_EN16_MASK                (0x10000U)
#define GPIO_INTENB_INT_EN16_SHIFT               (16U)
/*! INT_EN16 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN16(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN16_SHIFT)) & GPIO_INTENB_INT_EN16_MASK)
#define GPIO_INTENB_INT_EN17_MASK                (0x20000U)
#define GPIO_INTENB_INT_EN17_SHIFT               (17U)
/*! INT_EN17 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN17(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN17_SHIFT)) & GPIO_INTENB_INT_EN17_MASK)
#define GPIO_INTENB_INT_EN18_MASK                (0x40000U)
#define GPIO_INTENB_INT_EN18_SHIFT               (18U)
/*! INT_EN18 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN18(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN18_SHIFT)) & GPIO_INTENB_INT_EN18_MASK)
#define GPIO_INTENB_INT_EN19_MASK                (0x80000U)
#define GPIO_INTENB_INT_EN19_SHIFT               (19U)
/*! INT_EN19 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN19(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN19_SHIFT)) & GPIO_INTENB_INT_EN19_MASK)
#define GPIO_INTENB_INT_EN20_MASK                (0x100000U)
#define GPIO_INTENB_INT_EN20_SHIFT               (20U)
/*! INT_EN20 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN20(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN20_SHIFT)) & GPIO_INTENB_INT_EN20_MASK)
#define GPIO_INTENB_INT_EN21_MASK                (0x200000U)
#define GPIO_INTENB_INT_EN21_SHIFT               (21U)
/*! INT_EN21 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN21(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN21_SHIFT)) & GPIO_INTENB_INT_EN21_MASK)
#define GPIO_INTENB_INT_EN22_MASK                (0x400000U)
#define GPIO_INTENB_INT_EN22_SHIFT               (22U)
/*! INT_EN22 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN22(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN22_SHIFT)) & GPIO_INTENB_INT_EN22_MASK)
#define GPIO_INTENB_INT_EN23_MASK                (0x800000U)
#define GPIO_INTENB_INT_EN23_SHIFT               (23U)
/*! INT_EN23 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN23(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN23_SHIFT)) & GPIO_INTENB_INT_EN23_MASK)
#define GPIO_INTENB_INT_EN24_MASK                (0x1000000U)
#define GPIO_INTENB_INT_EN24_SHIFT               (24U)
/*! INT_EN24 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN24(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN24_SHIFT)) & GPIO_INTENB_INT_EN24_MASK)
#define GPIO_INTENB_INT_EN25_MASK                (0x2000000U)
#define GPIO_INTENB_INT_EN25_SHIFT               (25U)
/*! INT_EN25 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN25(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN25_SHIFT)) & GPIO_INTENB_INT_EN25_MASK)
#define GPIO_INTENB_INT_EN26_MASK                (0x4000000U)
#define GPIO_INTENB_INT_EN26_SHIFT               (26U)
/*! INT_EN26 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN26(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN26_SHIFT)) & GPIO_INTENB_INT_EN26_MASK)
#define GPIO_INTENB_INT_EN27_MASK                (0x8000000U)
#define GPIO_INTENB_INT_EN27_SHIFT               (27U)
/*! INT_EN27 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN27(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN27_SHIFT)) & GPIO_INTENB_INT_EN27_MASK)
#define GPIO_INTENB_INT_EN28_MASK                (0x10000000U)
#define GPIO_INTENB_INT_EN28_SHIFT               (28U)
/*! INT_EN28 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN28(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN28_SHIFT)) & GPIO_INTENB_INT_EN28_MASK)
#define GPIO_INTENB_INT_EN29_MASK                (0x20000000U)
#define GPIO_INTENB_INT_EN29_SHIFT               (29U)
/*! INT_EN29 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN29(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN29_SHIFT)) & GPIO_INTENB_INT_EN29_MASK)
#define GPIO_INTENB_INT_EN30_MASK                (0x40000000U)
#define GPIO_INTENB_INT_EN30_SHIFT               (30U)
/*! INT_EN30 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN30(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN30_SHIFT)) & GPIO_INTENB_INT_EN30_MASK)
#define GPIO_INTENB_INT_EN31_MASK                (0x80000000U)
#define GPIO_INTENB_INT_EN31_SHIFT               (31U)
/*! INT_EN31 - Interrupt B enable bits.
 *  0b0..Pin does not contribute to GPIO interrupt B
 *  0b1..Pin contributes to GPIO interrupt B
 */
#define GPIO_INTENB_INT_EN31(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTENB_INT_EN31_SHIFT)) & GPIO_INTENB_INT_EN31_MASK)
/*! @} */

/* The count of GPIO_INTENB */
#define GPIO_INTENB_COUNT                        (8U)

/*! @name INTPOL - Interupt polarity control */
/*! @{ */
#define GPIO_INTPOL_POL_CTL0_MASK                (0x1U)
#define GPIO_INTPOL_POL_CTL0_SHIFT               (0U)
/*! POL_CTL0 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL0(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL0_SHIFT)) & GPIO_INTPOL_POL_CTL0_MASK)
#define GPIO_INTPOL_POL_CTL1_MASK                (0x2U)
#define GPIO_INTPOL_POL_CTL1_SHIFT               (1U)
/*! POL_CTL1 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL1(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL1_SHIFT)) & GPIO_INTPOL_POL_CTL1_MASK)
#define GPIO_INTPOL_POL_CTL2_MASK                (0x4U)
#define GPIO_INTPOL_POL_CTL2_SHIFT               (2U)
/*! POL_CTL2 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL2(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL2_SHIFT)) & GPIO_INTPOL_POL_CTL2_MASK)
#define GPIO_INTPOL_POL_CTL3_MASK                (0x8U)
#define GPIO_INTPOL_POL_CTL3_SHIFT               (3U)
/*! POL_CTL3 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL3(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL3_SHIFT)) & GPIO_INTPOL_POL_CTL3_MASK)
#define GPIO_INTPOL_POL_CTL4_MASK                (0x10U)
#define GPIO_INTPOL_POL_CTL4_SHIFT               (4U)
/*! POL_CTL4 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL4(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL4_SHIFT)) & GPIO_INTPOL_POL_CTL4_MASK)
#define GPIO_INTPOL_POL_CTL5_MASK                (0x20U)
#define GPIO_INTPOL_POL_CTL5_SHIFT               (5U)
/*! POL_CTL5 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL5(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL5_SHIFT)) & GPIO_INTPOL_POL_CTL5_MASK)
#define GPIO_INTPOL_POL_CTL6_MASK                (0x40U)
#define GPIO_INTPOL_POL_CTL6_SHIFT               (6U)
/*! POL_CTL6 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL6(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL6_SHIFT)) & GPIO_INTPOL_POL_CTL6_MASK)
#define GPIO_INTPOL_POL_CTL7_MASK                (0x80U)
#define GPIO_INTPOL_POL_CTL7_SHIFT               (7U)
/*! POL_CTL7 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL7(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL7_SHIFT)) & GPIO_INTPOL_POL_CTL7_MASK)
#define GPIO_INTPOL_POL_CTL8_MASK                (0x100U)
#define GPIO_INTPOL_POL_CTL8_SHIFT               (8U)
/*! POL_CTL8 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL8(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL8_SHIFT)) & GPIO_INTPOL_POL_CTL8_MASK)
#define GPIO_INTPOL_POL_CTL9_MASK                (0x200U)
#define GPIO_INTPOL_POL_CTL9_SHIFT               (9U)
/*! POL_CTL9 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL9(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL9_SHIFT)) & GPIO_INTPOL_POL_CTL9_MASK)
#define GPIO_INTPOL_POL_CTL10_MASK               (0x400U)
#define GPIO_INTPOL_POL_CTL10_SHIFT              (10U)
/*! POL_CTL10 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL10(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL10_SHIFT)) & GPIO_INTPOL_POL_CTL10_MASK)
#define GPIO_INTPOL_POL_CTL11_MASK               (0x800U)
#define GPIO_INTPOL_POL_CTL11_SHIFT              (11U)
/*! POL_CTL11 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL11(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL11_SHIFT)) & GPIO_INTPOL_POL_CTL11_MASK)
#define GPIO_INTPOL_POL_CTL12_MASK               (0x1000U)
#define GPIO_INTPOL_POL_CTL12_SHIFT              (12U)
/*! POL_CTL12 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL12(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL12_SHIFT)) & GPIO_INTPOL_POL_CTL12_MASK)
#define GPIO_INTPOL_POL_CTL13_MASK               (0x2000U)
#define GPIO_INTPOL_POL_CTL13_SHIFT              (13U)
/*! POL_CTL13 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL13(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL13_SHIFT)) & GPIO_INTPOL_POL_CTL13_MASK)
#define GPIO_INTPOL_POL_CTL14_MASK               (0x4000U)
#define GPIO_INTPOL_POL_CTL14_SHIFT              (14U)
/*! POL_CTL14 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL14(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL14_SHIFT)) & GPIO_INTPOL_POL_CTL14_MASK)
#define GPIO_INTPOL_POL_CTL15_MASK               (0x8000U)
#define GPIO_INTPOL_POL_CTL15_SHIFT              (15U)
/*! POL_CTL15 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL15(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL15_SHIFT)) & GPIO_INTPOL_POL_CTL15_MASK)
#define GPIO_INTPOL_POL_CTL16_MASK               (0x10000U)
#define GPIO_INTPOL_POL_CTL16_SHIFT              (16U)
/*! POL_CTL16 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL16(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL16_SHIFT)) & GPIO_INTPOL_POL_CTL16_MASK)
#define GPIO_INTPOL_POL_CTL17_MASK               (0x20000U)
#define GPIO_INTPOL_POL_CTL17_SHIFT              (17U)
/*! POL_CTL17 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL17(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL17_SHIFT)) & GPIO_INTPOL_POL_CTL17_MASK)
#define GPIO_INTPOL_POL_CTL18_MASK               (0x40000U)
#define GPIO_INTPOL_POL_CTL18_SHIFT              (18U)
/*! POL_CTL18 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL18(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL18_SHIFT)) & GPIO_INTPOL_POL_CTL18_MASK)
#define GPIO_INTPOL_POL_CTL19_MASK               (0x80000U)
#define GPIO_INTPOL_POL_CTL19_SHIFT              (19U)
/*! POL_CTL19 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL19(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL19_SHIFT)) & GPIO_INTPOL_POL_CTL19_MASK)
#define GPIO_INTPOL_POL_CTL20_MASK               (0x100000U)
#define GPIO_INTPOL_POL_CTL20_SHIFT              (20U)
/*! POL_CTL20 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL20(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL20_SHIFT)) & GPIO_INTPOL_POL_CTL20_MASK)
#define GPIO_INTPOL_POL_CTL21_MASK               (0x200000U)
#define GPIO_INTPOL_POL_CTL21_SHIFT              (21U)
/*! POL_CTL21 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL21(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL21_SHIFT)) & GPIO_INTPOL_POL_CTL21_MASK)
#define GPIO_INTPOL_POL_CTL22_MASK               (0x400000U)
#define GPIO_INTPOL_POL_CTL22_SHIFT              (22U)
/*! POL_CTL22 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL22(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL22_SHIFT)) & GPIO_INTPOL_POL_CTL22_MASK)
#define GPIO_INTPOL_POL_CTL23_MASK               (0x800000U)
#define GPIO_INTPOL_POL_CTL23_SHIFT              (23U)
/*! POL_CTL23 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL23(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL23_SHIFT)) & GPIO_INTPOL_POL_CTL23_MASK)
#define GPIO_INTPOL_POL_CTL24_MASK               (0x1000000U)
#define GPIO_INTPOL_POL_CTL24_SHIFT              (24U)
/*! POL_CTL24 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL24(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL24_SHIFT)) & GPIO_INTPOL_POL_CTL24_MASK)
#define GPIO_INTPOL_POL_CTL25_MASK               (0x2000000U)
#define GPIO_INTPOL_POL_CTL25_SHIFT              (25U)
/*! POL_CTL25 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL25(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL25_SHIFT)) & GPIO_INTPOL_POL_CTL25_MASK)
#define GPIO_INTPOL_POL_CTL26_MASK               (0x4000000U)
#define GPIO_INTPOL_POL_CTL26_SHIFT              (26U)
/*! POL_CTL26 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL26(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL26_SHIFT)) & GPIO_INTPOL_POL_CTL26_MASK)
#define GPIO_INTPOL_POL_CTL27_MASK               (0x8000000U)
#define GPIO_INTPOL_POL_CTL27_SHIFT              (27U)
/*! POL_CTL27 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL27(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL27_SHIFT)) & GPIO_INTPOL_POL_CTL27_MASK)
#define GPIO_INTPOL_POL_CTL28_MASK               (0x10000000U)
#define GPIO_INTPOL_POL_CTL28_SHIFT              (28U)
/*! POL_CTL28 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL28(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL28_SHIFT)) & GPIO_INTPOL_POL_CTL28_MASK)
#define GPIO_INTPOL_POL_CTL29_MASK               (0x20000000U)
#define GPIO_INTPOL_POL_CTL29_SHIFT              (29U)
/*! POL_CTL29 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL29(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL29_SHIFT)) & GPIO_INTPOL_POL_CTL29_MASK)
#define GPIO_INTPOL_POL_CTL30_MASK               (0x40000000U)
#define GPIO_INTPOL_POL_CTL30_SHIFT              (30U)
/*! POL_CTL30 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL30(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL30_SHIFT)) & GPIO_INTPOL_POL_CTL30_MASK)
#define GPIO_INTPOL_POL_CTL31_MASK               (0x80000000U)
#define GPIO_INTPOL_POL_CTL31_SHIFT              (31U)
/*! POL_CTL31 - Polarity control for each pin
 *  0b0..High level or rising edge triggered
 *  0b1..Low level or falling edge triggered
 */
#define GPIO_INTPOL_POL_CTL31(x)                 (((uint32_t)(((uint32_t)(x)) << GPIO_INTPOL_POL_CTL31_SHIFT)) & GPIO_INTPOL_POL_CTL31_MASK)
/*! @} */

/* The count of GPIO_INTPOL */
#define GPIO_INTPOL_COUNT                        (8U)

/*! @name INTEDG - Interrupt edge select */
/*! @{ */
#define GPIO_INTEDG_EDGE0_MASK                   (0x1U)
#define GPIO_INTEDG_EDGE0_SHIFT                  (0U)
/*! EDGE0 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE0(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE0_SHIFT)) & GPIO_INTEDG_EDGE0_MASK)
#define GPIO_INTEDG_EDGE1_MASK                   (0x2U)
#define GPIO_INTEDG_EDGE1_SHIFT                  (1U)
/*! EDGE1 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE1(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE1_SHIFT)) & GPIO_INTEDG_EDGE1_MASK)
#define GPIO_INTEDG_EDGE2_MASK                   (0x4U)
#define GPIO_INTEDG_EDGE2_SHIFT                  (2U)
/*! EDGE2 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE2(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE2_SHIFT)) & GPIO_INTEDG_EDGE2_MASK)
#define GPIO_INTEDG_EDGE3_MASK                   (0x8U)
#define GPIO_INTEDG_EDGE3_SHIFT                  (3U)
/*! EDGE3 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE3(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE3_SHIFT)) & GPIO_INTEDG_EDGE3_MASK)
#define GPIO_INTEDG_EDGE4_MASK                   (0x10U)
#define GPIO_INTEDG_EDGE4_SHIFT                  (4U)
/*! EDGE4 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE4(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE4_SHIFT)) & GPIO_INTEDG_EDGE4_MASK)
#define GPIO_INTEDG_EDGE5_MASK                   (0x20U)
#define GPIO_INTEDG_EDGE5_SHIFT                  (5U)
/*! EDGE5 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE5(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE5_SHIFT)) & GPIO_INTEDG_EDGE5_MASK)
#define GPIO_INTEDG_EDGE6_MASK                   (0x40U)
#define GPIO_INTEDG_EDGE6_SHIFT                  (6U)
/*! EDGE6 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE6(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE6_SHIFT)) & GPIO_INTEDG_EDGE6_MASK)
#define GPIO_INTEDG_EDGE7_MASK                   (0x80U)
#define GPIO_INTEDG_EDGE7_SHIFT                  (7U)
/*! EDGE7 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE7(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE7_SHIFT)) & GPIO_INTEDG_EDGE7_MASK)
#define GPIO_INTEDG_EDGE8_MASK                   (0x100U)
#define GPIO_INTEDG_EDGE8_SHIFT                  (8U)
/*! EDGE8 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE8(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE8_SHIFT)) & GPIO_INTEDG_EDGE8_MASK)
#define GPIO_INTEDG_EDGE9_MASK                   (0x200U)
#define GPIO_INTEDG_EDGE9_SHIFT                  (9U)
/*! EDGE9 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE9(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE9_SHIFT)) & GPIO_INTEDG_EDGE9_MASK)
#define GPIO_INTEDG_EDGE10_MASK                  (0x400U)
#define GPIO_INTEDG_EDGE10_SHIFT                 (10U)
/*! EDGE10 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE10(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE10_SHIFT)) & GPIO_INTEDG_EDGE10_MASK)
#define GPIO_INTEDG_EDGE11_MASK                  (0x800U)
#define GPIO_INTEDG_EDGE11_SHIFT                 (11U)
/*! EDGE11 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE11(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE11_SHIFT)) & GPIO_INTEDG_EDGE11_MASK)
#define GPIO_INTEDG_EDGE12_MASK                  (0x1000U)
#define GPIO_INTEDG_EDGE12_SHIFT                 (12U)
/*! EDGE12 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE12(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE12_SHIFT)) & GPIO_INTEDG_EDGE12_MASK)
#define GPIO_INTEDG_EDGE13_MASK                  (0x2000U)
#define GPIO_INTEDG_EDGE13_SHIFT                 (13U)
/*! EDGE13 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE13(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE13_SHIFT)) & GPIO_INTEDG_EDGE13_MASK)
#define GPIO_INTEDG_EDGE14_MASK                  (0x4000U)
#define GPIO_INTEDG_EDGE14_SHIFT                 (14U)
/*! EDGE14 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE14(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE14_SHIFT)) & GPIO_INTEDG_EDGE14_MASK)
#define GPIO_INTEDG_EDGE15_MASK                  (0x8000U)
#define GPIO_INTEDG_EDGE15_SHIFT                 (15U)
/*! EDGE15 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE15(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE15_SHIFT)) & GPIO_INTEDG_EDGE15_MASK)
#define GPIO_INTEDG_EDGE16_MASK                  (0x10000U)
#define GPIO_INTEDG_EDGE16_SHIFT                 (16U)
/*! EDGE16 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE16(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE16_SHIFT)) & GPIO_INTEDG_EDGE16_MASK)
#define GPIO_INTEDG_EDGE17_MASK                  (0x20000U)
#define GPIO_INTEDG_EDGE17_SHIFT                 (17U)
/*! EDGE17 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE17(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE17_SHIFT)) & GPIO_INTEDG_EDGE17_MASK)
#define GPIO_INTEDG_EDGE18_MASK                  (0x40000U)
#define GPIO_INTEDG_EDGE18_SHIFT                 (18U)
/*! EDGE18 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE18(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE18_SHIFT)) & GPIO_INTEDG_EDGE18_MASK)
#define GPIO_INTEDG_EDGE19_MASK                  (0x80000U)
#define GPIO_INTEDG_EDGE19_SHIFT                 (19U)
/*! EDGE19 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE19(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE19_SHIFT)) & GPIO_INTEDG_EDGE19_MASK)
#define GPIO_INTEDG_EDGE20_MASK                  (0x100000U)
#define GPIO_INTEDG_EDGE20_SHIFT                 (20U)
/*! EDGE20 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE20(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE20_SHIFT)) & GPIO_INTEDG_EDGE20_MASK)
#define GPIO_INTEDG_EDGE21_MASK                  (0x200000U)
#define GPIO_INTEDG_EDGE21_SHIFT                 (21U)
/*! EDGE21 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE21(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE21_SHIFT)) & GPIO_INTEDG_EDGE21_MASK)
#define GPIO_INTEDG_EDGE22_MASK                  (0x400000U)
#define GPIO_INTEDG_EDGE22_SHIFT                 (22U)
/*! EDGE22 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE22(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE22_SHIFT)) & GPIO_INTEDG_EDGE22_MASK)
#define GPIO_INTEDG_EDGE23_MASK                  (0x800000U)
#define GPIO_INTEDG_EDGE23_SHIFT                 (23U)
/*! EDGE23 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE23(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE23_SHIFT)) & GPIO_INTEDG_EDGE23_MASK)
#define GPIO_INTEDG_EDGE24_MASK                  (0x1000000U)
#define GPIO_INTEDG_EDGE24_SHIFT                 (24U)
/*! EDGE24 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE24(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE24_SHIFT)) & GPIO_INTEDG_EDGE24_MASK)
#define GPIO_INTEDG_EDGE25_MASK                  (0x2000000U)
#define GPIO_INTEDG_EDGE25_SHIFT                 (25U)
/*! EDGE25 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE25(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE25_SHIFT)) & GPIO_INTEDG_EDGE25_MASK)
#define GPIO_INTEDG_EDGE26_MASK                  (0x4000000U)
#define GPIO_INTEDG_EDGE26_SHIFT                 (26U)
/*! EDGE26 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE26(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE26_SHIFT)) & GPIO_INTEDG_EDGE26_MASK)
#define GPIO_INTEDG_EDGE27_MASK                  (0x8000000U)
#define GPIO_INTEDG_EDGE27_SHIFT                 (27U)
/*! EDGE27 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE27(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE27_SHIFT)) & GPIO_INTEDG_EDGE27_MASK)
#define GPIO_INTEDG_EDGE28_MASK                  (0x10000000U)
#define GPIO_INTEDG_EDGE28_SHIFT                 (28U)
/*! EDGE28 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE28(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE28_SHIFT)) & GPIO_INTEDG_EDGE28_MASK)
#define GPIO_INTEDG_EDGE29_MASK                  (0x20000000U)
#define GPIO_INTEDG_EDGE29_SHIFT                 (29U)
/*! EDGE29 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE29(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE29_SHIFT)) & GPIO_INTEDG_EDGE29_MASK)
#define GPIO_INTEDG_EDGE30_MASK                  (0x40000000U)
#define GPIO_INTEDG_EDGE30_SHIFT                 (30U)
/*! EDGE30 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE30(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE30_SHIFT)) & GPIO_INTEDG_EDGE30_MASK)
#define GPIO_INTEDG_EDGE31_MASK                  (0x80000000U)
#define GPIO_INTEDG_EDGE31_SHIFT                 (31U)
/*! EDGE31 - Edge or level mode select bits.
 *  0b0..Level mode
 *  0b1..Edge mode
 */
#define GPIO_INTEDG_EDGE31(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_INTEDG_EDGE31_SHIFT)) & GPIO_INTEDG_EDGE31_MASK)
/*! @} */

/* The count of GPIO_INTEDG */
#define GPIO_INTEDG_COUNT                        (8U)

/*! @name INTSTATA - Interrupt status for interrupt A */
/*! @{ */
#define GPIO_INTSTATA_STATUS_MASK                (0xFFFFFFFFU)
#define GPIO_INTSTATA_STATUS_SHIFT               (0U)
/*! STATUS - Interrupt status.
 */
#define GPIO_INTSTATA_STATUS(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATA_STATUS_SHIFT)) & GPIO_INTSTATA_STATUS_MASK)
/*! @} */

/* The count of GPIO_INTSTATA */
#define GPIO_INTSTATA_COUNT                      (8U)

/*! @name INTSTATB - Interrupt status for interrupt B */
/*! @{ */
#define GPIO_INTSTATB_STATUS_MASK                (0xFFFFFFFFU)
#define GPIO_INTSTATB_STATUS_SHIFT               (0U)
/*! STATUS - Interrupt status
 */
#define GPIO_INTSTATB_STATUS(x)                  (((uint32_t)(((uint32_t)(x)) << GPIO_INTSTATB_STATUS_SHIFT)) & GPIO_INTSTATB_STATUS_MASK)
/*! @} */

/* The count of GPIO_INTSTATB */
#define GPIO_INTSTATB_COUNT                      (8U)


/*!
 * @}
 */ /* end of group GPIO_Register_Masks */


/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIO base address */
#define GPIO_BASE                                (0x40100000u)
/** Peripheral GPIO base pointer */
#define GPIO                                     ((GPIO_Type *)GPIO_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS                          { GPIO_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS                           { GPIO }

/*!
 * @}
 */ /* end of group GPIO_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- HASHCRYPT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer
 * @{
 */

/** HASHCRYPT - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
  __IO uint32_t STATUS;                            /**< Status, offset: 0x4 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable, offset: 0x8 */
  __IO uint32_t INTENCLR;                          /**< Interrupt Clear, offset: 0xC */
  __IO uint32_t MEMCTRL;                           /**< Memory Control, offset: 0x10 */
  __IO uint32_t MEMADDR;                           /**< Memory Address, offset: 0x14 */
       uint8_t RESERVED_0[8];
  __O  uint32_t INDATA;                            /**< Input Data, offset: 0x20 */
  __O  uint32_t ALIAS[7];                          /**< Alias, array offset: 0x24, array step: 0x4 */
  __I  uint32_t DIGEST0[8];                        /**< Digest0 n/Output Data0 n, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_1[32];
  __IO uint32_t CRYPTCFG;                          /**< Cryptographic Configuration, offset: 0x80 */
  __I  uint32_t CONFIG;                            /**< Configuration, offset: 0x84 */
       uint8_t RESERVED_2[4];
  __IO uint32_t LOCK;                              /**< Lock, offset: 0x8C */
  __O  uint32_t MASK[4];                           /**< Mask, array offset: 0x90, array step: 0x4 */
} HASHCRYPT_Type;

/* ----------------------------------------------------------------------------
   -- HASHCRYPT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks
 * @{
 */

/*! @name CTRL - Control */
/*! @{ */
#define HASHCRYPT_CTRL_MODE_MASK                 (0x7U)
#define HASHCRYPT_CTRL_MODE_SHIFT                (0U)
/*! MODE - Operational Mode
 *  0b000..Disabled
 *  0b001..SHA1 is enabled
 *  0b010..SHA2-256 is enabled
 *  0b011..
 *  0b100..AES is enabled (see also CRYPTCFG register for more controls)
 *  0b101..ICB-AES is enabled (see also CRYPTCFG register for more controls)
 *  0b110..
 *  0b111..
 */
#define HASHCRYPT_CTRL_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK)
#define HASHCRYPT_CTRL_NEW_HASH_MASK             (0x10U)
#define HASHCRYPT_CTRL_NEW_HASH_SHIFT            (4U)
/*! NEW_HASH - New Hash Operation
 *  0b1..Starts a new Hash/Crypto and initializes the Digest/Result.
 */
#define HASHCRYPT_CTRL_NEW_HASH(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK)
#define HASHCRYPT_CTRL_DMA_I_MASK                (0x100U)
#define HASHCRYPT_CTRL_DMA_I_SHIFT               (8U)
/*! DMA_I - DMA to Fill INDATA.
 *  0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used.
 *  0b1..DMA will push in the data.
 */
#define HASHCRYPT_CTRL_DMA_I(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK)
#define HASHCRYPT_CTRL_DMA_O_MASK                (0x200U)
#define HASHCRYPT_CTRL_DMA_O_SHIFT               (9U)
/*! DMA_O - DMA to Drain the Digest/Output
 *  0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt.
 *  0b1..DMA will drain the data.
 */
#define HASHCRYPT_CTRL_DMA_O(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK)
#define HASHCRYPT_CTRL_HASHSWPB_MASK             (0x1000U)
#define HASHCRYPT_CTRL_HASHSWPB_SHIFT            (12U)
/*! HASHSWPB - Hash Swap Bytes
 */
#define HASHCRYPT_CTRL_HASHSWPB(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK)
/*! @} */

/*! @name STATUS - Status */
/*! @{ */
#define HASHCRYPT_STATUS_WAITING_MASK            (0x1U)
#define HASHCRYPT_STATUS_WAITING_SHIFT           (0U)
/*! WAITING - Waiting for Data
 *  0b0..Not waiting for data - may be disabled or may be busy. For cryptographic uses, this is not set if IsLast
 *       is set nor will it set until at least 1 word is read of the output.
 *  0b1..Waiting for data to be written (16 words)
 */
#define HASHCRYPT_STATUS_WAITING(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK)
#define HASHCRYPT_STATUS_DIGEST_MASK             (0x2U)
#define HASHCRYPT_STATUS_DIGEST_SHIFT            (1U)
/*! DIGEST - Digest/Outdata
 *  0b0..Digest is not ready
 *  0b1..Digest is ready. Application may read it or may write more data.
 */
#define HASHCRYPT_STATUS_DIGEST(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK)
#define HASHCRYPT_STATUS_ERROR_MASK              (0x4U)
#define HASHCRYPT_STATUS_ERROR_SHIFT             (2U)
/*! ERROR - Error
 *  0b0..No error.
 *  0b1..An error occurred since last cleared (written 1 to clear).
 */
#define HASHCRYPT_STATUS_ERROR(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK)
#define HASHCRYPT_STATUS_NEEDKEY_MASK            (0x10U)
#define HASHCRYPT_STATUS_NEEDKEY_SHIFT           (4U)
/*! NEEDKEY - Need Key to be Written
 *  0b0..No Key is needed and writes will not be treated as Key
 *  0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING.
 */
#define HASHCRYPT_STATUS_NEEDKEY(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK)
#define HASHCRYPT_STATUS_NEEDIV_MASK             (0x20U)
#define HASHCRYPT_STATUS_NEEDIV_SHIFT            (5U)
/*! NEEDIV - Need IV/Nonce
 *  0b0..No IV/Nonce is needed, either because written already or because not needed.
 *  0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING.
 */
#define HASHCRYPT_STATUS_NEEDIV(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK)
#define HASHCRYPT_STATUS_ICBIDX_MASK             (0x3F0000U)
#define HASHCRYPT_STATUS_ICBIDX_SHIFT            (16U)
/*! ICBIDX - ICB Index Count
 */
#define HASHCRYPT_STATUS_ICBIDX(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable */
/*! @{ */
#define HASHCRYPT_INTENSET_WAITING_MASK          (0x1U)
#define HASHCRYPT_INTENSET_WAITING_SHIFT         (0U)
/*! WAITING - Interrupt When Waiting for Data Input
 *  0b0..Interrupt not enabled when waiting
 *  0b1..Interrupt is enabled when waiting
 */
#define HASHCRYPT_INTENSET_WAITING(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK)
#define HASHCRYPT_INTENSET_DIGEST_MASK           (0x2U)
#define HASHCRYPT_INTENSET_DIGEST_SHIFT          (1U)
/*! DIGEST - Digest/Outdata
 *  0b0..Interrupt not enabled when Digest is ready
 *  0b1..Interrupt is enabled when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done).
 */
#define HASHCRYPT_INTENSET_DIGEST(x)             (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK)
#define HASHCRYPT_INTENSET_ERROR_MASK            (0x4U)
#define HASHCRYPT_INTENSET_ERROR_SHIFT           (2U)
/*! ERROR - Interrupt on Error
 *  0b0..Interrupt not enabled on Error.
 *  0b1..Interrupt is enabled on Error (until cleared).
 */
#define HASHCRYPT_INTENSET_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Clear */
/*! @{ */
#define HASHCRYPT_INTENCLR_WAITING_MASK          (0x1U)
#define HASHCRYPT_INTENCLR_WAITING_SHIFT         (0U)
/*! WAITING - Waiting
 */
#define HASHCRYPT_INTENCLR_WAITING(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK)
#define HASHCRYPT_INTENCLR_DIGEST_MASK           (0x2U)
#define HASHCRYPT_INTENCLR_DIGEST_SHIFT          (1U)
/*! DIGEST - Digest
 */
#define HASHCRYPT_INTENCLR_DIGEST(x)             (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK)
#define HASHCRYPT_INTENCLR_ERROR_MASK            (0x4U)
#define HASHCRYPT_INTENCLR_ERROR_SHIFT           (2U)
/*! ERROR - Error
 */
#define HASHCRYPT_INTENCLR_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK)
/*! @} */

/*! @name MEMCTRL - Memory Control */
/*! @{ */
#define HASHCRYPT_MEMCTRL_MASTER_MASK            (0x1U)
#define HASHCRYPT_MEMCTRL_MASTER_SHIFT           (0U)
/*! MASTER - Master
 *  0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA.
 *  0b1..Mastering is enabled and DMA and INDATA should not be used.
 */
#define HASHCRYPT_MEMCTRL_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK)
#define HASHCRYPT_MEMCTRL_COUNT_MASK             (0x7FF0000U)
#define HASHCRYPT_MEMCTRL_COUNT_SHIFT            (16U)
/*! COUNT - Count
 *  0b00000000000..Done. Nothing to process
 *  0b00000000001..One 512-bit block to hash
 *  0b00000000010..Two 512-bit block to hash
 *  0b00000000011..Three 512-bit block to hash
 */
#define HASHCRYPT_MEMCTRL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK)
/*! @} */

/*! @name MEMADDR - Memory Address */
/*! @{ */
#define HASHCRYPT_MEMADDR_BASE_MASK              (0xFFFFFFFFU)
#define HASHCRYPT_MEMADDR_BASE_SHIFT             (0U)
/*! BASE - Base
 */
#define HASHCRYPT_MEMADDR_BASE(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK)
/*! @} */

/*! @name INDATA - Input Data */
/*! @{ */
#define HASHCRYPT_INDATA_DATA_MASK               (0xFFFFFFFFU)
#define HASHCRYPT_INDATA_DATA_SHIFT              (0U)
/*! DATA - Data
 */
#define HASHCRYPT_INDATA_DATA(x)                 (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK)
/*! @} */

/*! @name ALIAS - Alias */
/*! @{ */
#define HASHCRYPT_ALIAS_DATA_MASK                (0xFFFFFFFFU)
#define HASHCRYPT_ALIAS_DATA_SHIFT               (0U)
/*! DATA - Data
 */
#define HASHCRYPT_ALIAS_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK)
/*! @} */

/* The count of HASHCRYPT_ALIAS */
#define HASHCRYPT_ALIAS_COUNT                    (7U)

/*! @name DIGEST0 - Digest0 n/Output Data0 n */
/*! @{ */
#define HASHCRYPT_DIGEST0_DIGEST_MASK            (0xFFFFFFFFU)
#define HASHCRYPT_DIGEST0_DIGEST_SHIFT           (0U)
/*! DIGEST - Digest
 */
#define HASHCRYPT_DIGEST0_DIGEST(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK)
/*! @} */

/* The count of HASHCRYPT_DIGEST0 */
#define HASHCRYPT_DIGEST0_COUNT                  (8U)

/*! @name CRYPTCFG - Cryptographic Configuration */
/*! @{ */
#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK       (0x1U)
#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT      (0U)
/*! MSW1ST_OUT - Most Significant Word 1st Out
 */
#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x)         (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK)
#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK          (0x2U)
#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT         (1U)
/*! SWAPKEY - Swap Key
 */
#define HASHCRYPT_CRYPTCFG_SWAPKEY(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK)
#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK          (0x4U)
#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT         (2U)
/*! SWAPDAT - Swap Data/IV Inputs
 */
#define HASHCRYPT_CRYPTCFG_SWAPDAT(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK)
#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK           (0x8U)
#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT          (3U)
/*! MSW1ST - Most Significant Word 1st Load
 */
#define HASHCRYPT_CRYPTCFG_MSW1ST(x)             (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK)
#define HASHCRYPT_CRYPTCFG_AESMODE_MASK          (0x30U)
#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT         (4U)
/*! AESMODE - AES Cipher Mode
 *  0b00..ECB - used as is
 *  0b01..CBC mode (see details on IV/nonce)
 *  0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS.
 *  0b11..Reserved
 */
#define HASHCRYPT_CRYPTCFG_AESMODE(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK)
#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK       (0x40U)
#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT      (6U)
/*! AESDECRYPT - AES Decrypt
 *  0b0..Encrypt
 *  0b1..Decrypt
 */
#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x)         (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK)
#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK        (0x80U)
#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT       (7U)
/*! AESSECRET - AES Secret
 *  0b0..User key provided in normal way
 *  0b1..Secret key provided in hidden way by HW
 */
#define HASHCRYPT_CRYPTCFG_AESSECRET(x)          (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK)
#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK         (0x300U)
#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT        (8U)
/*! AESKEYSZ - AES Key Size
 *  0b00..128 bit key
 *  0b01..192 bit key
 *  0b10..256 bit key
 *  0b11..Reserved
 */
#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x)           (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK)
#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK        (0x1C00U)
#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT       (10U)
/*! AESCTRPOS - AES CTR Position
 */
#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x)          (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK)
#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK       (0x10000U)
#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT      (16U)
/*! STREAMLAST - Stream Last
 */
#define HASHCRYPT_CRYPTCFG_STREAMLAST(x)         (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK)
#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK            (0x300000U)
#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT           (20U)
/*! ICBSZ - ICB Size
 *  0b00..32 bits of the IV/ctr are used (from 127:96)
 *  0b01..64 bits of the IV/ctr are used (from 127:64)
 *  0b10..96 bits of the IV/ctr are used (from 127:32)
 *  0b11..All 128 bits of the IV/ctr are used
 */
#define HASHCRYPT_CRYPTCFG_ICBSZ(x)              (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK)
#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK          (0xC00000U)
#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT         (22U)
/*! ICBSTRM - ICB Stream Size
 *  0b00..8 blocks
 *  0b01..16 blocks
 *  0b10..32 blocks
 *  0b11..64 blocks
 */
#define HASHCRYPT_CRYPTCFG_ICBSTRM(x)            (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK)
/*! @} */

/*! @name CONFIG - Configuration */
/*! @{ */
#define HASHCRYPT_CONFIG_DUAL_MASK               (0x1U)
#define HASHCRYPT_CONFIG_DUAL_SHIFT              (0U)
/*! DUAL - Reads 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit
 */
#define HASHCRYPT_CONFIG_DUAL(x)                 (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK)
#define HASHCRYPT_CONFIG_DMA_MASK                (0x2U)
#define HASHCRYPT_CONFIG_DMA_SHIFT               (1U)
/*! DMA - Reads 1 if DMA is connected
 */
#define HASHCRYPT_CONFIG_DMA(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK)
#define HASHCRYPT_CONFIG_AHB_MASK                (0x8U)
#define HASHCRYPT_CONFIG_AHB_SHIFT               (3U)
/*! AHB - Reads 1 if AHB Master is enabled
 */
#define HASHCRYPT_CONFIG_AHB(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK)
#define HASHCRYPT_CONFIG_AES_MASK                (0x40U)
#define HASHCRYPT_CONFIG_AES_SHIFT               (6U)
/*! AES - Reads 1 if AES 128 is included
 */
#define HASHCRYPT_CONFIG_AES(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK)
#define HASHCRYPT_CONFIG_AESKEY_MASK             (0x80U)
#define HASHCRYPT_CONFIG_AESKEY_SHIFT            (7U)
/*! AESKEY - Reads 1 if AES 192 and 256 also included
 */
#define HASHCRYPT_CONFIG_AESKEY(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK)
#define HASHCRYPT_CONFIG_SECRET_MASK             (0x100U)
#define HASHCRYPT_CONFIG_SECRET_SHIFT            (8U)
/*! SECRET - Reads 1 if AES Secret key is available
 */
#define HASHCRYPT_CONFIG_SECRET(x)               (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK)
#define HASHCRYPT_CONFIG_ICB_MASK                (0x800U)
#define HASHCRYPT_CONFIG_ICB_SHIFT               (11U)
/*! ICB - ICB
 */
#define HASHCRYPT_CONFIG_ICB(x)                  (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK)
/*! @} */

/*! @name LOCK - Lock */
/*! @{ */
#define HASHCRYPT_LOCK_SECLOCK_MASK              (0x3U)
#define HASHCRYPT_LOCK_SECLOCK_SHIFT             (0U)
/*! SECLOCK - Secure Lock
 *  0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests.
 *  0b01..Locks to the current security level. AHB Master will issue requests at this level.
 */
#define HASHCRYPT_LOCK_SECLOCK(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK)
#define HASHCRYPT_LOCK_PATTERN_MASK              (0xFFF0U)
#define HASHCRYPT_LOCK_PATTERN_SHIFT             (4U)
/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0
 */
#define HASHCRYPT_LOCK_PATTERN(x)                (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK)
/*! @} */

/*! @name MASK - Mask */
/*! @{ */
#define HASHCRYPT_MASK_MASK_MASK                 (0xFFFFFFFFU)
#define HASHCRYPT_MASK_MASK_SHIFT                (0U)
/*! MASK - A random word.
 */
#define HASHCRYPT_MASK_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK)
/*! @} */

/* The count of HASHCRYPT_MASK */
#define HASHCRYPT_MASK_COUNT                     (4U)


/*!
 * @}
 */ /* end of group HASHCRYPT_Register_Masks */


/* HASHCRYPT - Peripheral instance base addresses */
/** Peripheral HASHCRYPT base address */
#define HASHCRYPT_BASE                           (0x40208000u)
/** Peripheral HASHCRYPT base pointer */
#define HASHCRYPT                                ((HASHCRYPT_Type *)HASHCRYPT_BASE)
/** Array initializer of HASHCRYPT peripheral base addresses */
#define HASHCRYPT_BASE_ADDRS                     { HASHCRYPT_BASE }
/** Array initializer of HASHCRYPT peripheral base pointers */
#define HASHCRYPT_BASE_PTRS                      { HASHCRYPT }

/*!
 * @}
 */ /* end of group HASHCRYPT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
 * @{
 */

/** I2C - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[2048];
  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x800 */
  __IO uint32_t STAT;                              /**< Status Register, offset: 0x804 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Set Register, offset: 0x808 */
  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear Register, offset: 0x80C */
  __IO uint32_t TIMEOUT;                           /**< Time-out Register, offset: 0x810 */
  __IO uint32_t CLKDIV;                            /**< Clock Divider Register, offset: 0x814 */
  __I  uint32_t INTSTAT;                           /**< Interrupt Status Register, offset: 0x818 */
       uint8_t RESERVED_1[4];
  __IO uint32_t MSTCTL;                            /**< Master Control Register, offset: 0x820 */
  __IO uint32_t MSTTIME;                           /**< Master Timing Register, offset: 0x824 */
  __IO uint32_t MSTDAT;                            /**< Master Data Register, offset: 0x828 */
       uint8_t RESERVED_2[20];
  __IO uint32_t SLVCTL;                            /**< Slave Control Register, offset: 0x840 */
  __IO uint32_t SLVDAT;                            /**< Slave Data Register, offset: 0x844 */
  __IO uint32_t SLVADR[4];                         /**< Slave Address Register, array offset: 0x848, array step: 0x4 */
  __IO uint32_t SLVQUAL0;                          /**< Slave Qualification for Address 0 Register, offset: 0x858 */
       uint8_t RESERVED_3[36];
  __I  uint32_t MONRXDAT;                          /**< Monitor Receiver Data Register, offset: 0x880 */
       uint8_t RESERVED_4[1912];
  __I  uint32_t ID;                                /**< Peripheral Identification Register, offset: 0xFFC */
} I2C_Type;

/* ----------------------------------------------------------------------------
   -- I2C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2C_Register_Masks I2C Register Masks
 * @{
 */

/*! @name CFG - Configuration Register */
/*! @{ */
#define I2C_CFG_MSTEN_MASK                       (0x1U)
#define I2C_CFG_MSTEN_SHIFT                      (0U)
/*! MSTEN - Master Enable
 *  0b0..Disabled. The I2C Master function is disabled. When disabled, the Master configuration settings are not
 *       changed, but the Master function is internally reset.
 *  0b1..Enabled. The I2C Master function is enabled.
 */
#define I2C_CFG_MSTEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
#define I2C_CFG_SLVEN_MASK                       (0x2U)
#define I2C_CFG_SLVEN_SHIFT                      (1U)
/*! SLVEN - Slave Enable
 *  0b0..Disabled. The I2C slave function is disabled. When disabled, the Slave configuration settings are not
 *       changed, but the Slave function is internally reset.
 *  0b1..Enabled. The I2C slave function is enabled.
 */
#define I2C_CFG_SLVEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
#define I2C_CFG_MONEN_MASK                       (0x4U)
#define I2C_CFG_MONEN_SHIFT                      (2U)
/*! MONEN - Monitor Enable
 *  0b0..Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function configuration
 *       settings are not changed, but the Monitor function is internally reset.
 *  0b1..Enabled. The I2C Monitor function is enabled.
 */
#define I2C_CFG_MONEN(x)                         (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
#define I2C_CFG_TIMEOUTEN_MASK                   (0x8U)
#define I2C_CFG_TIMEOUTEN_SHIFT                  (3U)
/*! TIMEOUTEN - I2C bus Time-out Enable
 *  0b0..Disabled. The time-out function is disabled. When disabled, the time-out function is internally reset.
 *  0b1..Enabled. The time-out function is enabled. Both types of time-out flags will be generated and will cause
 *       interrupts if those flags are enabled. Typically, only one time-out flag will be used in a system.
 */
#define I2C_CFG_TIMEOUTEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
#define I2C_CFG_MONCLKSTR_MASK                   (0x10U)
#define I2C_CFG_MONCLKSTR_SHIFT                  (4U)
/*! MONCLKSTR - Monitor function Clock Stretching
 *  0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
 *       to read data provided by the Monitor function before it (the data) is overwritten. This mode can be used
 *       when non-invasive monitoring is critical.
 *  0b1..Enabled. The Monitor function will perform clock stretching, to ensure that the software or DMA can read
 *       all incoming data supplied by the Monitor function.
 */
#define I2C_CFG_MONCLKSTR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
#define I2C_CFG_HSCAPABLE_MASK                   (0x20U)
#define I2C_CFG_HSCAPABLE_SHIFT                  (5U)
/*! HSCAPABLE - High Speed mode Capable enable
 *  0b0..Fast mode Plus enable
 *  0b1..High Speed mode enable
 */
#define I2C_CFG_HSCAPABLE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
/*! @} */

/*! @name STAT - Status Register */
/*! @{ */
#define I2C_STAT_MSTPENDING_MASK                 (0x1U)
#define I2C_STAT_MSTPENDING_SHIFT                (0U)
/*! MSTPENDING - Master Pending
 *  0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
 *  0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
 *       idle state, then the master is waiting to receive or transmit data, or is waiting for the NACK bit.
 */
#define I2C_STAT_MSTPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
#define I2C_STAT_MSTSTATE_MASK                   (0xEU)
#define I2C_STAT_MSTSTATE_SHIFT                  (1U)
/*! MSTSTATE - Master State code
 *  0b000..Idle. The Master function is available to be used for a new transaction.
 *  0b001..Receive ready. Received data is available (in Master Receiver mode). Address plus Read was previously sent and Acknowledged by a slave.
 *  0b010..Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Write was previously sent and Acknowledged by a slave.
 *  0b011..NACK Address. Slave NACKed address.
 *  0b100..NACK Data. Slave NACKed transmitted data.
 */
#define I2C_STAT_MSTSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
#define I2C_STAT_MSTARBLOSS_MASK                 (0x10U)
#define I2C_STAT_MSTARBLOSS_SHIFT                (4U)
/*! MSTARBLOSS - Master Arbitration Loss flag
 *  0b0..No Arbitration Loss has occurred
 *  0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
 *       function has already stopped driving the bus and has gone into an idle state. Software can respond by doing
 *       nothing, or by sending a Start (to attempt to gain control of the bus when the bus next becomes idle).
 */
#define I2C_STAT_MSTARBLOSS(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
#define I2C_STAT_MSTSTSTPERR_MASK                (0x40U)
#define I2C_STAT_MSTSTSTPERR_SHIFT               (6U)
/*! MSTSTSTPERR - Master Start/Stop Error flag
 *  0b0..No Start/Stop Error has occurred.
 *  0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when Start
 *       or Stop is not allowed by the I2C specification. The Master interface has stopped driving the bus and
 *       gone into an idle state; no action is required. A request for a Start could be made, or software could
 *       attempt to make sure that the bus has not stalled.
 */
#define I2C_STAT_MSTSTSTPERR(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
#define I2C_STAT_SLVPENDING_MASK                 (0x100U)
#define I2C_STAT_SLVPENDING_SHIFT                (8U)
/*! SLVPENDING - Slave Pending
 *  0b0..In progress. The Slave function does not currently need software service.
 *  0b1..Pending. The Slave function needs software service. Information about what is needed is in the Slave state field (SLVSTATE).
 */
#define I2C_STAT_SLVPENDING(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
#define I2C_STAT_SLVSTATE_MASK                   (0x600U)
#define I2C_STAT_SLVSTATE_SHIFT                  (9U)
/*! SLVSTATE - Slave State
 *  0b00..Slave address. Address plus R/W received. At least one of the 4 slave addresses has been matched by hardware.
 *  0b01..Slave receive. Received data is available (in Slave Receiver mode).
 *  0b10..Slave transmit. Data can be transmitted (in Slave Transmitter mode).
 *  0b11..Reserved
 */
#define I2C_STAT_SLVSTATE(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
#define I2C_STAT_SLVNOTSTR_MASK                  (0x800U)
#define I2C_STAT_SLVNOTSTR_SHIFT                 (11U)
/*! SLVNOTSTR - Slave Not Stretching
 *  0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepmode cannot be entered at this time.
 *  0b1..Not stretching. The slave function is not currently stretching the I2C bus clock. Deep-sleep mode can be entered at this time.
 */
#define I2C_STAT_SLVNOTSTR(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
#define I2C_STAT_SLVIDX_MASK                     (0x3000U)
#define I2C_STAT_SLVIDX_SHIFT                    (12U)
/*! SLVIDX - Slave address match Index T
 *  0b00..Address 0. Slave address 0 was matched.
 *  0b01..Address 1. Slave address 1 was matched.
 *  0b10..Address 2. Slave address 2 was matched.
 *  0b11..Address 3. Slave address 3 was matched.
 */
#define I2C_STAT_SLVIDX(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
#define I2C_STAT_SLVSEL_MASK                     (0x4000U)
#define I2C_STAT_SLVSEL_SHIFT                    (14U)
/*! SLVSEL - Slave selected flag
 *  0b0..Not selected. The Slave function is not currently selected.
 *  0b1..Selected. The Slave function is currently selected.
 */
#define I2C_STAT_SLVSEL(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
#define I2C_STAT_SLVDESEL_MASK                   (0x8000U)
#define I2C_STAT_SLVDESEL_SHIFT                  (15U)
/*! SLVDESEL - Slave Deselected flag
 *  0b0..Not deselected. The Slave function has not become deselected. This does not mean that the Slave is
 *       currently selected. That information is in the SLVSEL flag.
 *  0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
 *       changing from 1 to 0. See SLVSEL for details about when that event occurs.
 */
#define I2C_STAT_SLVDESEL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
#define I2C_STAT_MONRDY_MASK                     (0x10000U)
#define I2C_STAT_MONRDY_SHIFT                    (16U)
/*! MONRDY - Monitor Ready
 *  0b0..No data. The Monitor function does not currently have data available.
 *  0b1..Data waiting. The Monitor function has data waiting to be read.
 */
#define I2C_STAT_MONRDY(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
#define I2C_STAT_MONOV_MASK                      (0x20000U)
#define I2C_STAT_MONOV_SHIFT                     (17U)
/*! MONOV - Monitor Overflow flag
 *  0b0..No overrun. Monitor data has not overrun.
 *  0b1..Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor clock stretching
 *       not enabled via the CFG[MONCLKSTR] bit. Writing 1 to MONOV bit clears the MONOV flag.
 */
#define I2C_STAT_MONOV(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
#define I2C_STAT_MONACTIVE_MASK                  (0x40000U)
#define I2C_STAT_MONACTIVE_SHIFT                 (18U)
/*! MONACTIVE - Monitor Active flag
 *  0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
 *  0b1..Active. The Monitor function considers the I2C bus to be active.
 */
#define I2C_STAT_MONACTIVE(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
#define I2C_STAT_MONIDLE_MASK                    (0x80000U)
#define I2C_STAT_MONIDLE_SHIFT                   (19U)
/*! MONIDLE - Monitor Idle flag
 *  0b0..Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software.
 *  0b1..Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was cleared by software.
 */
#define I2C_STAT_MONIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
#define I2C_STAT_EVENTTIMEOUT_MASK               (0x1000000U)
#define I2C_STAT_EVENTTIMEOUT_SHIFT              (24U)
/*! EVENTTIMEOUT - Event Time-out Interrupt flag
 *  0b0..No time-out. I2C bus events have not caused a time-out.
 *  0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
 */
#define I2C_STAT_EVENTTIMEOUT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
#define I2C_STAT_SCLTIMEOUT_MASK                 (0x2000000U)
#define I2C_STAT_SCLTIMEOUT_SHIFT                (25U)
/*! SCLTIMEOUT - SCL Time-out Interrupt flag
 *  0b0..No time-out. SCL low time has not caused a time-out.
 *  0b1..Time-out. SCL low time has caused a time-out.
 */
#define I2C_STAT_SCLTIMEOUT(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Set Register */
/*! @{ */
#define I2C_INTENSET_MSTPENDINGEN_MASK           (0x1U)
#define I2C_INTENSET_MSTPENDINGEN_SHIFT          (0U)
/*! MSTPENDINGEN - Master Pending interrupt Enable
 *  0b0..Disabled. The MstPending interrupt is disabled.
 *  0b1..Enabled. The MstPending interrupt is enabled.
 */
#define I2C_INTENSET_MSTPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
#define I2C_INTENSET_MSTARBLOSSEN_MASK           (0x10U)
#define I2C_INTENSET_MSTARBLOSSEN_SHIFT          (4U)
/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable
 *  0b0..Disabled. The MstArbLoss interrupt is disabled.
 *  0b1..Enabled. The MstArbLoss interrupt is enabled.
 */
#define I2C_INTENSET_MSTARBLOSSEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
#define I2C_INTENSET_MSTSTSTPERREN_MASK          (0x40U)
#define I2C_INTENSET_MSTSTSTPERREN_SHIFT         (6U)
/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable
 *  0b0..Disabled. The MstStStpErr interrupt is disabled.
 *  0b1..Enabled. The MstStStpErr interrupt is enabled.
 */
#define I2C_INTENSET_MSTSTSTPERREN(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
#define I2C_INTENSET_SLVPENDINGEN_MASK           (0x100U)
#define I2C_INTENSET_SLVPENDINGEN_SHIFT          (8U)
/*! SLVPENDINGEN - Slave Pending interrupt Enable
 *  0b0..Disabled. The SlvPending interrupt is disabled.
 *  0b1..Enabled. The SlvPending interrupt is enabled.
 */
#define I2C_INTENSET_SLVPENDINGEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
#define I2C_INTENSET_SLVNOTSTREN_MASK            (0x800U)
#define I2C_INTENSET_SLVNOTSTREN_SHIFT           (11U)
/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable
 *  0b0..Disabled. The SlvNotStr interrupt is disabled.
 *  0b1..Enabled. The SlvNotStr interrupt is enabled.
 */
#define I2C_INTENSET_SLVNOTSTREN(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
#define I2C_INTENSET_SLVDESELEN_MASK             (0x8000U)
#define I2C_INTENSET_SLVDESELEN_SHIFT            (15U)
/*! SLVDESELEN - Slave Deselect interrupt Enable
 *  0b0..Disabled. The SlvDeSel interrupt is disabled.
 *  0b1..Enabled. The SlvDeSel interrupt is enabled.
 */
#define I2C_INTENSET_SLVDESELEN(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
#define I2C_INTENSET_MONRDYEN_MASK               (0x10000U)
#define I2C_INTENSET_MONRDYEN_SHIFT              (16U)
/*! MONRDYEN - Monitor data Ready interrupt Enable
 *  0b0..Disabled. The MonRdy interrupt is disabled.
 *  0b1..Enabled. The MonRdy interrupt is enabled.
 */
#define I2C_INTENSET_MONRDYEN(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
#define I2C_INTENSET_MONOVEN_MASK                (0x20000U)
#define I2C_INTENSET_MONOVEN_SHIFT               (17U)
/*! MONOVEN - Monitor Overrun interrupt Enable
 *  0b0..Disabled. The MonOv interrupt is disabled.
 *  0b1..Enabled. The MonOv interrupt is enabled.
 */
#define I2C_INTENSET_MONOVEN(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
#define I2C_INTENSET_MONIDLEEN_MASK              (0x80000U)
#define I2C_INTENSET_MONIDLEEN_SHIFT             (19U)
/*! MONIDLEEN - Monitor Idle interrupt Enable
 *  0b0..Disabled. The MonIdle interrupt is disabled.
 *  0b1..Enabled. The MonIdle interrupt is enabled.
 */
#define I2C_INTENSET_MONIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
#define I2C_INTENSET_EVENTTIMEOUTEN_MASK         (0x1000000U)
#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT        (24U)
/*! EVENTTIMEOUTEN - Event Time-out interrupt Enable
 *  0b0..Disabled. The Event time-out interrupt is disabled.
 *  0b1..Enabled. The Event time-out interrupt is enabled.
 */
#define I2C_INTENSET_EVENTTIMEOUTEN(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
#define I2C_INTENSET_SCLTIMEOUTEN_MASK           (0x2000000U)
#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT          (25U)
/*! SCLTIMEOUTEN - SCL Time-out interrupt Enable
 *  0b0..Disabled. The SCL time-out interrupt is disabled.
 *  0b1..Enabled. The SCL time-out interrupt is enabled.
 */
#define I2C_INTENSET_SCLTIMEOUTEN(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear Register */
/*! @{ */
#define I2C_INTENCLR_MSTPENDINGCLR_MASK          (0x1U)
#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT         (0U)
/*! MSTPENDINGCLR - Master Pending interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MSTPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
#define I2C_INTENCLR_MSTARBLOSSCLR_MASK          (0x10U)
#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT         (4U)
/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MSTARBLOSSCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK         (0x40U)
#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT        (6U)
/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MSTSTSTPERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
#define I2C_INTENCLR_SLVPENDINGCLR_MASK          (0x100U)
#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT         (8U)
/*! SLVPENDINGCLR - Slave Pending interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SLVPENDINGCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
#define I2C_INTENCLR_SLVNOTSTRCLR_MASK           (0x800U)
#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT          (11U)
/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SLVNOTSTRCLR(x)             (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
#define I2C_INTENCLR_SLVDESELCLR_MASK            (0x8000U)
#define I2C_INTENCLR_SLVDESELCLR_SHIFT           (15U)
/*! SLVDESELCLR - Slave Deselect interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SLVDESELCLR(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
#define I2C_INTENCLR_MONRDYCLR_MASK              (0x10000U)
#define I2C_INTENCLR_MONRDYCLR_SHIFT             (16U)
/*! MONRDYCLR - Monitor data Ready interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MONRDYCLR(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
#define I2C_INTENCLR_MONOVCLR_MASK               (0x20000U)
#define I2C_INTENCLR_MONOVCLR_SHIFT              (17U)
/*! MONOVCLR - Monitor Overrun interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MONOVCLR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
#define I2C_INTENCLR_MONIDLECLR_MASK             (0x80000U)
#define I2C_INTENCLR_MONIDLECLR_SHIFT            (19U)
/*! MONIDLECLR - Monitor Idle interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_MONIDLECLR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK        (0x1000000U)
#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT       (24U)
/*! EVENTTIMEOUTCLR - Event time-out interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_EVENTTIMEOUTCLR(x)          (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK          (0x2000000U)
#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT         (25U)
/*! SCLTIMEOUTCLR - SCL time-out interrupt clear
 *  0b0..No effect on interrupt
 *  0b1..Clears the interrupt bit in INTENSET register
 */
#define I2C_INTENCLR_SCLTIMEOUTCLR(x)            (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
/*! @} */

/*! @name TIMEOUT - Time-out Register */
/*! @{ */
#define I2C_TIMEOUT_TOMIN_MASK                   (0xFU)
#define I2C_TIMEOUT_TOMIN_SHIFT                  (0U)
/*! TOMIN - Time-out time value, the bottom 4 bits
 */
#define I2C_TIMEOUT_TOMIN(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
#define I2C_TIMEOUT_TO_MASK                      (0xFFF0U)
#define I2C_TIMEOUT_TO_SHIFT                     (4U)
/*! TO - Time-out time value
 *  0b000000000000..A time-out will occur after 16 counts of the I2C function clock.
 *  0b000000000001..A time-out will occur after 32 counts of the I2C function clock.
 *  0b111111111111..A time-out will occur after 65,536 counts of the I2C function clock.
 */
#define I2C_TIMEOUT_TO(x)                        (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
/*! @} */

/*! @name CLKDIV - Clock Divider Register */
/*! @{ */
#define I2C_CLKDIV_DIVVAL_MASK                   (0xFFFFU)
#define I2C_CLKDIV_DIVVAL_SHIFT                  (0U)
/*! DIVVAL - Divider Value
 *  0b0000000000000000..FCLK is used directly by the I2C.
 *  0b0000000000000001..FCLK is divided by 2 before being used by the I2C.
 *  0b0000000000000010..FCLK is divided by 3 before being used by the I2C.
 *  0b1111111111111111..FCLK is divided by 65,536 before being used by the I2C.
 */
#define I2C_CLKDIV_DIVVAL(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt Status Register */
/*! @{ */
#define I2C_INTSTAT_MSTPENDING_MASK              (0x1U)
#define I2C_INTSTAT_MSTPENDING_SHIFT             (0U)
/*! MSTPENDING - Master Pending
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MSTPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
#define I2C_INTSTAT_MSTARBLOSS_MASK              (0x10U)
#define I2C_INTSTAT_MSTARBLOSS_SHIFT             (4U)
/*! MSTARBLOSS - Master Arbitration Loss flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MSTARBLOSS(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
#define I2C_INTSTAT_MSTSTSTPERR_MASK             (0x40U)
#define I2C_INTSTAT_MSTSTSTPERR_SHIFT            (6U)
/*! MSTSTSTPERR - Master Start/Stop Error flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MSTSTSTPERR(x)               (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
#define I2C_INTSTAT_SLVPENDING_MASK              (0x100U)
#define I2C_INTSTAT_SLVPENDING_SHIFT             (8U)
/*! SLVPENDING - Slave Pending
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SLVPENDING(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
#define I2C_INTSTAT_SLVNOTSTR_MASK               (0x800U)
#define I2C_INTSTAT_SLVNOTSTR_SHIFT              (11U)
/*! SLVNOTSTR - Slave Not Stretching status
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SLVNOTSTR(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
#define I2C_INTSTAT_SLVDESEL_MASK                (0x8000U)
#define I2C_INTSTAT_SLVDESEL_SHIFT               (15U)
/*! SLVDESEL - Slave Deselected flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SLVDESEL(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
#define I2C_INTSTAT_MONRDY_MASK                  (0x10000U)
#define I2C_INTSTAT_MONRDY_SHIFT                 (16U)
/*! MONRDY - Monitor Ready
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MONRDY(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
#define I2C_INTSTAT_MONOV_MASK                   (0x20000U)
#define I2C_INTSTAT_MONOV_SHIFT                  (17U)
/*! MONOV - Monitor Overflow flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MONOV(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
#define I2C_INTSTAT_MONIDLE_MASK                 (0x80000U)
#define I2C_INTSTAT_MONIDLE_SHIFT                (19U)
/*! MONIDLE - Monitor Idle flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_MONIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
#define I2C_INTSTAT_EVENTTIMEOUT_MASK            (0x1000000U)
#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT           (24U)
/*! EVENTTIMEOUT - Event Time-out Interrupt flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_EVENTTIMEOUT(x)              (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
#define I2C_INTSTAT_SCLTIMEOUT_MASK              (0x2000000U)
#define I2C_INTSTAT_SCLTIMEOUT_SHIFT             (25U)
/*! SCLTIMEOUT - SCL Time-out Interrupt flag
 *  0b0..Not active
 *  0b1..Active
 */
#define I2C_INTSTAT_SCLTIMEOUT(x)                (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
/*! @} */

/*! @name MSTCTL - Master Control Register */
/*! @{ */
#define I2C_MSTCTL_MSTCONTINUE_MASK              (0x1U)
#define I2C_MSTCTL_MSTCONTINUE_SHIFT             (0U)
/*! MSTCONTINUE - Master Continue(write-only)
 *  0b0..No effect
 *  0b1..Continue. Informs the Master function to continue to the next operation. This action must done after
 *       writing transmit data, reading received data, or any other housekeeping related to the next bus operation.
 */
#define I2C_MSTCTL_MSTCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
#define I2C_MSTCTL_MSTSTART_MASK                 (0x2U)
#define I2C_MSTCTL_MSTSTART_SHIFT                (1U)
/*! MSTSTART - Master Start control(write-only)
 *  0b0..No effect
 *  0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
 */
#define I2C_MSTCTL_MSTSTART(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
#define I2C_MSTCTL_MSTSTOP_MASK                  (0x4U)
#define I2C_MSTCTL_MSTSTOP_SHIFT                 (2U)
/*! MSTSTOP - Master Stop control(write-only)
 *  0b0..No effect
 *  0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
 *       if the master is receiving data from the slave (in Master Receiver mode).
 */
#define I2C_MSTCTL_MSTSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
#define I2C_MSTCTL_MSTDMA_MASK                   (0x8U)
#define I2C_MSTCTL_MSTDMA_SHIFT                  (3U)
/*! MSTDMA - Master DMA enable
 *  0b0..Disable. No DMA requests are generated for master operation.
 *  0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
 *       Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
 */
#define I2C_MSTCTL_MSTDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
/*! @} */

/*! @name MSTTIME - Master Timing Register */
/*! @{ */
#define I2C_MSTTIME_MSTSCLLOW_MASK               (0x7U)
#define I2C_MSTTIME_MSTSCLLOW_SHIFT              (0U)
/*! MSTSCLLOW - Master SCL Low time
 *  0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
 *  0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
 *  0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
 *  0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
 *  0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
 *  0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
 *  0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
 *  0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
 */
#define I2C_MSTTIME_MSTSCLLOW(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
#define I2C_MSTTIME_MSTSCLHIGH_MASK              (0x70U)
#define I2C_MSTTIME_MSTSCLHIGH_SHIFT             (4U)
/*! MSTSCLHIGH - Master SCL High time
 *  0b000..2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider.
 *  0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
 *  0b010..4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider.
 *  0b011..5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider.
 *  0b100..6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider.
 *  0b101..7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider.
 *  0b110..8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider.
 *  0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
 */
#define I2C_MSTTIME_MSTSCLHIGH(x)                (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
/*! @} */

/*! @name MSTDAT - Master Data Register */
/*! @{ */
#define I2C_MSTDAT_DATA_MASK                     (0xFFU)
#define I2C_MSTDAT_DATA_SHIFT                    (0U)
/*! DATA - Master function data register
 */
#define I2C_MSTDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
/*! @} */

/*! @name SLVCTL - Slave Control Register */
/*! @{ */
#define I2C_SLVCTL_SLVCONTINUE_MASK              (0x1U)
#define I2C_SLVCTL_SLVCONTINUE_SHIFT             (0U)
/*! SLVCONTINUE - Slave Continue
 *  0b0..No effect
 *  0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the STAT[SLVPENDING]
 *       flag. This must be done after writing transmit data, reading received data, or any other housekeeping
 *       related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be
 *       set unless SLVPENDING = 1.
 */
#define I2C_SLVCTL_SLVCONTINUE(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
#define I2C_SLVCTL_SLVNACK_MASK                  (0x2U)
#define I2C_SLVCTL_SLVNACK_SHIFT                 (1U)
/*! SLVNACK - Slave NACK
 *  0b0..No effect
 *  0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (in Slave Receiver mode).
 */
#define I2C_SLVCTL_SLVNACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
#define I2C_SLVCTL_SLVDMA_MASK                   (0x8U)
#define I2C_SLVCTL_SLVDMA_SHIFT                  (3U)
/*! SLVDMA - Slave DMA enable
 *  0b0..Disabled. No DMA requests are issued for Slave mode operation.
 *  0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
 */
#define I2C_SLVCTL_SLVDMA(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
#define I2C_SLVCTL_AUTOACK_MASK                  (0x100U)
#define I2C_SLVCTL_AUTOACK_SHIFT                 (8U)
/*! AUTOACK - Automatic Acknowledge
 *  0b0..Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is generated when a
 *       matching address is received. If AUTONACK = 1, then received addresses are NACKed (ignored).
 *  0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately,
 *       allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does
 *       not match AUTOMATCHREAD, then the behavior will depend on the SLVADR0[AUTONACK] bit: if AUTONACK is set,
 *       then it will be Nacked; if AUTONACK is clear, then a SlvPending interrupt is generated.
 */
#define I2C_SLVCTL_AUTOACK(x)                    (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
#define I2C_SLVCTL_AUTOMATCHREAD_MASK            (0x200U)
#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT           (9U)
/*! AUTOMATCHREAD - Automatic Match Read
 *  0b0..In Automatic Mode, the expected next operation is an I2C write.
 *  0b1..In Automatic Mode, the expected next operation is an I2C read.
 */
#define I2C_SLVCTL_AUTOMATCHREAD(x)              (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
/*! @} */

/*! @name SLVDAT - Slave Data Register */
/*! @{ */
#define I2C_SLVDAT_DATA_MASK                     (0xFFU)
#define I2C_SLVDAT_DATA_SHIFT                    (0U)
/*! DATA - Slave function data register
 */
#define I2C_SLVDAT_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
/*! @} */

/*! @name SLVADR - Slave Address Register */
/*! @{ */
#define I2C_SLVADR_SADISABLE_MASK                (0x1U)
#define I2C_SLVADR_SADISABLE_SHIFT               (0U)
/*! SADISABLE - Slave Address n Disable
 *  0b0..Enabled. Slave Address n is enabled.
 *  0b1..Ignored. Slave Address n is ignored.
 */
#define I2C_SLVADR_SADISABLE(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
#define I2C_SLVADR_SLVADR_MASK                   (0xFEU)
#define I2C_SLVADR_SLVADR_SHIFT                  (1U)
/*! SLVADR - Slave Address.
 */
#define I2C_SLVADR_SLVADR(x)                     (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
#define I2C_SLVADR_AUTONACK_MASK                 (0x8000U)
#define I2C_SLVADR_AUTONACK_SHIFT                (15U)
/*! AUTONACK - Automatic NACK operation
 *  0b0..Normal operation, matching I2C addresses are not ignored.
 *  0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, and the address
 *       matches SLVADRn, and AUTOMATCHREAD matches the direction.
 */
#define I2C_SLVADR_AUTONACK(x)                   (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
/*! @} */

/* The count of I2C_SLVADR */
#define I2C_SLVADR_COUNT                         (4U)

/*! @name SLVQUAL0 - Slave Qualification for Address 0 Register */
/*! @{ */
#define I2C_SLVQUAL0_QUALMODE0_MASK              (0x1U)
#define I2C_SLVQUAL0_QUALMODE0_SHIFT             (0U)
/*! QUALMODE0 - Qualify mode for slave address 0
 *  0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
 *  0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
 */
#define I2C_SLVQUAL0_QUALMODE0(x)                (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
#define I2C_SLVQUAL0_SLVQUAL0_MASK               (0xFEU)
#define I2C_SLVQUAL0_SLVQUAL0_SHIFT              (1U)
/*! SLVQUAL0 - Slave address Qualifier for address 0
 */
#define I2C_SLVQUAL0_SLVQUAL0(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
/*! @} */

/*! @name MONRXDAT - Monitor Receiver Data Register */
/*! @{ */
#define I2C_MONRXDAT_MONRXDAT_MASK               (0xFFU)
#define I2C_MONRXDAT_MONRXDAT_SHIFT              (0U)
/*! MONRXDAT - Monitor function Receiver Data
 */
#define I2C_MONRXDAT_MONRXDAT(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
#define I2C_MONRXDAT_MONSTART_MASK               (0x100U)
#define I2C_MONRXDAT_MONSTART_SHIFT              (8U)
/*! MONSTART - Monitor Received Start
 *  0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
 *  0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
 */
#define I2C_MONRXDAT_MONSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
#define I2C_MONRXDAT_MONRESTART_MASK             (0x200U)
#define I2C_MONRXDAT_MONRESTART_SHIFT            (9U)
/*! MONRESTART - Monitor Received Repeated Start
 *  0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
 *  0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
 */
#define I2C_MONRXDAT_MONRESTART(x)               (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
#define I2C_MONRXDAT_MONNACK_MASK                (0x400U)
#define I2C_MONRXDAT_MONNACK_SHIFT               (10U)
/*! MONNACK - Monitor Received NACK
 *  0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
 *  0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
 */
#define I2C_MONRXDAT_MONNACK(x)                  (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
/*! @} */

/*! @name ID - Peripheral Identification Register */
/*! @{ */
#define I2C_ID_APERTURE_MASK                     (0xFFU)
#define I2C_ID_APERTURE_SHIFT                    (0U)
/*! APERTURE - Aperture
 */
#define I2C_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
#define I2C_ID_MINOR_REV_MASK                    (0xF00U)
#define I2C_ID_MINOR_REV_SHIFT                   (8U)
/*! MINOR_REV - Minor revision of module implementation
 */
#define I2C_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
#define I2C_ID_MAJOR_REV_MASK                    (0xF000U)
#define I2C_ID_MAJOR_REV_SHIFT                   (12U)
/*! MAJOR_REV - Major revision of module implementation
 */
#define I2C_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
#define I2C_ID_ID_MASK                           (0xFFFF0000U)
#define I2C_ID_ID_SHIFT                          (16U)
/*! ID - Module identifier for the selected function
 */
#define I2C_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I2C_Register_Masks */


/* I2C - Peripheral instance base addresses */
/** Peripheral I2C0 base address */
#define I2C0_BASE                                (0x40106000u)
/** Peripheral I2C0 base pointer */
#define I2C0                                     ((I2C_Type *)I2C0_BASE)
/** Peripheral I2C1 base address */
#define I2C1_BASE                                (0x40107000u)
/** Peripheral I2C1 base pointer */
#define I2C1                                     ((I2C_Type *)I2C1_BASE)
/** Peripheral I2C2 base address */
#define I2C2_BASE                                (0x40108000u)
/** Peripheral I2C2 base pointer */
#define I2C2                                     ((I2C_Type *)I2C2_BASE)
/** Peripheral I2C3 base address */
#define I2C3_BASE                                (0x40109000u)
/** Peripheral I2C3 base pointer */
#define I2C3                                     ((I2C_Type *)I2C3_BASE)
/** Peripheral I2C4 base address */
#define I2C4_BASE                                (0x40122000u)
/** Peripheral I2C4 base pointer */
#define I2C4                                     ((I2C_Type *)I2C4_BASE)
/** Peripheral I2C5 base address */
#define I2C5_BASE                                (0x40123000u)
/** Peripheral I2C5 base pointer */
#define I2C5                                     ((I2C_Type *)I2C5_BASE)
/** Peripheral I2C6 base address */
#define I2C6_BASE                                (0x40124000u)
/** Peripheral I2C6 base pointer */
#define I2C6                                     ((I2C_Type *)I2C6_BASE)
/** Peripheral I2C7 base address */
#define I2C7_BASE                                (0x40125000u)
/** Peripheral I2C7 base pointer */
#define I2C7                                     ((I2C_Type *)I2C7_BASE)
/** Peripheral I2C8 base address */
#define I2C8_BASE                                (0x40209000u)
/** Peripheral I2C8 base pointer */
#define I2C8                                     ((I2C_Type *)I2C8_BASE)
/** Peripheral I2C9 base address */
#define I2C9_BASE                                (0x4020A000u)
/** Peripheral I2C9 base pointer */
#define I2C9                                     ((I2C_Type *)I2C9_BASE)
/** Peripheral I2C10 base address */
#define I2C10_BASE                               (0x4020B000u)
/** Peripheral I2C10 base pointer */
#define I2C10                                    ((I2C_Type *)I2C10_BASE)
/** Peripheral I2C11 base address */
#define I2C11_BASE                               (0x4020C000u)
/** Peripheral I2C11 base pointer */
#define I2C11                                    ((I2C_Type *)I2C11_BASE)
/** Peripheral I2C12 base address */
#define I2C12_BASE                               (0x4020D000u)
/** Peripheral I2C12 base pointer */
#define I2C12                                    ((I2C_Type *)I2C12_BASE)
/** Peripheral I2C13 base address */
#define I2C13_BASE                               (0x4020E000u)
/** Peripheral I2C13 base pointer */
#define I2C13                                    ((I2C_Type *)I2C13_BASE)
/** Peripheral I2C15 base address */
#define I2C15_BASE                               (0x40127000u)
/** Peripheral I2C15 base pointer */
#define I2C15                                    ((I2C_Type *)I2C15_BASE)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE, I2C10_BASE, I2C11_BASE, I2C12_BASE, I2C13_BASE, I2C15_BASE }
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I2C10, I2C11, I2C12, I2C13, I2C15 }
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group I2C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I2S Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
 * @{
 */

/** I2S - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[3072];
  __IO uint32_t CFG1;                              /**< Configuration Register 1 for the Primary Channel Pair, offset: 0xC00 */
  __IO uint32_t CFG2;                              /**< Configuration Register 2 for the Primary Channel Pair, offset: 0xC04 */
  __IO uint32_t STAT;                              /**< Status Register for the Primary Channel Pair, offset: 0xC08 */
       uint8_t RESERVED_1[16];
  __IO uint32_t DIV;                               /**< Clock Divider, offset: 0xC1C */
  struct {                                         /* offset: 0xC20, array step: 0x20 */
    __IO uint32_t PCFG1;                             /**< Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3, array offset: 0xC20, array step: 0x20 */
    __IO uint32_t PCFG2;                             /**< Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3, array offset: 0xC24, array step: 0x20 */
    __I  uint32_t PSTAT;                             /**< Status Register for Channel Pair 1..Status Register for Channel Pair 3, array offset: 0xC28, array step: 0x20 */
         uint8_t RESERVED_0[20];
  } SECCHANNEL[3];
       uint8_t RESERVED_2[384];
  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration and Enable, offset: 0xE00 */
  __IO uint32_t FIFOSTAT;                          /**< FIFO Status, offset: 0xE04 */
  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Settings, offset: 0xE08 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable Set and Read, offset: 0xE10 */
  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear and Read, offset: 0xE14 */
  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status, offset: 0xE18 */
       uint8_t RESERVED_4[4];
  __O  uint32_t FIFOWR;                            /**< FIFO Write Data, offset: 0xE20 */
  __O  uint32_t FIFOWR48H;                         /**< FIFO Write Data for Upper Data Bits, offset: 0xE24 */
       uint8_t RESERVED_5[8];
  __I  uint32_t FIFORD;                            /**< FIFO Read Data, offset: 0xE30 */
  __I  uint32_t FIFORD48H;                         /**< FIFO Read Data for Upper Data Bits, offset: 0xE34 */
       uint8_t RESERVED_6[8];
  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
  __I  uint32_t FIFORD48HNOPOP;                    /**< FIFO Data Read for Upper Data Bits with No FIFO Pop, offset: 0xE44 */
  __I  uint32_t FIFOSIZE;                          /**< FIFO Size Register, offset: 0xE48 */
       uint8_t RESERVED_7[432];
  __I  uint32_t ID;                                /**< I2S Module Identification, offset: 0xFFC */
} I2S_Type;

/* ----------------------------------------------------------------------------
   -- I2S Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I2S_Register_Masks I2S Register Masks
 * @{
 */

/*! @name CFG1 - Configuration Register 1 for the Primary Channel Pair */
/*! @{ */
#define I2S_CFG1_MAINENABLE_MASK                 (0x1U)
#define I2S_CFG1_MAINENABLE_SHIFT                (0U)
/*! MAINENABLE - Main Enable
 *  0b0..Disabled. All I2S channel pairs in this Flexcomm are disabled and the internal state machines, counters,
 *       and flags are reset. No other channel pairs can be enabled.
 *  0b1..Enabled. This I2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.
 */
#define I2S_CFG1_MAINENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
#define I2S_CFG1_DATAPAUSE_MASK                  (0x2U)
#define I2S_CFG1_DATAPAUSE_SHIFT                 (1U)
/*! DATAPAUSE - Data Flow Pause
 *  0b0..Normal operation
 *  0b1..Pause
 */
#define I2S_CFG1_DATAPAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
#define I2S_CFG1_PAIRCOUNT_MASK                  (0xCU)
#define I2S_CFG1_PAIRCOUNT_SHIFT                 (2U)
/*! PAIRCOUNT - Pair Count
 *  0b00..1 I2S channel pairs in this Flexcomm module
 *  0b01..2 I2S channel pairs in this Flexcomm module
 *  0b10..3 I2S channel pairs in this Flexcomm module
 *  0b11..4 I2S channel pairs in this Flexcomm module
 */
#define I2S_CFG1_PAIRCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
#define I2S_CFG1_MSTSLVCFG_MASK                  (0x30U)
#define I2S_CFG1_MSTSLVCFG_SHIFT                 (4U)
/*! MSTSLVCFG - Master/Slave Configuration Selection
 *  0b00..Normal Slave Mode
 *  0b01..WS Synchronized Master Mode
 *  0b10..Master Using an Existing SCK Mode
 *  0b11..Normal Master Mode
 */
#define I2S_CFG1_MSTSLVCFG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
#define I2S_CFG1_MODE_MASK                       (0xC0U)
#define I2S_CFG1_MODE_SHIFT                      (6U)
/*! MODE - Mode
 *  0b00..Classic Mode
 *  0b01..DSP mode WS 50% duty cycle
 *  0b10..DSP mode WS 1 clock
 *  0b11..DSP mode WS 1 data
 */
#define I2S_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
#define I2S_CFG1_RIGHTLOW_MASK                   (0x100U)
#define I2S_CFG1_RIGHTLOW_SHIFT                  (8U)
/*! RIGHTLOW - Right Channel Low
 *  0b0..Right high. The right channel is taken from the high part of the FIFO data. For example, when data is 16
 *       bits, FIFO bits 31:16 are used for the right channel.
 *  0b1..Right low. The right channel is taken from the low part of the FIFO data. For example, when data is 16
 *       bits, FIFO bits 15:0 are used for the right channel.
 */
#define I2S_CFG1_RIGHTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
#define I2S_CFG1_LEFTJUST_MASK                   (0x200U)
#define I2S_CFG1_LEFTJUST_SHIFT                  (9U)
/*! LEFTJUST - Left-Justify Data
 *  0b0..Right-justified. Data is transferred between the FIFO and the I2S serializer/deserializer right
 *       justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This corresponds to
 *       right-justified data in the stream on the data bus.
 *  0b1..Left-justified. Data is transferred between the FIFO and the I2S serializer/deserializer left justified,
 *       i.e., starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN.
 *       This corresponds to left-justified data in the stream on the data bus.
 */
#define I2S_CFG1_LEFTJUST(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
#define I2S_CFG1_ONECHANNEL_MASK                 (0x400U)
#define I2S_CFG1_ONECHANNEL_SHIFT                (10U)
/*! ONECHANNEL - Single Channel Mode
 *  0b0..Dual channel
 *  0b1..Single channel
 */
#define I2S_CFG1_ONECHANNEL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
#define I2S_CFG1_PDMDATA_MASK                    (0x800U)
#define I2S_CFG1_PDMDATA_SHIFT                   (11U)
/*! PDMDATA - PDM Data Selection
 *  0b0..Normal operation. Data is transferred to or from the Flexcomm FIFO.
 *  0b1..DMIC subsystem. The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair
 *       can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS signal rate must
 *       match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to
 *       overrun or underrun.
 */
#define I2S_CFG1_PDMDATA(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
#define I2S_CFG1_SCK_POL_MASK                    (0x1000U)
#define I2S_CFG1_SCK_POL_SHIFT                   (12U)
/*! SCK_POL - SCK Polarity
 *  0b0..Falling edge. Data is launched on the SCK signal falling edges and sampled on the SCK signal rising edges (standard for I2S).
 *  0b1..Rising edge. Data is launched on the SCK signal rising edges and sampled on the SCK signal falling edges.
 */
#define I2S_CFG1_SCK_POL(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
#define I2S_CFG1_WS_POL_MASK                     (0x2000U)
#define I2S_CFG1_WS_POL_SHIFT                    (13U)
/*! WS_POL - WS Polarity
 *  0b0..Not inverted. Data frames begin at a falling edge of the WS signal (standard for classic I2S).
 *  0b1..Inverted. The WS signal is inverted, resulting in a data frame beginning at a rising edge of the WS
 *       signal (standard for most 'non-classic' variations of I2S).
 */
#define I2S_CFG1_WS_POL(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
#define I2S_CFG1_DATALEN_MASK                    (0x1F0000U)
#define I2S_CFG1_DATALEN_SHIFT                   (16U)
/*! DATALEN - Data Length
 *  0b00011..Data is 4 bits in length.
 *  0b00100..Data is 5 bits in length.
 *  0b00111..Data is 8 bits in length.
 *  0b11110..Data is 31 bits in length.
 *  0b11111..Data is 32 bits in length.
 */
#define I2S_CFG1_DATALEN(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
/*! @} */

/*! @name CFG2 - Configuration Register 2 for the Primary Channel Pair */
/*! @{ */
#define I2S_CFG2_FRAMELEN_MASK                   (0x1FFU)
#define I2S_CFG2_FRAMELEN_SHIFT                  (0U)
/*! FRAMELEN - Frame Length
 *  0b000000011..Frame is 4 bits in total length
 *  0b000000100..Frame is 5 bits in total length
 *  0b111111111..Frame is 512 bits in total length
 */
#define I2S_CFG2_FRAMELEN(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
#define I2S_CFG2_POSITION_MASK                   (0x1FF0000U)
#define I2S_CFG2_POSITION_SHIFT                  (16U)
/*! POSITION - Data Position
 *  0b000000000..Data begins at bit position 0 (the first bit position) within the frame or WS phase
 *  0b000000001..Data begins at bit position 1 within the frame or WS phase
 *  0b000000010..Data begins at bit position 2 within the frame or WS phase
 */
#define I2S_CFG2_POSITION(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
/*! @} */

/*! @name STAT - Status Register for the Primary Channel Pair */
/*! @{ */
#define I2S_STAT_BUSY_MASK                       (0x1U)
#define I2S_STAT_BUSY_SHIFT                      (0U)
/*! BUSY - Busy Status
 *  0b0..Idle. The transmitter/receiver for channel pair is currently idle.
 *  0b1..Busy. The transmitter/receiver for channel pair is currently processing data.
 */
#define I2S_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
#define I2S_STAT_SLVFRMERR_MASK                  (0x2U)
#define I2S_STAT_SLVFRMERR_SHIFT                 (1U)
/*! SLVFRMERR - Slave Frame Error
 *  0b0..No error. No error has been recorded.
 *  0b1..Error. An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared
 *       by writing a 1 to this bit position.
 */
#define I2S_STAT_SLVFRMERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
#define I2S_STAT_LR_MASK                         (0x4U)
#define I2S_STAT_LR_SHIFT                        (2U)
/*! LR - Left/Right Indication
 *  0b0..Left channel
 *  0b1..Right channel
 */
#define I2S_STAT_LR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
#define I2S_STAT_DATAPAUSED_MASK                 (0x8U)
#define I2S_STAT_DATAPAUSED_SHIFT                (3U)
/*! DATAPAUSED - Data Paused
 *  0b0..Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in force,
 *       waiting for an allowed pause point. Refer to the description of the CFG1[DATAPAUSE] control bit.
 *  0b1..Paused. A data pause has been requested and is now in force.
 */
#define I2S_STAT_DATAPAUSED(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
/*! @} */

/*! @name DIV - Clock Divider */
/*! @{ */
#define I2S_DIV_DIV_MASK                         (0xFFFU)
#define I2S_DIV_DIV_SHIFT                        (0U)
/*! DIV - Divider
 *  0b000000000000..FCLK is used directly.
 *  0b000000000001..FCLK is divided by 2.
 *  0b000000000010..FCLK is divided by 3.
 *  0b111111111111..FCLK is divided by 4,096.
 */
#define I2S_DIV_DIV(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
/*! @} */

/*! @name SECCHANNEL_PCFG1 - Configuration Register 1 for Channel Pair 1..Configuration Register 1 for Channel Pair 3 */
/*! @{ */
#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK     (0x1U)
#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT    (0U)
/*! PAIRENABLE - Pair Enable
 *  0b0..Disabled. This I2S channel pair is disabled.
 *  0b1..Enabled. This I2S channel pair is enabled. Other channel pairs in this Flexcomm module may be enabled in their individual PAIRENABLE bits.
 */
#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK     (0x400U)
#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT    (10U)
/*! ONECHANNEL - Single Channel Mode
 *  0b0..Dual Channel. I2S data for this channel pair is treated as left and right channels.
 *  0b1..Single Channel. I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair.
 */
#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
/*! @} */

/* The count of I2S_SECCHANNEL_PCFG1 */
#define I2S_SECCHANNEL_PCFG1_COUNT               (3U)

/*! @name SECCHANNEL_PCFG2 - Configuration Register 2 for Channel Pair 1..Configuration Register 2 for Channel Pair 3 */
/*! @{ */
#define I2S_SECCHANNEL_PCFG2_POSITION_MASK       (0x1FF0000U)
#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT      (16U)
/*! POSITION - Data Position
 */
#define I2S_SECCHANNEL_PCFG2_POSITION(x)         (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
/*! @} */

/* The count of I2S_SECCHANNEL_PCFG2 */
#define I2S_SECCHANNEL_PCFG2_COUNT               (3U)

/*! @name SECCHANNEL_PSTAT - Status Register for Channel Pair 1..Status Register for Channel Pair 3 */
/*! @{ */
#define I2S_SECCHANNEL_PSTAT_BUSY_MASK           (0x1U)
#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT          (0U)
/*! BUSY - Busy Status for Channel Pair
 *  0b0..Idle. The transmitter/receiver for this channel pair is currently idle.
 *  0b1..Busy. The transmitter/receiver for this channel pair is currently processing data.
 */
#define I2S_SECCHANNEL_PSTAT_BUSY(x)             (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK      (0x2U)
#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT     (1U)
/*! SLVFRMERR - Save Frame Error Flag
 *  0b0..No Error. No error has been recorded.
 *  0b1..Error. An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared
 *       by writing a 1 to this bit position.
 */
#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x)        (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
#define I2S_SECCHANNEL_PSTAT_LR_MASK             (0x4U)
#define I2S_SECCHANNEL_PSTAT_LR_SHIFT            (2U)
/*! LR - Left/Right Indication
 *  0b0..Left channel
 *  0b1..Right channel
 */
#define I2S_SECCHANNEL_PSTAT_LR(x)               (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK     (0x8U)
#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT    (3U)
/*! DATAPAUSED - Data Paused Status Flag
 *  0b0..Data Not Paused. Data is not currently paused. A data pause may have been requested but is not yet in
 *       force, waiting for an allowed pause point. Refer to the description in CFG1[DATAPAUSE].
 *  0b1..Data Paused. A data pause has been requested and is now in force.
 */
#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
/*! @} */

/* The count of I2S_SECCHANNEL_PSTAT */
#define I2S_SECCHANNEL_PSTAT_COUNT               (3U)

/*! @name FIFOCFG - FIFO Configuration and Enable */
/*! @{ */
#define I2S_FIFOCFG_ENABLETX_MASK                (0x1U)
#define I2S_FIFOCFG_ENABLETX_SHIFT               (0U)
/*! ENABLETX
 *  0b0..Disabled Transmit. The transmit FIFO is not enabled.
 *  0b1..Enabled transmit. The transmit FIFO is enabled.
 */
#define I2S_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
#define I2S_FIFOCFG_ENABLERX_MASK                (0x2U)
#define I2S_FIFOCFG_ENABLERX_SHIFT               (1U)
/*! ENABLERX
 *  0b0..Disabled. The receive FIFO is not enabled.
 *  0b1..Enabled. The receive FIFO is enabled.
 */
#define I2S_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
#define I2S_FIFOCFG_TXI2SE0_MASK                 (0x4U)
#define I2S_FIFOCFG_TXI2SE0_SHIFT                (2U)
/*! TXI2SE0
 *  0b0..Last value. If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data
 *       length is 24 bits or less, or when MONO = 1 for this channel pair.
 *  0b1..Zero. If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.
 */
#define I2S_FIFOCFG_TXI2SE0(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
#define I2S_FIFOCFG_PACK48_MASK                  (0x8U)
#define I2S_FIFOCFG_PACK48_SHIFT                 (3U)
/*! PACK48 - Packing Format 48-bit data
 *  0b0..Bits_24. 48-bit I2S FIFO entries are handled as all 24-bit values.
 *  0b1..Bits_32_16. 48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.
 */
#define I2S_FIFOCFG_PACK48(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
#define I2S_FIFOCFG_SIZE_MASK                    (0x30U)
#define I2S_FIFOCFG_SIZE_SHIFT                   (4U)
/*! SIZE - FIFO Size Configuration
 *  0b10..Size 32 Bits. FIFO is configured as 8 entries of 32 bits, each corresponding to 2 16-bit data values for
 *        left and right channels. This setting occurs when the I2S CFG1[DATALEN] value is less than 16 bits, or
 *        from 25 to 32 bits.
 *  0b11..Size 48 Bits. FIFO is configured as 8 entries of 48 bits, each corresponding to 2 24-bit (?) data values
 *        for left and right channels. This setting occurs when the I2S CFG1[DATALEN] value is from 17 to 24 bits.
 */
#define I2S_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
#define I2S_FIFOCFG_DMATX_MASK                   (0x1000U)
#define I2S_FIFOCFG_DMATX_SHIFT                  (12U)
/*! DMATX - DMA Transmit
 *  0b0..Disabled. DMA is not used for the transmit function.
 *  0b1..Enabled. Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define I2S_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
#define I2S_FIFOCFG_DMARX_MASK                   (0x2000U)
#define I2S_FIFOCFG_DMARX_SHIFT                  (13U)
/*! DMARX - DMA Receive
 *  0b0..Disabled. DMA is not used for the receive function.
 *  0b1..Enabled. Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define I2S_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
#define I2S_FIFOCFG_WAKETX_MASK                  (0x4000U)
#define I2S_FIFOCFG_WAKETX_SHIFT                 (14U)
/*! WAKETX - Wake-up for Transmit FIFO Level
 *  0b0..Disabled. Only enabled interrupts wake up the device from reduced power modes.
 *  0b1..Enabled. A device wake up for DMA occurs if the transmit FIFO level reaches the value specified by
 *       FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled.
 */
#define I2S_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
#define I2S_FIFOCFG_WAKERX_MASK                  (0x8000U)
#define I2S_FIFOCFG_WAKERX_SHIFT                 (15U)
/*! WAKERX - Wake-up for Receive FIFO Level
 *  0b0..Only enabled interrupts wake up the device from reduced power modes.
 *  0b1..A device wake-up for DMA occurs if the receive FIFO level reaches the value specified by FIFOTRIG[RXLVL],
 *       even when the RXLVL interrupt is not enabled.
 */
#define I2S_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
#define I2S_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
#define I2S_FIFOCFG_EMPTYTX_SHIFT                (16U)
#define I2S_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
#define I2S_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
#define I2S_FIFOCFG_EMPTYRX_SHIFT                (17U)
#define I2S_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
#define I2S_FIFOCFG_POPDBG_MASK                  (0x40000U)
#define I2S_FIFOCFG_POPDBG_SHIFT                 (18U)
/*! POPDBG - Pop FIFO for Debug Reads
 *  0b0..Debug reads of the FIFO do not pop the FIFO.
 *  0b1..A debug read causes the FIFO to pop.
 */
#define I2S_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
/*! @} */

/*! @name FIFOSTAT - FIFO Status */
/*! @{ */
#define I2S_FIFOSTAT_TXERR_MASK                  (0x1U)
#define I2S_FIFOSTAT_TXERR_SHIFT                 (0U)
/*! TXERR - TX FIFO Error
 *  0b0..No transmit FIFO error occured
 *  0b1..Transmit FIFO error occured
 */
#define I2S_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
#define I2S_FIFOSTAT_RXERR_MASK                  (0x2U)
#define I2S_FIFOSTAT_RXERR_SHIFT                 (1U)
/*! RXERR - RX FIFO Error
 *  0b0..No receive FIFO error occured
 *  0b1..Receive FIFO error occured
 */
#define I2S_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
#define I2S_FIFOSTAT_PERINT_MASK                 (0x8U)
#define I2S_FIFOSTAT_PERINT_SHIFT                (3U)
/*! PERINT - Peripheral Interrupt
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define I2S_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
#define I2S_FIFOSTAT_TXEMPTY_MASK                (0x10U)
#define I2S_FIFOSTAT_TXEMPTY_SHIFT               (4U)
/*! TXEMPTY - Transmit FIFO Empty
 *  0b0..Transmit FIFO is not empty
 *  0b1..Transmit FIFO is empty; however, the peripheral may still be processing the last piece of data.
 */
#define I2S_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
#define I2S_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
#define I2S_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
/*! TXNOTFULL - Transmit FIFO Not Full
 *  0b0..Transmit FIFO is full, and another write would cause an overflow
 *  0b1..Transmit FIFO is not full, so more data can be written
 */
#define I2S_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
#define I2S_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
/*! RXNOTEMPTY - Receive FIFO Not Empty
 *  0b0..Receive FIFO is empty
 *  0b1..Receive FIFO is not empty, so data can be read.
 */
#define I2S_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
#define I2S_FIFOSTAT_RXFULL_MASK                 (0x80U)
#define I2S_FIFOSTAT_RXFULL_SHIFT                (7U)
/*! RXFULL - Receive FIFO Full
 *  0b0..Receive FIFO is not full
 *  0b1..Receive FIFO is full
 */
#define I2S_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
#define I2S_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
#define I2S_FIFOSTAT_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Current Level
 *  0b00000..TX FIFO is empty
 */
#define I2S_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
#define I2S_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
#define I2S_FIFOSTAT_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Current Level
 *  0b00000..RX FIFO is empty
 */
#define I2S_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
/*! @} */

/*! @name FIFOTRIG - FIFO Trigger Settings */
/*! @{ */
#define I2S_FIFOTRIG_TXLVLENA_MASK               (0x1U)
#define I2S_FIFOTRIG_TXLVLENA_SHIFT              (0U)
/*! TXLVLENA - Transmit FIFO Level Trigger Enable
 *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
 *  0b1..An trigger generates if the transmit FIFO level reaches the value specified by the TXLVL field in this register.
 */
#define I2S_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
#define I2S_FIFOTRIG_RXLVLENA_MASK               (0x2U)
#define I2S_FIFOTRIG_RXLVLENA_SHIFT              (1U)
/*! RXLVLENA - Receive FIFO Level Trigger Enable
 *  0b0..Receive FIFO level does not generate a FIFO level trigger.
 *  0b1..An trigger generates if the receive FIFO level reaches the value specified by the RXLVL.
 */
#define I2S_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
#define I2S_FIFOTRIG_TXLVL_MASK                  (0xF00U)
#define I2S_FIFOTRIG_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Level Trigger Point
 *  0b0000..Trigger when the TX FIFO becomes empty.
 *  0b0001..Trigger when the TX FIFO level decreases to one entry.
 *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full).
 */
#define I2S_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
#define I2S_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
#define I2S_FIFOTRIG_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Level Trigger Point
 *  0b0000..Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty).
 *  0b0001..Trigger when the RX FIFO has received 2 entries.
 *  0b1111..Trigger when the RX FIFO has received 16 entries (the FIFO has become full).
 */
#define I2S_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENSET - FIFO Interrupt Enable Set and Read */
/*! @{ */
#define I2S_FIFOINTENSET_TXERR_MASK              (0x1U)
#define I2S_FIFOINTENSET_TXERR_SHIFT             (0U)
/*! TXERR - Transmit Error Interrupt
 *  0b0..Disabled. No interrupt generates for a transmit error.
 *  0b1..Enabled. An interrupt generates when a transmit error occurs.
 */
#define I2S_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
#define I2S_FIFOINTENSET_RXERR_MASK              (0x2U)
#define I2S_FIFOINTENSET_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt
 *  0b0..Disabled. No interrupt generates for a receive error.
 *  0b1..Enabled. An interrupt generates when a receive error occurs.
 */
#define I2S_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
#define I2S_FIFOINTENSET_TXLVL_MASK              (0x4U)
#define I2S_FIFOINTENSET_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit Level Interrupt
 *  0b0..Disabled. No interrupt generates based on the TX FIFO level.
 *  0b1..Enabled. If FIFOTRIG[TXLVLENA] = 1, an interrupt generates when the TX FIFO level decreases to the level
 *       specified by the FIFOTRIG[TXLVL] flag.
 */
#define I2S_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
#define I2S_FIFOINTENSET_RXLVL_MASK              (0x8U)
#define I2S_FIFOINTENSET_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive Level Interrupt
 *  0b0..Disabled. No interrupt generates based on the RX FIFO level.
 *  0b1..Enabled. If FIFOTRIG[RXLVLENA] = 1, an interrupt generates when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL].
 */
#define I2S_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear and Read */
/*! @{ */
#define I2S_FIFOINTENCLR_TXERR_MASK              (0x1U)
#define I2S_FIFOINTENCLR_TXERR_SHIFT             (0U)
/*! TXERR - Transmit Error Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
#define I2S_FIFOINTENCLR_RXERR_MASK              (0x2U)
#define I2S_FIFOINTENCLR_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
#define I2S_FIFOINTENCLR_TXLVL_MASK              (0x4U)
#define I2S_FIFOINTENCLR_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit Level Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
#define I2S_FIFOINTENCLR_RXLVL_MASK              (0x8U)
#define I2S_FIFOINTENCLR_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive Level Interrupt Clear
 *  0b0..Interrupt is not cleared.
 *  0b1..Interrupt is cleared.
 */
#define I2S_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTSTAT - FIFO Interrupt Status */
/*! @{ */
#define I2S_FIFOINTSTAT_TXERR_MASK               (0x1U)
#define I2S_FIFOINTSTAT_TXERR_SHIFT              (0U)
/*! TXERR - TX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
#define I2S_FIFOINTSTAT_RXERR_MASK               (0x2U)
#define I2S_FIFOINTSTAT_RXERR_SHIFT              (1U)
/*! RXERR - RX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
#define I2S_FIFOINTSTAT_TXLVL_MASK               (0x4U)
#define I2S_FIFOINTSTAT_TXLVL_SHIFT              (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
#define I2S_FIFOINTSTAT_RXLVL_MASK               (0x8U)
#define I2S_FIFOINTSTAT_RXLVL_SHIFT              (3U)
/*! RXLVL - Receive FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
#define I2S_FIFOINTSTAT_PERINT_MASK              (0x10U)
#define I2S_FIFOINTSTAT_PERINT_SHIFT             (4U)
/*! PERINT - Peripheral Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define I2S_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
/*! @} */

/*! @name FIFOWR - FIFO Write Data */
/*! @{ */
#define I2S_FIFOWR_TXDATA_MASK                   (0xFFFFFFFFU)
#define I2S_FIFOWR_TXDATA_SHIFT                  (0U)
/*! TXDATA - Transmit Data to the FIFO
 */
#define I2S_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
/*! @} */

/*! @name FIFOWR48H - FIFO Write Data for Upper Data Bits */
/*! @{ */
#define I2S_FIFOWR48H_TXDATA_MASK                (0xFFFFFFU)
#define I2S_FIFOWR48H_TXDATA_SHIFT               (0U)
/*! TXDATA - Transmit Data to the FIFO
 */
#define I2S_FIFOWR48H_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
/*! @} */

/*! @name FIFORD - FIFO Read Data */
/*! @{ */
#define I2S_FIFORD_RXDATA_MASK                   (0xFFFFFFFFU)
#define I2S_FIFORD_RXDATA_SHIFT                  (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
/*! @} */

/*! @name FIFORD48H - FIFO Read Data for Upper Data Bits */
/*! @{ */
#define I2S_FIFORD48H_RXDATA_MASK                (0xFFFFFFU)
#define I2S_FIFORD48H_RXDATA_SHIFT               (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORD48H_RXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
/*! @} */

/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
/*! @{ */
#define I2S_FIFORDNOPOP_RXDATA_MASK              (0xFFFFFFFFU)
#define I2S_FIFORDNOPOP_RXDATA_SHIFT             (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
/*! @} */

/*! @name FIFORD48HNOPOP - FIFO Data Read for Upper Data Bits with No FIFO Pop */
/*! @{ */
#define I2S_FIFORD48HNOPOP_RXDATA_MASK           (0xFFFFFFU)
#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT          (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define I2S_FIFORD48HNOPOP_RXDATA(x)             (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
/*! @} */

/*! @name FIFOSIZE - FIFO Size Register */
/*! @{ */
#define I2S_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
#define I2S_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
#define I2S_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK)
/*! @} */

/*! @name ID - I2S Module Identification */
/*! @{ */
#define I2S_ID_APERTURE_MASK                     (0xFFU)
#define I2S_ID_APERTURE_SHIFT                    (0U)
/*! APERTURE - Aperture
 */
#define I2S_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK)
#define I2S_ID_MINOR_REV_MASK                    (0xF00U)
#define I2S_ID_MINOR_REV_SHIFT                   (8U)
/*! MINOR_REV - Minor Revision
 */
#define I2S_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK)
#define I2S_ID_MAJOR_REV_MASK                    (0xF000U)
#define I2S_ID_MAJOR_REV_SHIFT                   (12U)
/*! MAJOR_REV - Major Revision
 */
#define I2S_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK)
#define I2S_ID_ID_MASK                           (0xFFFF0000U)
#define I2S_ID_ID_SHIFT                          (16U)
/*! ID - Module Identifier
 */
#define I2S_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I2S_Register_Masks */


/* I2S - Peripheral instance base addresses */
/** Peripheral I2S0 base address */
#define I2S0_BASE                                (0x40106000u)
/** Peripheral I2S0 base pointer */
#define I2S0                                     ((I2S_Type *)I2S0_BASE)
/** Peripheral I2S1 base address */
#define I2S1_BASE                                (0x40107000u)
/** Peripheral I2S1 base pointer */
#define I2S1                                     ((I2S_Type *)I2S1_BASE)
/** Peripheral I2S2 base address */
#define I2S2_BASE                                (0x40108000u)
/** Peripheral I2S2 base pointer */
#define I2S2                                     ((I2S_Type *)I2S2_BASE)
/** Peripheral I2S3 base address */
#define I2S3_BASE                                (0x40109000u)
/** Peripheral I2S3 base pointer */
#define I2S3                                     ((I2S_Type *)I2S3_BASE)
/** Peripheral I2S4 base address */
#define I2S4_BASE                                (0x40122000u)
/** Peripheral I2S4 base pointer */
#define I2S4                                     ((I2S_Type *)I2S4_BASE)
/** Peripheral I2S5 base address */
#define I2S5_BASE                                (0x40123000u)
/** Peripheral I2S5 base pointer */
#define I2S5                                     ((I2S_Type *)I2S5_BASE)
/** Peripheral I2S6 base address */
#define I2S6_BASE                                (0x40124000u)
/** Peripheral I2S6 base pointer */
#define I2S6                                     ((I2S_Type *)I2S6_BASE)
/** Peripheral I2S7 base address */
#define I2S7_BASE                                (0x40125000u)
/** Peripheral I2S7 base pointer */
#define I2S7                                     ((I2S_Type *)I2S7_BASE)
/** Peripheral I2S8 base address */
#define I2S8_BASE                                (0x40209000u)
/** Peripheral I2S8 base pointer */
#define I2S8                                     ((I2S_Type *)I2S8_BASE)
/** Peripheral I2S9 base address */
#define I2S9_BASE                                (0x4020A000u)
/** Peripheral I2S9 base pointer */
#define I2S9                                     ((I2S_Type *)I2S9_BASE)
/** Peripheral I2S10 base address */
#define I2S10_BASE                               (0x4020B000u)
/** Peripheral I2S10 base pointer */
#define I2S10                                    ((I2S_Type *)I2S10_BASE)
/** Peripheral I2S11 base address */
#define I2S11_BASE                               (0x4020C000u)
/** Peripheral I2S11 base pointer */
#define I2S11                                    ((I2S_Type *)I2S11_BASE)
/** Peripheral I2S12 base address */
#define I2S12_BASE                               (0x4020D000u)
/** Peripheral I2S12 base pointer */
#define I2S12                                    ((I2S_Type *)I2S12_BASE)
/** Peripheral I2S13 base address */
#define I2S13_BASE                               (0x4020E000u)
/** Peripheral I2S13 base pointer */
#define I2S13                                    ((I2S_Type *)I2S13_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE, I2S8_BASE, I2S9_BASE, I2S10_BASE, I2S11_BASE, I2S12_BASE, I2S13_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS                            { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7, I2S8, I2S9, I2S10, I2S11, I2S12, I2S13 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group I2S_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- I3C Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer
 * @{
 */

/** I3C - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCONFIG;                           /**< Master Configuration Register, offset: 0x0 */
  __IO uint32_t SCONFIG;                           /**< Slave Configuration Register, offset: 0x4 */
  __IO uint32_t SSTATUS;                           /**< Slave Status Register, offset: 0x8 */
  __IO uint32_t SCTRL;                             /**< Slave Control Register, offset: 0xC */
  __IO uint32_t SINTSET;                           /**< Slave Interrupt Set Register, offset: 0x10 */
  __IO uint32_t SINTCLR;                           /**< Slave Interrupt Clear Register, offset: 0x14 */
  __I  uint32_t SINTMASKED;                        /**< Slave Interrupt Mask Register, offset: 0x18 */
  __IO uint32_t SERRWARN;                          /**< Slave Errors and Warnings Register, offset: 0x1C */
  __IO uint32_t SDMACTRL;                          /**< Slave DMA Control Register, offset: 0x20 */
       uint8_t RESERVED_0[8];
  __IO uint32_t SDATACTRL;                         /**< Slave Data Control Register, offset: 0x2C */
  __O  uint32_t SWDATAB;                           /**< Slave Write Data Byte Register, offset: 0x30 */
  __O  uint32_t SWDATABE;                          /**< Slave Write Data Byte End, offset: 0x34 */
  __O  uint32_t SWDATAH;                           /**< Slave Write Data Half-word Register, offset: 0x38 */
  __O  uint32_t SWDATAHE;                          /**< Slave Write Data Half-word End Register, offset: 0x3C */
  __I  uint32_t SRDATAB;                           /**< Slave Read Data Byte Register, offset: 0x40 */
       uint8_t RESERVED_1[4];
  __I  uint32_t SRDATAH;                           /**< Slave Read Data Half-word Register, offset: 0x48 */
       uint8_t RESERVED_2[20];
  __I  uint32_t SCAPABILITIES;                     /**< Slave Capabilities Register, offset: 0x60 */
  __IO uint32_t SDYNADDR;                          /**< Slave Dynamic Address Register, offset: 0x64 */
  __IO uint32_t SMAXLIMITS;                        /**< Slave Maximum Limits Register, offset: 0x68 */
  __IO uint32_t SIDPARTNO;                         /**< Slave ID Part Number Register, offset: 0x6C */
  __IO uint32_t SIDEXT;                            /**< Slave ID Extension Register, offset: 0x70 */
  __IO uint32_t SVENDORID;                         /**< Slave Vendor ID Register, offset: 0x74 */
  __IO uint32_t STCCLOCK;                          /**< Slave Time Control Clock Register, offset: 0x78 */
  __I  uint32_t SMSGMAPADDR;                       /**< Slave Message-Mapped Address Register, offset: 0x7C */
       uint8_t RESERVED_3[4];
  __IO uint32_t MCTRL;                             /**< Master Main Control Register, offset: 0x84 */
  __IO uint32_t MSTATUS;                           /**< Master Status Register, offset: 0x88 */
  __IO uint32_t MIBIRULES;                         /**< Master In-band Interrupt Registry and Rules Register, offset: 0x8C */
  __IO uint32_t MINTSET;                           /**< Master Interrupt Set Register, offset: 0x90 */
  __O  uint32_t MINTCLR;                           /**< Master Interrupt Clear Register, offset: 0x94 */
  __I  uint32_t MINTMASKED;                        /**< Master Interrupt Mask Register, offset: 0x98 */
  __IO uint32_t MERRWARN;                          /**< Master Errors and Warnings Register, offset: 0x9C */
  __IO uint32_t MDMACTRL;                          /**< Master DMA Control Register, offset: 0xA0 */
       uint8_t RESERVED_4[8];
  __IO uint32_t MDATACTRL;                         /**< Master Data Control Register, offset: 0xAC */
  __O  uint32_t MWDATAB;                           /**< Master Write Data Byte Register, offset: 0xB0 */
  __O  uint32_t MWDATABE;                          /**< Master Write Data Byte End Register, offset: 0xB4 */
  __O  uint32_t MWDATAH;                           /**< Master Write Data Half-word Register, offset: 0xB8 */
  __O  uint32_t MWDATAHE;                          /**< Master Write Data Byte End Register, offset: 0xBC */
  __I  uint32_t MRDATAB;                           /**< Master Read Data Byte Register, offset: 0xC0 */
       uint8_t RESERVED_5[4];
  __I  uint32_t MRDATAH;                           /**< Master Read Data Half-word Register, offset: 0xC8 */
       uint8_t RESERVED_6[4];
  union {                                          /* offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_CONTROL;                 /**< Master Write Message in SDR mode, offset: 0xD0 */
    __O  uint32_t MWMSG_SDR_DATA;                    /**< Master Write Message Data in SDR mode, offset: 0xD0 */
  };
  __I  uint32_t MRMSG_SDR;                         /**< Master Read Message in SDR mode, offset: 0xD4 */
  union {                                          /* offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_CONTROL;                 /**< Master Write Message in DDR mode, offset: 0xD8 */
    __O  uint32_t MWMSG_DDR_DATA;                    /**< Master Write Message Data in DDR mode, offset: 0xD8 */
  };
  __IO uint32_t MRMSG_DDR;                         /**< Master Read Message in DDR mode, offset: 0xDC */
       uint8_t RESERVED_7[4];
  __IO uint32_t MDYNADDR;                          /**< Master Dynamic Address Register, offset: 0xE4 */
       uint8_t RESERVED_8[3860];
  __I  uint32_t SID;                               /**< Slave Module ID Register, offset: 0xFFC */
} I3C_Type;

/* ----------------------------------------------------------------------------
   -- I3C Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup I3C_Register_Masks I3C Register Masks
 * @{
 */

/*! @name MCONFIG - Master Configuration Register */
/*! @{ */
#define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
#define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
/*! MSTENA - Master enable
 *  0b00..MASTER_OFF: Master is off (is not enabled). If MASTER_OFF is enabled, then the I3C module can only use slave mode.
 *  0b01..MASTER_ON: Master is on (is enabled). When used from start-up, this I3C module is master by default (the
 *        main master). The module will control the bus unless the master is handed off. If the master is handed
 *        off, then MSTENA must move to 2 after that happens. The handoff means emitting GETACCMST and if accepted,
 *        the module will emit a STOP and set the MSTENA bit to 2 (or 0).
 *  0b10..MASTER_CAPABLE: The I3C module is master-capable; however the module is operating as a slave now. When
 *        used from the start, the I3C module will start as a slave, but will be prepared to switch to master mode.
 *        To switch to master mode, the slave emits an Master Request (MR), or gets a GETACCMST CCC command and
 *        accepts it (to switch on the STOP).
 *  0b11..RESERVED
 */
#define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)
#define I3C_MCONFIG_DISTO_MASK                   (0x8U)
#define I3C_MCONFIG_DISTO_SHIFT                  (3U)
/*! DISTO - Disable Timeout
 */
#define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)
#define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
#define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
/*! HKEEP - High-Keeper
 *  0b00..NONE: Use PUR (Pull-Up Resistor). Hold SCL High.
 *  0b01..WIRED_IN: Wired-in High Keeper controls; use pin_HK (High Keeper) controls.
 *  0b10..PASSIVE_SDA: Passive on SDA; can Hi-Z (high impedance) for Bus Free (IDLE) and hold.
 *  0b11..PASSIVE_ON_SDA_SCL: Passive on SDA and SCL; can Hi-Z (high impedance) both for Bus Free (IDLE), and can Hi-Z SDA for hold.
 */
#define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)
#define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
#define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
/*! ODSTOP - Open drain stop
 */
#define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)
#define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
#define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
/*! PPBAUD - Push-pull baud rate
 */
#define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)
#define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
#define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
/*! PPLOW - Push-Pull low
 */
#define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
#define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
#define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
/*! ODBAUD - Open drain baud rate
 */
#define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)
#define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
#define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
/*! ODHPP - Open drain high push-pull
 */
#define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
#define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
#define I3C_MCONFIG_SKEW_SHIFT                   (25U)
/*! SKEW - Skew
 */
#define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)
#define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
#define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
/*! I2CBAUD - I2C baud rate
 */
#define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
/*! @} */

/*! @name SCONFIG - Slave Configuration Register */
/*! @{ */
#define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
#define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
/*! SLVENA - Slave enable
 */
#define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)
#define I3C_SCONFIG_NACK_MASK                    (0x2U)
#define I3C_SCONFIG_NACK_SHIFT                   (1U)
/*! NACK - Not acknowledge
 */
#define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)
#define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
#define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
/*! MATCHSS - Match START or STOP
 */
#define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)
#define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
#define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
/*! S0IGNORE - S0/S1 errors ignore
 */
#define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)
#define I3C_SCONFIG_DDROK_MASK                   (0x10U)
#define I3C_SCONFIG_DDROK_SHIFT                  (4U)
/*! DDROK - Double Data Rate OK
 */
#define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)
#define I3C_SCONFIG_IDRAND_MASK                  (0x100U)
#define I3C_SCONFIG_IDRAND_SHIFT                 (8U)
/*! IDRAND - ID random
 */
#define I3C_SCONFIG_IDRAND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)
#define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
#define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
/*! OFFLINE - Offline
 */
#define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)
#define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
#define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
/*! BAMATCH - Bus available match
 */
#define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)
#define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
#define I3C_SCONFIG_SADDR_SHIFT                  (25U)
/*! SADDR - Static address
 */
#define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
/*! @} */

/*! @name SSTATUS - Slave Status Register */
/*! @{ */
#define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
#define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
/*! STNOTSTOP - Status not stop
 */
#define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)
#define I3C_SSTATUS_STMSG_MASK                   (0x2U)
#define I3C_SSTATUS_STMSG_SHIFT                  (1U)
/*! STMSG - Status message
 */
#define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)
#define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
#define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
/*! STCCCH - Status Common Command Code Handler
 */
#define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)
#define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
#define I3C_SSTATUS_STREQRD_SHIFT                (3U)
/*! STREQRD - Status required
 */
#define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)
#define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
#define I3C_SSTATUS_STREQWR_SHIFT                (4U)
/*! STREQWR - Status request write
 */
#define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)
#define I3C_SSTATUS_STDAA_MASK                   (0x20U)
#define I3C_SSTATUS_STDAA_SHIFT                  (5U)
/*! STDAA - Status Dynamic Address Assignment
 */
#define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)
#define I3C_SSTATUS_STHDR_MASK                   (0x40U)
#define I3C_SSTATUS_STHDR_SHIFT                  (6U)
/*! STHDR - Status High Data Rate
 */
#define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)
#define I3C_SSTATUS_START_MASK                   (0x100U)
#define I3C_SSTATUS_START_SHIFT                  (8U)
/*! START - Start
 */
#define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)
#define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
#define I3C_SSTATUS_MATCHED_SHIFT                (9U)
/*! MATCHED - Matched
 */
#define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)
#define I3C_SSTATUS_STOP_MASK                    (0x400U)
#define I3C_SSTATUS_STOP_SHIFT                   (10U)
/*! STOP - Stop
 */
#define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)
#define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
#define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
/*! RX_PEND - Received message pending
 */
#define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)
#define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - Transmit buffer is not full
 */
#define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)
#define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
#define I3C_SSTATUS_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG
 */
#define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)
#define I3C_SSTATUS_CCC_MASK                     (0x4000U)
#define I3C_SSTATUS_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code
 */
#define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)
#define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error warning
 */
#define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)
#define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
#define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
/*! HDRMATCH - High Data Rate command match
 */
#define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)
#define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
#define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common-Command-Code handled
 */
#define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)
#define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
#define I3C_SSTATUS_EVENT_SHIFT                  (18U)
/*! EVENT - Event
 */
#define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)
#define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
#define I3C_SSTATUS_EVDET_SHIFT                  (20U)
/*! EVDET - Event details
 *  0b00..NONE: no event or no pending event
 *  0b01..NO_REQUEST: Request not sent yet. Either there was no START yet, or is waiting for Bus-Available or Bus-Idle (HJ).
 *  0b10..NACKED: Not acknowledged(Request sent and NACKed); the module will try again.
 *  0b11..ACKED: Acknowledged (Request sent and ACKed), so Done (unless the time control data is still being sent).
 */
#define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)
#define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
#define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
/*! IBIDIS - In-Band Interrupts are disabled
 */
#define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)
#define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
#define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
/*! MRDIS - Master requests are disabled
 */
#define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)
#define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
#define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
/*! HJDIS - Hot-Join is disabled
 */
#define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)
#define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
#define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
/*! ACTSTATE - Activity state from Common Command Codes (CCC)
 *  0b00..NO_LATENCY: normal bus operations
 *  0b01..LATENCY_1MS: 1 ms of latency
 *  0b10..LATENCY_100MS: 100 ms of latency
 *  0b11..LATENCY_10S: 10 seconds of latency
 */
#define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)
#define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
#define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
/*! TIMECTRL - Time control
 *  0b00..NO_TIME_CONTROL: No time control is enabled
 *  0b01..Reserved
 *  0b10..ASYNC_MODE: Asynchronous standard mode (0) is enabled
 *  0b11..RESERVED
 */
#define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
/*! @} */

/*! @name SCTRL - Slave Control Register */
/*! @{ */
#define I3C_SCTRL_EVENT_MASK                     (0x3U)
#define I3C_SCTRL_EVENT_SHIFT                    (0U)
/*! EVENT - EVENT
 *  0b00..NORMAL_MODE: If EVENT is set to 0 after was a non-0 value, event processing will cancel if the event
 *        processing has not yet started; if event processing has already been started, then event processing will not
 *        be be cancelled.
 *  0b01..IBI: Start an In-Band Interrupt. This will try to push an IBI interrupt onto the I3C bus. If data is
 *        associated with the IBI, then the data will be read from the SCTRL.IBIDATA field. If time control is
 *        enabled, then this data will also include any time control-related bytes; additionally, the IBIDATA byte will
 *        have bit 7 set to 1 automatically (as is required for time control). The IBI interrupt will occur after the
 *        1st (mandatory) IBIDATA, if any.
 *  0b10..MASTER_REQUEST: Start a Master-Request.
 *  0b11..HOT_JOIN_REQUEST: Start a Hot-Join request. A Hot-Join Request should only be used when the device is
 *        powered on after the I3C bus is already powered up, or when the device is connected using hot insertion
 *        methods (the device is powered up when it is physically inserted onto the powered-up I3C bus). The hot join
 *        will wait for Bus Idle, and SCTRL.EVENT=HOT_JOIN_REQUEST must be set before the slave enable
 *        (SCONFIG.SLVENA).
 */
#define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)
#define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
#define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
/*! IBIDATA - In-Band Interrupt data
 */
#define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)
#define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
#define I3C_SCTRL_PENDINT_SHIFT                  (16U)
/*! PENDINT - Pending interrupt
 */
#define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)
#define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
#define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
/*! ACTSTATE - Activity state (of slave)
 */
#define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)
#define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
#define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
/*! VENDINFO - Vendor information
 */
#define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
/*! @} */

/*! @name SINTSET - Slave Interrupt Set Register */
/*! @{ */
#define I3C_SINTSET_START_MASK                   (0x100U)
#define I3C_SINTSET_START_SHIFT                  (8U)
/*! START - Start interrupt enable
 */
#define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)
#define I3C_SINTSET_MATCHED_MASK                 (0x200U)
#define I3C_SINTSET_MATCHED_SHIFT                (9U)
/*! MATCHED - Match interrupt enable
 */
#define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)
#define I3C_SINTSET_STOP_MASK                    (0x400U)
#define I3C_SINTSET_STOP_SHIFT                   (10U)
/*! STOP - Stop interrupt enable
 */
#define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)
#define I3C_SINTSET_RXPEND_MASK                  (0x800U)
#define I3C_SINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - Receive interrupt enable
 */
#define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)
#define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
#define I3C_SINTSET_TXSEND_SHIFT                 (12U)
/*! TXSEND - Transmit interrupt enable
 */
#define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)
#define I3C_SINTSET_DACHG_MASK                   (0x2000U)
#define I3C_SINTSET_DACHG_SHIFT                  (13U)
/*! DACHG - Dynamic address change interrupt enable
 */
#define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)
#define I3C_SINTSET_CCC_MASK                     (0x4000U)
#define I3C_SINTSET_CCC_SHIFT                    (14U)
/*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable
 */
#define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)
#define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error/warning interrupt enable
 */
#define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)
#define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - Double Data Rate (DDR) interrupt enable
 */
#define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)
#define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
#define I3C_SINTSET_CHANDLED_SHIFT               (17U)
/*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable
 */
#define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)
#define I3C_SINTSET_EVENT_MASK                   (0x40000U)
#define I3C_SINTSET_EVENT_SHIFT                  (18U)
/*! EVENT - Event interrupt enable
 */
#define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
/*! @} */

/*! @name SINTCLR - Slave Interrupt Clear Register */
/*! @{ */
#define I3C_SINTCLR_START_MASK                   (0x100U)
#define I3C_SINTCLR_START_SHIFT                  (8U)
/*! START - START interrupt enable clear
 */
#define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)
#define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
#define I3C_SINTCLR_MATCHED_SHIFT                (9U)
/*! MATCHED - MATCHED interrupt enable clear
 */
#define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)
#define I3C_SINTCLR_STOP_MASK                    (0x400U)
#define I3C_SINTCLR_STOP_SHIFT                   (10U)
/*! STOP - STOP interrupt enable clear
 */
#define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)
#define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear
 */
#define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)
#define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
#define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
/*! TXSEND - TXSEND interrupt enable clear
 */
#define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)
#define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
#define I3C_SINTCLR_DACHG_SHIFT                  (13U)
/*! DACHG - DACHG interrupt enable clear
 */
#define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)
#define I3C_SINTCLR_CCC_MASK                     (0x4000U)
#define I3C_SINTCLR_CCC_SHIFT                    (14U)
/*! CCC - CCC interrupt enable clear
 */
#define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)
#define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear
 */
#define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)
#define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
#define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
/*! DDRMATCHED - DDRMATCHED interrupt enable clear
 */
#define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)
#define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
#define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
/*! CHANDLED - CHANDLED interrupt enable clear
 */
#define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)
#define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
#define I3C_SINTCLR_EVENT_SHIFT                  (18U)
/*! EVENT - EVENT interrupt enable clear
 */
#define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
/*! @} */

/*! @name SINTMASKED - Slave Interrupt Mask Register */
/*! @{ */
#define I3C_SINTMASKED_START_MASK                (0x100U)
#define I3C_SINTMASKED_START_SHIFT               (8U)
/*! START - START interrupt mask
 */
#define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)
#define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
#define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
/*! MATCHED - MATCHED interrupt mask
 */
#define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)
#define I3C_SINTMASKED_STOP_MASK                 (0x400U)
#define I3C_SINTMASKED_STOP_SHIFT                (10U)
/*! STOP - STOP interrupt mask
 */
#define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)
#define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask
 */
#define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)
#define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
#define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
/*! TXSEND - TXSEND interrupt mask
 */
#define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)
#define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
#define I3C_SINTMASKED_DACHG_SHIFT               (13U)
/*! DACHG - DACHG interrupt mask
 */
#define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)
#define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
#define I3C_SINTMASKED_CCC_SHIFT                 (14U)
/*! CCC - CCC interrupt mask
 */
#define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)
#define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask
 */
#define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)
#define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
#define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
/*! DDRMATCHED - DDRMATCHED interrupt mask
 */
#define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)
#define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
#define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
/*! CHANDLED - CHANDLED interrupt mask
 */
#define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)
#define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
#define I3C_SINTMASKED_EVENT_SHIFT               (18U)
/*! EVENT - EVENT interrupt mask
 */
#define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
/*! @} */

/*! @name SERRWARN - Slave Errors and Warnings Register */
/*! @{ */
#define I3C_SERRWARN_ORUN_MASK                   (0x1U)
#define I3C_SERRWARN_ORUN_SHIFT                  (0U)
/*! ORUN - Overrun error
 */
#define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)
#define I3C_SERRWARN_URUN_MASK                   (0x2U)
#define I3C_SERRWARN_URUN_SHIFT                  (1U)
/*! URUN - Underrun error
 */
#define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)
#define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
#define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
/*! URUNNACK - Underrun and Not Acknowledged (NACKed) error
 */
#define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)
#define I3C_SERRWARN_TERM_MASK                   (0x8U)
#define I3C_SERRWARN_TERM_SHIFT                  (3U)
/*! TERM - Terminated error
 */
#define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)
#define I3C_SERRWARN_INVSTART_MASK               (0x10U)
#define I3C_SERRWARN_INVSTART_SHIFT              (4U)
/*! INVSTART - Invalid start error
 */
#define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)
#define I3C_SERRWARN_SPAR_MASK                   (0x100U)
#define I3C_SERRWARN_SPAR_SHIFT                  (8U)
/*! SPAR - SDR parity error
 */
#define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)
#define I3C_SERRWARN_HPAR_MASK                   (0x200U)
#define I3C_SERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - HDR parity error
 */
#define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)
#define I3C_SERRWARN_HCRC_MASK                   (0x400U)
#define I3C_SERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - HDR-DDR CRC error
 */
#define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)
#define I3C_SERRWARN_S0S1_MASK                   (0x800U)
#define I3C_SERRWARN_S0S1_SHIFT                  (11U)
/*! S0S1 - S0 or S1 error
 */
#define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)
#define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_SERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error
 */
#define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)
#define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_SERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error
 */
#define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
/*! @} */

/*! @name SDMACTRL - Slave DMA Control Register */
/*! @{ */
#define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA Read (From-bus) trigger
 *  0b00..DMA not used
 *  0b01..DMA is enabled for 1 frame
 *  0b10..DMA enable
 */
#define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)
#define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA Write (To-bus) trigger
 *  0b00..NOT_USED: DMA is not used
 *  0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 Frame (ended by DMA or terminated). DMATB auto-clears on a STOP
 *        or START (see the Match START or STOP bit (SCONFIG.MATCHSS).
 *  0b10..ENABLE: DMA is enabled until turned off. Normally, ENABLE should only be used with Master Message mode.
 */
#define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)
#define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - Width of DMA operations
 *  0b00..BYTE
 *  0b01..BYTE_AGAIN
 *  0b10..HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO.
 *  0b11..RESERVED
 */
#define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name SDATACTRL - Slave Data Control Register */
/*! @{ */
#define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush the to-bus buffer/FIFO
 */
#define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)
#define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flushes the from-bus buffer/FIFO
 */
#define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)
#define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
#define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
/*! UNLOCK - Unlock
 */
#define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)
#define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - Trigger level for TX FIFO emptiness
 *  0b00..Trigger on empty
 *  0b01..Trigger on ¼ full or less
 *  0b10..Trigger on .5 full or less
 *  0b11..Trigger on 1 less than full or less (Default)
 */
#define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)
#define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - Trigger level for RX FIFO fullness
 *  0b00..Trigger on not empty
 *  0b01..Trigger on ¼ or more full
 *  0b10..Trigger on .5 or more full
 *  0b11..Trigger on 3/4 or more full
 */
#define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)
#define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - Count of bytes in TX
 */
#define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)
#define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - Count of bytes in RX
 */
#define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)
#define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full
 *  0b1..TX is full
 *  0b0..TX is not full
 */
#define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)
#define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty
 *  0b1..RX is empty
 *  0b0..RX is not empty
 */
#define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name SWDATAB - Slave Write Data Byte Register */
/*! @{ */
#define I3C_SWDATAB_DATA_MASK                    (0xFFU)
#define I3C_SWDATAB_DATA_SHIFT                   (0U)
/*! DATA - The data byte to send to the master
 */
#define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)
#define I3C_SWDATAB_END_MASK                     (0x100U)
#define I3C_SWDATAB_END_SHIFT                    (8U)
/*! END - End
 */
#define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)
#define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End also
 */
#define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name SWDATABE - Slave Write Data Byte End */
/*! @{ */
#define I3C_SWDATABE_DATA_MASK                   (0xFFU)
#define I3C_SWDATABE_DATA_SHIFT                  (0U)
/*! DATA - The data byte to send to the master
 */
#define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
/*! @} */

/*! @name SWDATAH - Slave Write Data Half-word Register */
/*! @{ */
#define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_SWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - The 1st byte to send to the master
 */
#define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)
#define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_SWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - The 2nd byte to send to the master
 */
#define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)
#define I3C_SWDATAH_END_MASK                     (0x10000U)
#define I3C_SWDATAH_END_SHIFT                    (16U)
/*! END - End of message
 */
#define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
/*! @} */

/*! @name SWDATAHE - Slave Write Data Half-word End Register */
/*! @{ */
#define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - The 1st byte to send to the master
 */
#define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)
#define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - The 2nd byte to send to the master
 */
#define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
/*! @} */

/*! @name SRDATAB - Slave Read Data Byte Register */
/*! @{ */
#define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
#define I3C_SRDATAB_DATA0_SHIFT                  (0U)
/*! DATA0 - Byte read from the master
 */
#define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
/*! @} */

/*! @name SRDATAH - Slave Read Data Half-word Register */
/*! @{ */
#define I3C_SRDATAH_LSB_MASK                     (0xFFU)
#define I3C_SRDATAH_LSB_SHIFT                    (0U)
/*! LSB - The 1st byte read from the slave
 */
#define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)
#define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_SRDATAH_MSB_SHIFT                    (8U)
/*! MSB - The 2nd byte read from the slave
 */
#define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
/*! @} */

/*! @name SCAPABILITIES - Slave Capabilities Register */
/*! @{ */
#define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
#define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
/*! IDENA - ID 48b handler
 *  0b00..APPLICATION: Application handles ID 48b
 *  0b01..HW: Hardware handles ID 48b
 *  0b10..HW_BUT: in hardware but the I3C module instance handles ID 48b.
 *  0b11..PARTNO: a part number register (PARTNO) handles ID 48b
 */
#define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)
#define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
#define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
/*! IDREG - ID register
 */
#define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)
#define I3C_SCAPABILITIES_HDRSUPP_MASK           (0x1C0U)
#define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
/*! HDRSUPP - HDR support
 */
#define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)
#define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
#define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
/*! MASTER - Master
 *  0b0..MASTERNOTSUPPORTED: master capability is not supported.
 *  0b1..MASTERSUPPORTED: master capability is supported.
 */
#define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)
#define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
#define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
/*! SADDR - Static address
 *  0b00..NO_STATIC: No static address
 *  0b01..STATIC: Static address is fixed in hardware
 *  0b10..HW_CONTROL: Hardware controls the static address dynamically (for example, from the pin strap)
 *  0b11..CONFIG: SCONFIG register supplies the static address
 */
#define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)
#define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
/*! CCCHANDLE - Common Command Codes (CCC) handling
 */
#define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)
#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
/*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events
 */
#define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)
#define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
#define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
/*! TIMECTRL - Time control
 *  0b0..NO_TIME_CONTROL_TYPE: No time control is enabled
 *  0b1..ATLEAST1_TIME_CONTROL: at least one time-control type is supported
 */
#define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)
#define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
#define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
/*! EXTFIFO - External FIFO
 *  0b001..STD_EXT_FIFO: standard available/free external FIFO
 *  0b011..RESERVED
 */
#define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)
#define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
#define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
/*! FIFOTX - FIFO transmit
 *  0b00..FIFO_2BYTE: 2-byte TX FIFO, the default FIFO transmit value (FIFOTX)
 *  0b01..FIFO_4BYTE: 4-byte TX FIFO
 *  0b10..FIFO_8BYTE: 8-byte TX FIFO
 *  0b11..FIFO_16BYTE: 16-byte TX FIFO
 */
#define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)
#define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
#define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
/*! FIFORX - FIFO receive
 *  0b00..FIFO_2BYTE: 2 (or 3)-byte RX FIFO, the default FIFO receive value (FIFORX)
 *  0b01..FIFO_4BYTE: 4-byte RX FIFO
 *  0b10..FIFO_8BYTE: 8-byte RX FIFO
 *  0b11..FIFO_16BYTE: 16-byte RX FIFO
 */
#define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)
#define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
#define I3C_SCAPABILITIES_INT_SHIFT              (30U)
/*! INT - INT
 *  0b1..Interrupts are supported
 *  0b0..Interrupts are not supported
 */
#define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)
#define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
#define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
/*! DMA - DMA
 *  0b1..DMA is supported
 *  0b0..DMA is not supported
 */
#define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
/*! @} */

/*! @name SDYNADDR - Slave Dynamic Address Register */
/*! @{ */
#define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - DAVALID
 *  0b0..DANOTASSIGNED: a Dynamic Address is not assigned
 *  0b1..DAASSIGNED: a Dynamic Address is assigned
 */
#define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)
#define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address
 */
#define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)
#define I3C_SDYNADDR_MAPIDX_MASK                 (0xF00U)
#define I3C_SDYNADDR_MAPIDX_SHIFT                (8U)
/*! MAPIDX - Mapped Dynamic Address
 */
#define I3C_SDYNADDR_MAPIDX(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPIDX_SHIFT)) & I3C_SDYNADDR_MAPIDX_MASK)
#define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
#define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
/*! MAPSA - Map a Static Address
 */
#define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)
#define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
#define I3C_SDYNADDR_KEY_SHIFT                   (16U)
/*! KEY - Key
 */
#define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
/*! @} */

/*! @name SMAXLIMITS - Slave Maximum Limits Register */
/*! @{ */
#define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
#define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
/*! MAXRD - Maximum read length
 */
#define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)
#define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
#define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
/*! MAXWR - Maximum write length
 */
#define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
/*! @} */

/*! @name SIDPARTNO - Slave ID Part Number Register */
/*! @{ */
#define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
#define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
/*! PARTNO - Part number
 */
#define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
/*! @} */

/*! @name SIDEXT - Slave ID Extension Register */
/*! @{ */
#define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
#define I3C_SIDEXT_DCR_SHIFT                     (8U)
/*! DCR - Device Characteristic Register
 */
#define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)
#define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
#define I3C_SIDEXT_BCR_SHIFT                     (16U)
/*! BCR - Bus Characteristics Register
 */
#define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
/*! @} */

/*! @name SVENDORID - Slave Vendor ID Register */
/*! @{ */
#define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
#define I3C_SVENDORID_VID_SHIFT                  (0U)
/*! VID - Vendor ID
 */
#define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
/*! @} */

/*! @name STCCLOCK - Slave Time Control Clock Register */
/*! @{ */
#define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
#define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
/*! ACCURACY - Clock accuracy
 */
#define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)
#define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
#define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
/*! FREQ - Clock frequency
 */
#define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
/*! @} */

/*! @name SMSGMAPADDR - Slave Message-Mapped Address Register */
/*! @{ */
#define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
#define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
/*! MAPLAST - Matched address index
 */
#define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)
#define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
/*! MAPLASTM1 - Previous match index 1
 */
#define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)
#define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
/*! MAPLASTM2 - Previous match index 2
 */
#define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
/*! @} */

/*! @name MCTRL - Master Main Control Register */
/*! @{ */
#define I3C_MCTRL_REQUEST_MASK                   (0x7U)
#define I3C_MCTRL_REQUEST_SHIFT                  (0U)
/*! REQUEST - Request
 *  0b000..NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's
 *         state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in
 *         progress) or when setting IBI reponse field (IBIRESP) for MSG use
 *  0b001..EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single
 *         Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event
 *         (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be
 *         resubmitted.
 *  0b010..EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment
 *         (DAA) mode, Emit stop will exit DAA mode.
 *  0b011..IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP
 *         has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses
 *         IBIRESP to provide the information.
 *  0b100..PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then
 *         will emit 7E/R to process each slave. Will stop just before the new Dynamic Address (DA) is to be
 *         emitted. The next Process DAA request will use the Addr field as the new DA to assign. If NACKed on the 7E/R,
 *         then the interrupt will indicate this situation, and a STOP will be emitted.
 *  0b101..RESERVED
 *  0b110..FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including
 *         MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band
 *         Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it
 *         does a forced reset (will always reset).
 *  0b111..AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an
 *         In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP.
 */
#define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)
#define I3C_MCTRL_TYPE_MASK                      (0x30U)
#define I3C_MCTRL_TYPE_SHIFT                     (4U)
/*! TYPE - Bus type with START
 *  0b00..I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern.
 *  0b01..I2C: Normally the Standard I2C protocol.
 *  0b10..DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the
 *        module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should
 *        already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware
 *        Reset).
 *  0b11..For ForcedExit, this is forced IBHR.
 */
#define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)
#define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
#define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
/*! IBIRESP - In-Band Interrupt (IBI) response
 *  0b00..ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and
 *        Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field
 *        (MCTRL.RDTERM).
 *  0b01..NACK: Not acknowledge
 *  0b10..ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with
 *        mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt.
 *  0b11..MANUAL: stop and wait for a decision using the IBIAckNack request
 */
#define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)
#define I3C_MCTRL_DIR_MASK                       (0x100U)
#define I3C_MCTRL_DIR_SHIFT                      (8U)
/*! DIR - DIR
 *  0b0..DIRWRITE: Write
 *  0b1..DIRREAD: Read
 */
#define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)
#define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
#define I3C_MCTRL_ADDR_SHIFT                     (9U)
/*! ADDR - ADDR
 */
#define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
#define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
#define I3C_MCTRL_RDTERM_SHIFT                   (16U)
/*! RDTERM - Read terminate
 */
#define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
/*! @} */

/*! @name MSTATUS - Master Status Register */
/*! @{ */
#define I3C_MSTATUS_STATE_MASK                   (0x7U)
#define I3C_MSTATUS_STATE_SHIFT                  (0U)
/*! STATE - State of the master
 *  0b000..IDLE: the bus has STOPped.
 *  0b001..SLVREQ: (Slave Request state) the bus has STOPped but a slave is holding SDA low. If using auto-emit
 *         IBI (MCTRL.AutoIBI), then the master will not stay in the Slave Request state.
 *  0b010..MSGSDR: in Single Data Rate (SDR) Message state (from using MWMSG_SDR)
 *  0b011..NORMACT: normal active Single Data Rate (SDR) state (from using MCTRL and MWDATAn and MRDATAn
 *         registers). The master will stay in the NORMACT state until a STOP is issued.
 *  0b100..MSGDDR: in Double Data Rate (DDR) Message mode (from using MWMSG_DDR or using the normal method with
 *         DDR). The master will stay in the DDR state, until the master exits using EXIT (emits the Exit pattern).
 *  0b101..DAA: in Enter Dynamic Address Assignment (ENTDAA) mode
 *  0b110..IBIACK: waiting for an In-Band Interrupt (IBI) ACK/NACK decision
 *  0b111..IBIRCV: Receiving an In-Band Interrupt (IBI); this IBIRCV state is used after IBI/MR/HJ has won the
 *         arbitration, and IBIRCV state is also used for IBI mandatory byte (if any) and any bytes that follow.
 */
#define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)
#define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
#define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
/*! BETWEEN - Between messages or Dynamic Address Assignments (DAA)
 */
#define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)
#define I3C_MSTATUS_NACKED_MASK                  (0x20U)
#define I3C_MSTATUS_NACKED_SHIFT                 (5U)
/*! NACKED - Not acknowledged
 */
#define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)
#define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
#define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
/*! IBITYPE - In-Band Interrupt (IBI) type
 *  0b00..NONE: cleared when IBI Won bit (MSTATUS.IBIWON) is cleared
 *  0b01..IBI: In-Band Interrupt
 *  0b10..MR: Master Request
 *  0b11..HJ: Hot-Join
 */
#define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)
#define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
#define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start
 */
#define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)
#define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
#define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done
 */
#define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)
#define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
#define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE
 */
#define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)
#define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
#define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND
 */
#define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)
#define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
#define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO not yet full
 */
#define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)
#define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
#define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won
 */
#define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)
#define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
#define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning
 */
#define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)
#define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
#define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this module is a master)
 */
#define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)
#define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
#define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
/*! IBIADDR - IBI address
 */
#define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
/*! @} */

/*! @name MIBIRULES - Master In-band Interrupt Registry and Rules Register */
/*! @{ */
#define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
#define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
/*! ADDR0 - ADDR0
 */
#define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)
#define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
#define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
/*! ADDR1 - ADDR1
 */
#define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)
#define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
#define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
/*! ADDR2 - ADDR2
 */
#define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)
#define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
#define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
/*! ADDR3 - ADDR3
 */
#define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)
#define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
#define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
/*! ADDR4 - ADDR4
 */
#define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)
#define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
#define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
/*! MSB0 - Set Most Significant address Bit to 0
 */
#define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)
#define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
#define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
/*! NOBYTE - No IBI byte
 */
#define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
/*! @} */

/*! @name MINTSET - Master Interrupt Set Register */
/*! @{ */
#define I3C_MINTSET_SLVSTART_MASK                (0x100U)
#define I3C_MINTSET_SLVSTART_SHIFT               (8U)
/*! SLVSTART - Slave start interrupt enable
 */
#define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)
#define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - Master control done interrupt enable
 */
#define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)
#define I3C_MINTSET_COMPLETE_MASK                (0x400U)
#define I3C_MINTSET_COMPLETE_SHIFT               (10U)
/*! COMPLETE - Completed message interrupt enable
 */
#define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)
#define I3C_MINTSET_RXPEND_MASK                  (0x800U)
#define I3C_MINTSET_RXPEND_SHIFT                 (11U)
/*! RXPEND - RX pending interrupt enable
 */
#define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)
#define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable
 */
#define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)
#define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
#define I3C_MINTSET_IBIWON_SHIFT                 (13U)
/*! IBIWON - In-Band Interrupt (IBI) won interrupt enable
 */
#define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)
#define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTSET_ERRWARN_SHIFT                (15U)
/*! ERRWARN - Error or warning (ERRWARN) interrupt enable
 */
#define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)
#define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable
 */
#define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
/*! @} */

/*! @name MINTCLR - Master Interrupt Clear Register */
/*! @{ */
#define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
#define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
/*! SLVSTART - SLVSTART interrupt enable clear
 */
#define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)
#define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
#define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
/*! MCTRLDONE - MCTRLDONE interrupt enable clear
 */
#define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)
#define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
#define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
/*! COMPLETE - COMPLETE interrupt enable clear
 */
#define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)
#define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
#define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
/*! RXPEND - RXPEND interrupt enable clear
 */
#define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)
#define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
#define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
/*! TXNOTFULL - TXNOTFULL interrupt enable clear
 */
#define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)
#define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
#define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
/*! IBIWON - IBIWON interrupt enable clear
 */
#define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)
#define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
#define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
/*! ERRWARN - ERRWARN interrupt enable clear
 */
#define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)
#define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
#define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
/*! NOWMASTER - NOWMASTER interrupt enable clear
 */
#define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
/*! @} */

/*! @name MINTMASKED - Master Interrupt Mask Register */
/*! @{ */
#define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
#define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
/*! SLVSTART - SLVSTART interrupt mask
 */
#define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)
#define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
#define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
/*! MCTRLDONE - MCTRLDONE interrupt mask
 */
#define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)
#define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
#define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
/*! COMPLETE - COMPLETE interrupt mask
 */
#define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)
#define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
#define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
/*! RXPEND - RXPEND interrupt mask
 */
#define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)
#define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
#define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
/*! TXNOTFULL - TXNOTFULL interrupt mask
 */
#define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)
#define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
#define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
/*! IBIWON - IBIWON interrupt mask
 */
#define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)
#define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
#define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
/*! ERRWARN - ERRWARN interrupt mask
 */
#define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)
#define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
#define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
/*! NOWMASTER - NOWMASTER interrupt mask
 */
#define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
/*! @} */

/*! @name MERRWARN - Master Errors and Warnings Register */
/*! @{ */
#define I3C_MERRWARN_NACK_MASK                   (0x4U)
#define I3C_MERRWARN_NACK_SHIFT                  (2U)
/*! NACK - Not acknowledge (NACK) error
 */
#define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)
#define I3C_MERRWARN_WRABT_MASK                  (0x8U)
#define I3C_MERRWARN_WRABT_SHIFT                 (3U)
/*! WRABT - WRABT (Write abort) error
 */
#define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)
#define I3C_MERRWARN_TERM_MASK                   (0x10U)
#define I3C_MERRWARN_TERM_SHIFT                  (4U)
/*! TERM - Terminate error
 */
#define I3C_MERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)
#define I3C_MERRWARN_HPAR_MASK                   (0x200U)
#define I3C_MERRWARN_HPAR_SHIFT                  (9U)
/*! HPAR - High data rate parity
 */
#define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)
#define I3C_MERRWARN_HCRC_MASK                   (0x400U)
#define I3C_MERRWARN_HCRC_SHIFT                  (10U)
/*! HCRC - High data rate CRC error
 */
#define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)
#define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
#define I3C_MERRWARN_OREAD_SHIFT                 (16U)
/*! OREAD - Over-read error
 */
#define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)
#define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
#define I3C_MERRWARN_OWRITE_SHIFT                (17U)
/*! OWRITE - Over-write error
 */
#define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)
#define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
#define I3C_MERRWARN_MSGERR_SHIFT                (18U)
/*! MSGERR - Message error
 */
#define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)
#define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
#define I3C_MERRWARN_INVREQ_SHIFT                (19U)
/*! INVREQ - Invalid request error
 */
#define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)
#define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
#define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
/*! TIMEOUT - TIMEOUT error
 */
#define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
/*! @} */

/*! @name MDMACTRL - Master DMA Control Register */
/*! @{ */
#define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
#define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
/*! DMAFB - DMA from bus
 *  0b00..NOT_USED: DMA is not used
 *  0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 frame. DMAFB auto-clears on STOP or repeated START. See MCONFIG.MATCHSS.
 *  0b10..ENABLE: DMA is enabled until the DMA is turned off.
 */
#define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)
#define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
#define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
/*! DMATB - DMA to bus
 *  0b00..NOT_USED: DMA is not used
 *  0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 frame (ended by DMA or Terminated). DMATB auto-clears on STOP or START. See MCONFIG.MATCHSS.
 *  0b10..ENABLE: DMA is enabled until DMA is turned off. Normally DMA ENABLE should only be used in Master Message mode.
 */
#define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)
#define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
#define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
/*! DMAWIDTH - DMA width
 *  0b00..BYTE
 *  0b01..BYTE_AGAIN
 *  0b10..HALF_WORD: Half-word (16 bits). This will make sure that 2 bytes are free/available in FIFO.
 *  0b11..RESERVED
 */
#define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
/*! @} */

/*! @name MDATACTRL - Master Data Control Register */
/*! @{ */
#define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
#define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
/*! FLUSHTB - Flush to-bus buffer/FIFO
 */
#define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)
#define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
#define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
/*! FLUSHFB - Flush from-bus buffer/FIFO
 */
#define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)
#define I3C_MDATACTRL_UNLOCK_MASK                (0x4U)
#define I3C_MDATACTRL_UNLOCK_SHIFT               (2U)
/*! UNLOCK - Unlock
 */
#define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)
#define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
#define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
/*! TXTRIG - TX trigger level
 */
#define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)
#define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
#define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
/*! RXTRIG - RX trigger level
 */
#define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)
#define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
#define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
/*! TXCOUNT - TX byte count
 */
#define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)
#define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
#define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
/*! RXCOUNT - RX byte count
 */
#define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)
#define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
#define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
/*! TXFULL - TX is full
 */
#define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)
#define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
#define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
/*! RXEMPTY - RX is empty
 */
#define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
/*! @} */

/*! @name MWDATAB - Master Write Data Byte Register */
/*! @{ */
#define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MWDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - Data byte
 */
#define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)
#define I3C_MWDATAB_END_MASK                     (0x100U)
#define I3C_MWDATAB_END_SHIFT                    (8U)
/*! END - End of message
 */
#define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)
#define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
#define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
/*! END_ALSO - End of message also
 */
#define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
/*! @} */

/*! @name MWDATABE - Master Write Data Byte End Register */
/*! @{ */
#define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
#define I3C_MWDATABE_VALUE_SHIFT                 (0U)
/*! VALUE - Data
 */
#define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
/*! @} */

/*! @name MWDATAH - Master Write Data Half-word Register */
/*! @{ */
#define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
#define I3C_MWDATAH_DATA0_SHIFT                  (0U)
/*! DATA0 - Data byte 0
 */
#define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)
#define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
#define I3C_MWDATAH_DATA1_SHIFT                  (8U)
/*! DATA1 - Data byte 1
 */
#define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)
#define I3C_MWDATAH_END_MASK                     (0x10000U)
#define I3C_MWDATAH_END_SHIFT                    (16U)
/*! END - End of message
 */
#define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
/*! @} */

/*! @name MWDATAHE - Master Write Data Byte End Register */
/*! @{ */
#define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
#define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
/*! DATA0 - DATA 0
 */
#define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)
#define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
#define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
/*! DATA1 - DATA 1
 */
#define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
/*! @} */

/*! @name MRDATAB - Master Read Data Byte Register */
/*! @{ */
#define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
#define I3C_MRDATAB_VALUE_SHIFT                  (0U)
/*! VALUE - VALUE
 */
#define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
/*! @} */

/*! @name MRDATAH - Master Read Data Half-word Register */
/*! @{ */
#define I3C_MRDATAH_LSB_MASK                     (0xFFU)
#define I3C_MRDATAH_LSB_SHIFT                    (0U)
/*! LSB - LSB
 */
#define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)
#define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
#define I3C_MRDATAH_MSB_SHIFT                    (8U)
/*! MSB - MSB
 */
#define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
/*! @} */

/*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
/*! @{ */
#define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
/*! DIR - Direction
 *  0b0..Write
 *  0b1..Read
 */
#define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)
#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
/*! ADDR - Address to be written to
 */
#define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)
#define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
#define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
/*! END - End of SDR message
 */
#define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)
#define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
/*! I2C - I2C
 *  0b0..I3C message
 *  0b1..I2C message
 */
#define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)
#define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
/*! LEN - Length
 */
#define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
/*! @} */

/*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
/*! @{ */
#define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data
 */
#define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
#define I3C_MWMSG_SDR_DATA_END_MASK              (0x10000U)
#define I3C_MWMSG_SDR_DATA_END_SHIFT             (16U)
/*! END - End of message
 */
#define I3C_MWMSG_SDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_END_SHIFT)) & I3C_MWMSG_SDR_DATA_END_MASK)
/*! @} */

/*! @name MRMSG_SDR - Master Read Message in SDR mode */
/*! @{ */
#define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
/*! DATA - Data
 */
#define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
/*! @} */

/*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
/*! @{ */
#define I3C_MWMSG_DDR_CONTROL_LEN_MASK           (0x3FFU)
#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT          (0U)
/*! LEN - Length of message
 */
#define I3C_MWMSG_DDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK)
#define I3C_MWMSG_DDR_CONTROL_END_MASK           (0x4000U)
#define I3C_MWMSG_DDR_CONTROL_END_SHIFT          (14U)
/*! END - End of message
 */
#define I3C_MWMSG_DDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK)
/*! @} */

/*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
/*! @{ */
#define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
/*! DATA16B - Data
 */
#define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
#define I3C_MWMSG_DDR_DATA_END_MASK              (0x10000U)
#define I3C_MWMSG_DDR_DATA_END_SHIFT             (16U)
/*! END - End of message
 */
#define I3C_MWMSG_DDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_END_SHIFT)) & I3C_MWMSG_DDR_DATA_END_MASK)
/*! @} */

/*! @name MRMSG_DDR - Master Read Message in DDR mode */
/*! @{ */
#define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
#define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
/*! DATA - Data
 */
#define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
#define I3C_MRMSG_DDR_CLEN_MASK                  (0x3FF0000U)
#define I3C_MRMSG_DDR_CLEN_SHIFT                 (16U)
/*! CLEN - Current length
 */
#define I3C_MRMSG_DDR_CLEN(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_CLEN_SHIFT)) & I3C_MRMSG_DDR_CLEN_MASK)
/*! @} */

/*! @name MDYNADDR - Master Dynamic Address Register */
/*! @{ */
#define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
#define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
/*! DAVALID - Dynamic address valid
 */
#define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)
#define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
#define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
/*! DADDR - Dynamic address
 */
#define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
/*! @} */

/*! @name SID - Slave Module ID Register */
/*! @{ */
#define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
#define I3C_SID_ID_SHIFT                         (0U)
/*! ID - ID
 */
#define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group I3C_Register_Masks */


/* I3C - Peripheral instance base addresses */
/** Peripheral I3C0 base address */
#define I3C0_BASE                                (0x40036000u)
/** Peripheral I3C0 base pointer */
#define I3C0                                     ((I3C_Type *)I3C0_BASE)
/** Peripheral I3C1 base address */
#define I3C1_BASE                                (0x40037000u)
/** Peripheral I3C1 base pointer */
#define I3C1                                     ((I3C_Type *)I3C1_BASE)
/** Array initializer of I3C peripheral base addresses */
#define I3C_BASE_ADDRS                           { I3C0_BASE, I3C1_BASE }
/** Array initializer of I3C peripheral base pointers */
#define I3C_BASE_PTRS                            { I3C0, I3C1 }

/*!
 * @}
 */ /* end of group I3C_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- INPUTMUX Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
 * @{
 */

/** INPUTMUX - Register Layout Typedef */
typedef struct {
  __IO uint32_t SCT0_IN_SEL[7];                    /**< SCT Peripheral Input multiplexer 0..SCT Peripheral Input multiplexer 6, array offset: 0x0, array step: 0x4 */
       uint8_t RESERVED_0[228];
  __IO uint32_t PINT_SEL[8];                       /**< GPIO Pin Input Multiplexer 0..GPIO Pin Input Multiplexer 7, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[32];
  __IO uint32_t DSP_INT_SEL[27];                   /**< Fusion DSP Interrupt Input Multiplexer, array offset: 0x140, array step: 0x4 */
       uint8_t RESERVED_2[84];
  __IO uint32_t DMAC0_ITRIG_SEL[37];               /**< DMAC0 Input Trigger Select, array offset: 0x200, array step: 0x4 */
       uint8_t RESERVED_3[108];
  __IO uint32_t DMAC0_OTRIG_SEL[4];                /**< DMAC0 Output Trigger Select, array offset: 0x300, array step: 0x4 */
       uint8_t RESERVED_4[16];
  __IO uint32_t DMAC0_CHMUX_SEL[16];               /**< DMAC0 Channel mux select 0..DMAC0 Channel mux select 15, array offset: 0x320, array step: 0x4 */
       uint8_t RESERVED_5[160];
  __IO uint32_t DMAC1_ITRIG_SEL[37];               /**< DMAC1 Input Trigger Select, array offset: 0x400, array step: 0x4 */
       uint8_t RESERVED_6[108];
  __IO uint32_t DMAC1_OTRIG_SEL[4];                /**< DMAC0 Output Trigger Select, array offset: 0x500, array step: 0x4 */
       uint8_t RESERVED_7[16];
  __IO uint32_t DMAC1_CHMUX_SEL[16];               /**< DMAC1 Channel mux select 0..DMAC1 Channel mux select 15, array offset: 0x520, array step: 0x4 */
       uint8_t RESERVED_8[160];
  __IO uint32_t CT32BIT_CAP_SEL[5][4];             /**< CT32BIT Timer Capture Multiplexers, array offset: 0x600, array step: index*0x10, index2*0x4 */
       uint8_t RESERVED_9[176];
  __IO uint32_t FMEASURE_CH_SEL[2];                /**< Frequency Measurement Input Channel Multiplexers, array offset: 0x700, array step: 0x4 */
       uint8_t RESERVED_10[24];
  __IO uint32_t SMART_DMA_TRIG_CH_SEL[8];          /**< SMART_DMA trigger channel select, array offset: 0x720, array step: 0x4 */
  __IO uint32_t DMAC0_REQ_ENA0;                    /**< DMAC0 request enable 0, offset: 0x740 */
  __IO uint32_t DMAC0_REQ_ENA1;                    /**< DMAC0 request enable 1, offset: 0x744 */
  __IO uint32_t DMAC0_REQ_ENA0_SET;                /**< DMAC0 request enable set 0, offset: 0x748 */
  __IO uint32_t DMAC0_REQ_ENA1_SET;                /**< DMAC0 request enable set 1, offset: 0x74C */
  __IO uint32_t DMAC0_REQ_ENA0_CLR;                /**< DMAC0 request enable clear 0, offset: 0x750 */
  __IO uint32_t DMAC0_REQ_ENA1_CLR;                /**< DMAC0 request enable 1 clear, offset: 0x754 */
       uint8_t RESERVED_11[8];
  __IO uint32_t DMAC1_REQ_ENA0;                    /**< DMAC1 request enable 0, offset: 0x760 */
  __IO uint32_t DMAC1_REQ_ENA1;                    /**< DMAC1 request enable 1, offset: 0x764 */
  __IO uint32_t DMAC1_REQ_ENA0_SET;                /**< DMAC1 request enable set 0, offset: 0x768 */
  __IO uint32_t DMAC1_REQ_ENA1_SET;                /**< DMAC1 request enable set 1, offset: 0x76C */
  __IO uint32_t DMAC1_REQ_ENA0_CLR;                /**< DMAC1 request enable clear 0, offset: 0x770 */
  __IO uint32_t DMAC1_REQ_ENA1_CLR;                /**< DMAC1 request enable 1 clear, offset: 0x774 */
       uint8_t RESERVED_12[8];
  __IO uint32_t DMAC0_ITRIG_ENA0;                  /**< DMAC0 Input Trigger Enable 0, offset: 0x780 */
       uint8_t RESERVED_13[4];
  __O  uint32_t DMAC0_ITRIG_ENA0_SET;              /**< DMAC0 Input Trigger Enable 0 Set, offset: 0x788 */
       uint8_t RESERVED_14[4];
  __O  uint32_t DMAC0_ITRIG_ENA0_CLR;              /**< DMAC0 Input Trigger Enable 0 Clear, offset: 0x790 */
       uint8_t RESERVED_15[12];
  __IO uint32_t DMAC1_ITRIG_ENA0;                  /**< DMAC1 Input Trigger Enable 0, offset: 0x7A0 */
       uint8_t RESERVED_16[4];
  __O  uint32_t DMAC1_ITRIG_ENA0_SET;              /**< DMAC1 Input Trigger Enable 0 set, offset: 0x7A8 */
       uint8_t RESERVED_17[4];
  __O  uint32_t DMAC1_ITRIG_ENA0_CLR;              /**< DMAC1 Input Trigger Enable 0 clear, offset: 0x7B0 */
} INPUTMUX_Type;

/* ----------------------------------------------------------------------------
   -- INPUTMUX Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
 * @{
 */

/*! @name SCT0_IN_SEL - SCT Peripheral Input multiplexer 0..SCT Peripheral Input multiplexer 6 */
/*! @{ */
#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_MASK     (0x1FU)
#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_SHIFT    (0U)
/*! SCT_IN_SEL - SCT0 Input Selection.
 *  0b00000..SCT0_PIN_INP0
 *  0b00001..SCT0_PIN_INP1
 *  0b00010..SCT0_PIN_INP2
 *  0b00011..SCT0_PIN_INP3
 *  0b00100..SCT0_PIN_INP4
 *  0b00101..SCT0_PIN_INP5
 *  0b00110..SCT0_PIN_INP6
 *  0b00111..SCT0_PIN_INP7
 *  0b01000..CT32BIT0_MAT0
 *  0b01001..CT32BIT1_MAT0
 *  0b01010..CT32BIT2_MAT0
 *  0b01011..CT32BIT3_MAT0
 *  0b01100..CT32BIT4_MAT0
 *  0b01101..ADCIRQ
 *  0b01110..GPIOINT_BMATCH
 *  0b01111..USB0_FRAME_TOGGLE
 *  0b10000..CMP0_OUT
 *  0b10001..SHARED I2S0_SCLK
 *  0b10010..SHARED I2S1_SCLK
 *  0b10011..SHARED I2S0_WS
 *  0b10100..SHARED I2S1_WS
 *  0b10101..MCLK
 *  0b10110..ARM_TXEV
 *  0b10111..DEBUG_HALTED
 *  0b11000..Reserved
 *  0b11001..Reserved
 *  0b11010..Reserved
 *  0b11011..Reserved
 *  0b11100..Reserved
 *  0b11101..Reserved
 *  0b11110..Reserved
 *  0b11111..Reserved
 */
#define INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_SHIFT)) & INPUTMUX_SCT0_IN_SEL_SCT_IN_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_SCT0_IN_SEL */
#define INPUTMUX_SCT0_IN_SEL_COUNT               (7U)

/*! @name PINT_SEL - GPIO Pin Input Multiplexer 0..GPIO Pin Input Multiplexer 7 */
/*! @{ */
#define INPUTMUX_PINT_SEL_PINT_SEL_MASK          (0xFFU)
#define INPUTMUX_PINT_SEL_PINT_SEL_SHIFT         (0U)
/*! PINT_SEL - Interrupt select
 */
#define INPUTMUX_PINT_SEL_PINT_SEL(x)            (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINT_SEL_PINT_SEL_SHIFT)) & INPUTMUX_PINT_SEL_PINT_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_PINT_SEL */
#define INPUTMUX_PINT_SEL_COUNT                  (8U)

/*! @name DSP_INT_SEL - Fusion DSP Interrupt Input Multiplexer */
/*! @{ */
#define INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_MASK    (0x3FU)
#define INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_SHIFT   (0U)
/*! DSP_INT_SEL
 *  0b000000..FLEXCOMM0_IRQ
 *  0b000001..FLEXCOMM1_IRQ
 *  0b000010..FLEXCOMM2_IRQ
 *  0b000011..FLEXCOMM3_IRQ
 *  0b000100..FLEXCOMM4_IRQ
 *  0b000101..FLEXCOMM5_IRQ
 *  0b000110..FLEXCOMM6_IRQ
 *  0b000111..FLEXCOMM7_IRQ
 *  0b001000..FLEXCOMM14_IRQ
 *  0b001001..FLEXCOMM16_IRQ
 *  0b001010..GPIO_INT0_IRQ0
 *  0b001011..GPIO_INT0_IRQ1
 *  0b001100..GPIO_INT0_IRQ2
 *  0b001101..GPIO_INT0_IRQ3
 *  0b001110..GPIO_INT0_IRQ4
 *  0b001111..GPIO_INT0_IRQ5
 *  0b010000..GPIO_INT0_IRQ6
 *  0b010001..GPIO_INT0_IRQ7
 *  0b010010..NSHSGPIO_INT0_IRQ0
 *  0b010011..NSHSGPIO_INT1_IRQ1
 *  0b010100..WDT1
 *  0b010101..DMAC0_IRQ
 *  0b010110..DMAC1_IRQ
 *  0b010111..MU_B_IRQ
 *  0b011000..UTICK0_IRQ
 *  0b011001..MRT0_IRQ
 *  0b011010..OS_EVENT_TIMER or OS_EVENT_WAKEUP
 *  0b011011..CTIMER0
 *  0b011100..CTIMER1
 *  0b011101..CTIMER2
 *  0b011110..CTIMER3
 *  0b011111..CTIMER4
 *  0b100000..RTC_LITE0_ALARM or RTC_LITE0_WAKEUP
 *  0b100001..I3C0
 *  0b100010..I3C1
 *  0b100011..DMIC0
 *  0b100100..HWVAD
 *  0b100101..LCDIF_IRQ
 *  0b100110..GPU_IRQ
 *  0b100111..SMARTDMA_IRQ
 *  0b101000..FLEXIO_IRQ
 */
#define INPUTMUX_DSP_INT_SEL_DSP_INT_SEL(x)      (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_SHIFT)) & INPUTMUX_DSP_INT_SEL_DSP_INT_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DSP_INT_SEL */
#define INPUTMUX_DSP_INT_SEL_COUNT               (27U)

/*! @name DMAC0_ITRIG_SEL - DMAC0 Input Trigger Select */
/*! @{ */
#define INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_MASK (0x1FU)
#define INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_SHIFT (0U)
/*! DMAC0_ITRIG_SEL - DMA Input Trigger Selection.
 *  0b00000..GPIO_INT0
 *  0b00001..GPIO_INT1
 *  0b00010..GPIO_INT2
 *  0b00011..GPIO_INT3
 *  0b00100..T0_DMAREQ_M0
 *  0b00101..T0_DMAREQ_M1
 *  0b00110..T1_DMAREQ_M0
 *  0b00111..T1_DMAREQ_M1
 *  0b01000..T2_DMAREQ_M0
 *  0b01001..T2_DMAREQ_M1
 *  0b01010..T3_DMAREQ_M0
 *  0b01011..T3_DMAREQ_M1
 *  0b01100..T4_DMAREQ_M0
 *  0b01101..T4_DMAREQ_M1
 *  0b01110..DMA0_TRIGOUT_A
 *  0b01111..DMA0_TRIGOUT_B
 *  0b10000..DMA0_TRIGOUT_C
 *  0b10001..DMA0_TRIGOUT_D
 *  0b10010..SCT_DMAC0_REQ0
 *  0b10011..SCT_DMAC1_REQ1
 *  0b10100..HASHCRYPT_OUT_DMA
 *  0b10101..ACMP_DMA
 *  0b10110..FlexSPI0_RX_DMA
 *  0b10111..FlexSPI0_TX_DMA
 *  0b11000..ADC_DMA
 *  0b11001..FlexSPI1_RX_DMA
 *  0b11010..FlexSPI1_TX_DMA
 */
#define INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_SHIFT)) & INPUTMUX_DMAC0_ITRIG_SEL_DMAC0_ITRIG_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DMAC0_ITRIG_SEL */
#define INPUTMUX_DMAC0_ITRIG_SEL_COUNT           (37U)

/*! @name DMAC0_OTRIG_SEL - DMAC0 Output Trigger Select */
/*! @{ */
#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_MASK (0x3FU)
#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_SHIFT (0U)
/*! DMAC0_OTRIG_SEL
 *  0b000000..DMAC0_OTRIG_CH0
 *  0b000001..DMAC0_OTRIG_CH1
 *  0b000010..DMAC0_OTRIG_CH2
 *  0b000011..DMAC0_OTRIG_CH3
 *  0b000100..DMAC0_OTRIG_CH4
 *  0b000101..DMAC0_OTRIG_CH5
 *  0b000110..DMAC0_OTRIG_CH6
 *  0b000111..DMAC0_OTRIG_CH7
 *  0b001000..DMAC0_OTRIG_CH8
 *  0b001001..DMAC0_OTRIG_CH9
 *  0b001010..DMAC0_OTRIG_CH10
 *  0b001011..DMAC0_OTRIG_CH11
 *  0b001100..DMAC0_OTRIG_CH12
 *  0b001101..DMAC0_OTRIG_CH13
 *  0b001110..DMAC0_OTRIG_CH14
 *  0b001111..DMAC0_OTRIG_CH15
 *  0b010000..DMAC0_OTRIG_CH16
 *  0b010001..DMAC0_OTRIG_CH17
 *  0b010010..DMAC0_OTRIG_CH18
 *  0b010011..DMAC0_OTRIG_CH19
 *  0b010100..DMAC0_OTRIG_CH20
 *  0b010101..DMAC0_OTRIG_CH21
 *  0b010110..DMAC0_OTRIG_CH22
 *  0b010111..DMAC0_OTRIG_CH23
 *  0b011000..DMAC0_OTRIG_CH24
 *  0b011001..DMAC0_OTRIG_CH25
 *  0b011010..DMAC0_OTRIG_CH26
 *  0b011011..DMAC0_OTRIG_CH27
 *  0b011100..DMAC0_OTRIG_CH28
 *  0b011101..DMAC0_OTRIG_CH29
 *  0b011110..DMAC0_OTRIG_CH30
 *  0b011111..DMAC0_OTRIG_CH31
 *  0b100000..DMAC0_OTRIG_CH32
 *  0b100001..DMAC0_OTRIG_CH33
 *  0b100010..DMAC0_OTRIG_CH34
 *  0b100011..DMAC0_OTRIG_CH35
 *  0b100100..DMAC0_OTRIG_CH36
 */
#define INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_SHIFT)) & INPUTMUX_DMAC0_OTRIG_SEL_DMAC0_OTRIG_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DMAC0_OTRIG_SEL */
#define INPUTMUX_DMAC0_OTRIG_SEL_COUNT           (4U)

/*! @name DMAC0_CHMUX_SEL - DMAC0 Channel mux select 0..DMAC0 Channel mux select 15 */
/*! @{ */
#define INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_MASK (0x1U)
#define INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_SHIFT (0U)
/*! DMAC0_CHMUX_SEL - DMAC0 Channel mux select 1
 *  0b0..DMIC_CH0_DMA
 *  0b1..FLEXCOM8_RX_DMA
 */
#define INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_SHIFT)) & INPUTMUX_DMAC0_CHMUX_SEL_DMAC0_CHMUX_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DMAC0_CHMUX_SEL */
#define INPUTMUX_DMAC0_CHMUX_SEL_COUNT           (16U)

/*! @name DMAC1_ITRIG_SEL - DMAC1 Input Trigger Select */
/*! @{ */
#define INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_MASK (0x1FU)
#define INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_SHIFT (0U)
/*! DMAC1_ITRIG_SEL - DMA Input Trigger Selection.
 *  0b00000..GPIO_INT0
 *  0b00001..GPIO_INT1
 *  0b00010..GPIO_INT2
 *  0b00011..GPIO_INT3
 *  0b00100..T0_DMAREQ_M0
 *  0b00101..T0_DMAREQ_M1
 *  0b00110..T1_DMAREQ_M0
 *  0b00111..T1_DMAREQ_M1
 *  0b01000..T2_DMAREQ_M0
 *  0b01001..T2_DMAREQ_M1
 *  0b01010..T3_DMAREQ_M0
 *  0b01011..T3_DMAREQ_M1
 *  0b01100..T4_DMAREQ_M0
 *  0b01101..T4_DMAREQ_M1
 *  0b01110..DMA0_TRIGOUT_A
 *  0b01111..DMA0_TRIGOUT_B
 *  0b10000..DMA0_TRIGOUT_C
 *  0b10001..DMA0_TRIGOUT_D
 *  0b10010..SCT_DMAC0_REQ0
 *  0b10011..SCT_DMAC1_REQ1
 *  0b10100..HASHCRYPT_OUT_DMA
 *  0b10101..ACMP_DMA
 *  0b10110..FlexSPI0_RX_DMA
 *  0b10111..FlexSPI0_TX_DMA
 *  0b11000..ADC_DMA
 *  0b11001..FlexSPI1_RX_DMA
 *  0b11010..FlexSPI1_TX_DMA
 */
#define INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_SHIFT)) & INPUTMUX_DMAC1_ITRIG_SEL_DMAC1_ITRIG_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DMAC1_ITRIG_SEL */
#define INPUTMUX_DMAC1_ITRIG_SEL_COUNT           (37U)

/*! @name DMAC1_OTRIG_SEL - DMAC0 Output Trigger Select */
/*! @{ */
#define INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_MASK (0x3FU)
#define INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_SHIFT (0U)
/*! DMAC1_OTRIG_SEL - DMA Output Trigger Selection.
 *  0b000000..DMAC1_OTRIG_CH0
 *  0b000001..DMAC1_OTRIG_CH1
 *  0b000010..DMAC1_OTRIG_CH2
 *  0b000011..DMAC1_OTRIG_CH3
 *  0b000100..DMAC1_OTRIG_CH4
 *  0b000101..DMAC1_OTRIG_CH5
 *  0b000110..DMAC1_OTRIG_CH6
 *  0b000111..DMAC1_OTRIG_CH7
 *  0b001000..DMAC1_OTRIG_CH8
 *  0b001001..DMAC1_OTRIG_CH9
 *  0b001010..DMAC1_OTRIG_CH10
 *  0b001011..DMAC1_OTRIG_CH11
 *  0b001100..DMAC1_OTRIG_CH12
 *  0b001101..DMAC1_OTRIG_CH13
 *  0b001110..DMAC1_OTRIG_CH14
 *  0b001111..DMAC1_OTRIG_CH15
 *  0b010000..DMAC1_OTRIG_CH16
 *  0b010001..DMAC1_OTRIG_CH17
 *  0b010010..DMAC1_OTRIG_CH18
 *  0b010011..DMAC1_OTRIG_CH19
 *  0b010100..DMAC1_OTRIG_CH20
 *  0b010101..DMAC1_OTRIG_CH21
 *  0b010110..DMAC1_OTRIG_CH22
 *  0b010111..DMAC1_OTRIG_CH23
 *  0b011000..DMAC1_OTRIG_CH24
 *  0b011001..DMAC1_OTRIG_CH25
 *  0b011010..DMAC1_OTRIG_CH26
 *  0b011011..DMAC1_OTRIG_CH27
 *  0b011100..DMAC1_OTRIG_CH28
 *  0b011101..DMAC1_OTRIG_CH29
 *  0b011110..DMAC1_OTRIG_CH30
 *  0b011111..DMAC1_OTRIG_CH31
 *  0b100000..DMAC1_OTRIG_CH32
 *  0b100001..DMAC1_OTRIG_CH33
 *  0b100010..DMAC1_OTRIG_CH34
 *  0b100011..DMAC1_OTRIG_CH35
 *  0b100100..DMAC1_OTRIG_CH36
 */
#define INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_SHIFT)) & INPUTMUX_DMAC1_OTRIG_SEL_DMAC1_OTRIG_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DMAC1_OTRIG_SEL */
#define INPUTMUX_DMAC1_OTRIG_SEL_COUNT           (4U)

/*! @name DMAC1_CHMUX_SEL - DMAC1 Channel mux select 0..DMAC1 Channel mux select 15 */
/*! @{ */
#define INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_MASK (0x1U)
#define INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_SHIFT (0U)
/*! DMAC1_CHMUX_SEL - DMAC1 Channel mux select
 *  0b0..DMIC_CH0_DMA
 *  0b1..FLEXCOM8_RX_DMA
 */
#define INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_SHIFT)) & INPUTMUX_DMAC1_CHMUX_SEL_DMAC1_CHMUX_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_DMAC1_CHMUX_SEL */
#define INPUTMUX_DMAC1_CHMUX_SEL_COUNT           (16U)

/*! @name CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL - CT32BIT Timer Capture Multiplexers */
/*! @{ */
#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_MASK (0x1FU)
#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_SHIFT (0U)
/*! CAPn_SEL - Counter Timer n, Capture Input m
 *  0b00000..CT_INP0 (function must be selected in IOPCTL)
 *  0b00001..CT_INP1 (function must be selected in IOPCTL)
 *  0b00010..CT_INP2 (function must be selected in IOPCTL)
 *  0b00011..CT_INP3 (function must be selected in IOPCTL)
 *  0b00100..CT_INP4 (function must be selected in IOPCTL)
 *  0b00101..CT_INP5 (function must be selected in IOPCTL)
 *  0b00110..CT_INP6 (function must be selected in IOPCTL)
 *  0b00111..CT_INP7 (function must be selected in IOPCTL)
 *  0b01000..CT_INP8 (function must be selected in IOPCTL)
 *  0b01001..CT_INP9 (function must be selected in IOPCTL)
 *  0b01010..CT_INP10 (function must be selected in IOPCTL)
 *  0b01011..CT_INP11 (function must be selected in IOPCTL)
 *  0b01100..CT_INP12 (function must be selected in IOPCTL)
 *  0b01101..CT_INP13 (function must be selected in IOPCTL)
 *  0b01110..CT_INP14 (function must be selected in IOPCTL)
 *  0b01111..CT_INP15 (function must be selected in IOPCTL)
 *  0b10000..SHARED I2S0_WS
 *  0b10001..SHARED I2S1_WS
 *  0b10010..USB1_FRAME_TOGGLE (see USB Controller Chapter)
 */
#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_SHIFT)) & INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_CAPn_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL */
#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_COUNT (5U)

/* The count of INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL */
#define INPUTMUX_CT32BITY_CAPX_SEL_CT32BIT_CAP_SEL_COUNT2 (4U)

/*! @name FMEASURE_CH_SEL - Frequency Measurement Input Channel Multiplexers */
/*! @{ */
#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_MASK (0x1FU)
#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_SHIFT (0U)
/*! FMEASURE_SEL - Frequency Measure Channel Selection
 *  0b00000..OSC_CLK
 *  0b00001..FRO_12M
 *  0b00010..FRO_OSC_192M
 *  0b00011..Low Power Oscillator Clock (LPOSC)
 *  0b00100..RTC 32 kHz OSC
 *  0b00101..Main SYSCLK
 *  0b00110..FREQME_GPIO_CLK
 *  0b00111..Reserved
 *  0b01000..Reserved
 *  0b01001..Input Gated Low
 *  0b01010..Input Gated Low
 *  0b01011..Clock Out
 *  0b01100..USB PLL PHY Divider Out
 *  0b01101..PMC Core Digital Out
 *  0b01110..PMC Bias Digital Out
 *  0b01111..OSC32K_SCR Clock Out
 *  0b10000..SYSPLL VCO Divided CLK Out
 *  0b10001..APLL VCO Divided CLK Out
 */
#define INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_SHIFT)) & INPUTMUX_FMEASURE_CH_SEL_FMEASURE_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_FMEASURE_CH_SEL */
#define INPUTMUX_FMEASURE_CH_SEL_COUNT           (2U)

/*! @name SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL - SMART_DMA trigger channel select */
/*! @{ */
#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_MASK (0x7FU)
#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_SHIFT (0U)
/*! SMART_DMA_IN_SEL - SMART_DMA Input(n) Selection
 */
#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_SHIFT)) & INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_SMART_DMA_IN_SEL_MASK)
/*! @} */

/* The count of INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL */
#define INPUTMUX_SMART_DMA_TRIG_CHN_SEL_SMART_DMA_TRIG_CH_SEL_COUNT (8U)

/*! @name DMAC0_REQ_ENA0 - DMAC0 request enable 0 */
/*! @{ */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_MASK (0x1U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_SHIFT (0U)
/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_MASK (0x2U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_SHIFT (1U)
/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM0_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_MASK (0x4U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_SHIFT (2U)
/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_MASK (0x8U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_SHIFT (3U)
/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM1_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_MASK (0x10U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_SHIFT (4U)
/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_MASK (0x20U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_SHIFT (5U)
/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM2_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_MASK (0x40U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_SHIFT (6U)
/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_MASK (0x80U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_SHIFT (7U)
/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM3_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_MASK (0x100U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_SHIFT (8U)
/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_MASK (0x200U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_SHIFT (9U)
/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM4_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_MASK (0x400U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_SHIFT (10U)
/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_MASK (0x800U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_SHIFT (11U)
/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM5_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_MASK (0x1000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_SHIFT (12U)
/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_MASK (0x2000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_SHIFT (13U)
/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM6_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_MASK (0x4000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_SHIFT (14U)
/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_MASK (0x8000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_SHIFT (15U)
/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM7_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_MASK     (0x1000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_SHIFT    (24U)
/*! I3C0_RX - I3C RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C0_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_MASK     (0x2000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_SHIFT    (25U)
/*! I3C0_TX - I3C TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C0_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_MASK (0x4000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_SHIFT (26U)
/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_MASK (0x8000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_SHIFT (27U)
/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM14_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK (0x10000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT (28U)
/*! FLEXCOMM16_RX_FLEXIO_SHFT4 - FLEXCOMM16 RX / FLEXIO SHFT4 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK (0x20000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT (29U)
/*! FLEXCOMM16_TX_FLEXIO_SHFT5 - FLEXCOMM16 RX / FLEXIO_SHFT5 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_MASK (0x40000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_SHIFT (30U)
/*! I3C1_RX_FLEXIO_SHFT6 - I3C1_RX / FLEXIO_SHFT6 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_MASK (0x80000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_SHIFT (31U)
/*! I3C1_TX_FLEXIO_SHFT7 - I3C1_TX / FLEXIO_SHFT7 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_MASK)
/*! @} */

/*! @name DMAC0_REQ_ENA1 - DMAC0 request enable 1 */
/*! @{ */
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK (0x1U)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT (0U)
/*! FLEXIO_SHFT0_FLEXCOMM11_RX - FLEXIO_SHFT0_FLEXCOMM11_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK (0x2U)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT (1U)
/*! FLEXIO_SHFT1_FLEXCOMM11_TX - FLEXIO_SHFT1_FLEXCOMM11_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK (0x4U)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT (2U)
/*! FLEXIO_SHFT2_FLEXCOMM12_RX - FLEXIO_SHFT2_FLEXCOMM12_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK (0x8U)
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT (3U)
/*! FLEXIO_SHFT3_FLEXCOMM12_TX - FLEXIO_SHFT3_FLEXCOMM12_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_MASK (0x10U)
#define INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_SHIFT (4U)
/*! HASHCRYPT_IN - HASHCRYPT_IN
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_HASHCRYPT_IN_MASK)
/*! @} */

/*! @name DMAC0_REQ_ENA0_SET - DMAC0 request enable set 0 */
/*! @{ */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_MASK (0x1U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT (0U)
/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_MASK (0x2U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT (1U)
/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM0_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_MASK (0x4U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT (2U)
/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_MASK (0x8U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT (3U)
/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM1_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_MASK (0x10U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT (4U)
/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_MASK (0x20U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT (5U)
/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM2_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_MASK (0x40U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT (6U)
/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_MASK (0x80U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT (7U)
/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM3_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_MASK (0x100U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT (8U)
/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_MASK (0x200U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT (9U)
/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM4_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_MASK (0x400U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT (10U)
/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_MASK (0x800U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT (11U)
/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM5_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_MASK (0x1000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT (12U)
/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_MASK (0x2000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT (13U)
/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM6_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_MASK (0x4000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT (14U)
/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_MASK (0x8000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT (15U)
/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM7_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM10 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_MASK (0x1000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_SHIFT (24U)
/*! I3C0_RX - I3C RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_MASK (0x2000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_SHIFT (25U)
/*! I3C0_TX - I3C TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C0_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_MASK (0x4000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT (26U)
/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_MASK (0x8000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT (27U)
/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM14_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK (0x10000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT (28U)
/*! FLEXCOMM16_RX_FLEXIO_SHFT4 - FLEXCOMM16 RX / FLEXIO SHFT4 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK (0x20000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT (29U)
/*! FLEXCOMM16_TX_FLEXIO_SHFT5 - FLEXCOMM16 RX / FLEXIO SHFT5 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_MASK (0x40000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_SHIFT (30U)
/*! I3C1_RX_FLEXIO_SHFT6 - I3C1_RX / FLEXIO SHFT6 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_MASK (0x80000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_SHIFT (31U)
/*! I3C1_TX_FLEXIO_SHFT7 - I3C1_TX / FLEXIO_SHFT7 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_MASK)
/*! @} */

/*! @name DMAC0_REQ_ENA1_SET - DMAC0 request enable set 1 */
/*! @{ */
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK (0x1U)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT (0U)
/*! FLEXIO_SHFT0_FLEXCOMM11_RX - FLEXIO_SHFT0_FLEXCOMM11_RX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK (0x2U)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT (1U)
/*! FLEXIO_SHFT1_FLEXCOMM11_TX - FLEXIO_SHFT1_FLEXCOMM11_TX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK (0x4U)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT (2U)
/*! FLEXIO_SHFT2_FLEXCOMM12_RX - FLEXIO_SHFT2_FLEXCOMM12_RX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK (0x8U)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT (3U)
/*! FLEXIO_SHFT3_FLEXCOMM12_TX - FLEXIO_SHFT3_FLEXCOMM12_TX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_MASK (0x10U)
#define INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT (4U)
/*! HASHCRYPT_IN - HASHCRYPT_IN
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_SET_HASHCRYPT_IN_MASK)
/*! @} */

/*! @name DMAC0_REQ_ENA0_CLR - DMAC0 request enable clear 0 */
/*! @{ */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK (0x1U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT (0U)
/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK (0x2U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT (1U)
/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK (0x4U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT (2U)
/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK (0x8U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT (3U)
/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK (0x10U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT (4U)
/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK (0x20U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT (5U)
/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK (0x40U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT (6U)
/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK (0x80U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT (7U)
/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK (0x100U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT (8U)
/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK (0x200U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT (9U)
/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK (0x400U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT (10U)
/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK (0x800U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT (11U)
/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK (0x1000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT (12U)
/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK (0x2000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT (13U)
/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK (0x4000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT (14U)
/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK (0x8000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT (15U)
/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_MASK (0x1000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_SHIFT (24U)
/*! I3C0_RX - I3C RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_MASK (0x2000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_SHIFT (25U)
/*! I3C0_TX - I3C TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C0_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK (0x4000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT (26U)
/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK (0x8000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT (27U)
/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK (0x10000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT (28U)
/*! FLEXCOMM16_RX_FLEXIO_SHFT4 - FLEXCOMM16 RX / FLEXIO SHFT4 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK (0x20000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT (29U)
/*! FLEXCOMM16_TX_FLEXIO_SHFT5 - FLEXCOMM16 RX / FLEXIO SHFT5 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_MASK (0x40000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_SHIFT (30U)
/*! I3C1_RX_FLEXIO_SHFT6 - I3C1_RX / FLEXIO SHFT6 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_MASK)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_MASK (0x80000000U)
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_SHIFT (31U)
/*! I3C1_TX_FLEXIO_SHFT7 - I3C1_TX / FLEXIO SHFT7 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_MASK)
/*! @} */

/*! @name DMAC0_REQ_ENA1_CLR - DMAC0 request enable 1 clear */
/*! @{ */
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK (0x1U)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT (0U)
/*! FLEXIO_SHFT0_FLEXCOMM11_RX - FLEXIO_SHFT0_FLEXCOMM11_RX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK (0x2U)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT (1U)
/*! FLEXIO_SHFT1_FLEXCOMM11_TX - FLEXIO_SHFT1_FLEXCOMM11_TX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK (0x4U)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT (2U)
/*! FLEXIO_SHFT2_FLEXCOMM12_RX - FLEXIO_SHFT2_FLEXCOMM12_RX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK (0x8U)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT (3U)
/*! FLEXIO_SHFT3_FLEXCOMM12_TX - FLEXIO_SHFT3_FLEXCOMM12_TX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_MASK (0x10U)
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT (4U)
/*! HASHCRYPT_IN - HASHCRYPT_IN
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC0_REQ_ENA1_CLR_HASHCRYPT_IN_MASK)
/*! @} */

/*! @name DMAC1_REQ_ENA0 - DMAC1 request enable 0 */
/*! @{ */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_MASK (0x1U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_SHIFT (0U)
/*! FLEXCOMM0_RX - FLEXCOMM0_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_MASK (0x2U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_SHIFT (1U)
/*! FLEXCOMM0_TX - FLEXCOMM0_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM0_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_MASK (0x4U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_SHIFT (2U)
/*! FLEXCOMM1_RX - FLEXCOMM1_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_MASK (0x8U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_SHIFT (3U)
/*! FLEXCOMM1_TX - FLEXCOMM1_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM1_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_MASK (0x10U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_SHIFT (4U)
/*! FLEXCOMM2_RX - FLEXCOMM2_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_MASK (0x20U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_SHIFT (5U)
/*! FLEXCOMM2_TX - FLEXCOMM2_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM2_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_MASK (0x40U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_SHIFT (6U)
/*! FLEXCOMM3_RX - FLEXCOMM3_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_MASK (0x80U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_SHIFT (7U)
/*! FLEXCOMM3_TX - FLEXCOMM3_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM3_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_MASK (0x100U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_SHIFT (8U)
/*! FLEXCOMM4_RX - FLEXCOMM4_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_MASK (0x200U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_SHIFT (9U)
/*! FLEXCOMM4_TX - FLEXCOMM4_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM4_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_MASK (0x400U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_SHIFT (10U)
/*! FLEXCOMM5_RX - FLEXCOMM5_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_MASK (0x800U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_SHIFT (11U)
/*! FLEXCOMM5_TX - FLEXCOMM5_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM5_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_MASK (0x1000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_SHIFT (12U)
/*! FLEXCOMM6_RX - FLEXCOMM6_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_MASK (0x2000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_SHIFT (13U)
/*! FLEXCOMM6_TX - FLEXCOMM6_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM6_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_MASK (0x4000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_SHIFT (14U)
/*! FLEXCOMM7_RX - FLEXCOMM7_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_MASK (0x8000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_SHIFT (15U)
/*! FLEXCOMM7_TX - FLEXCOMM7_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM7_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2/ FLEXCOMM9 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_MASK     (0x1000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_SHIFT    (24U)
/*! I3C0_RX - I3C RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C0_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_MASK     (0x2000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_SHIFT    (25U)
/*! I3C0_TX - I3C TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX(x)       (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C0_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_MASK (0x4000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_SHIFT (26U)
/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_MASK (0x8000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_SHIFT (27U)
/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM14_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK (0x10000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT (28U)
/*! FLEXCOMM16_RX_FLEXIO_SHFT4 - FLEXCOMM16 RX / FLEXIO_SHFT4 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK (0x20000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT (29U)
/*! FLEXCOMM16_TX_FLEXIO_SHFT5 - FLEXCOMM16 RX / FLEXIO_SHFT5 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_MASK (0x40000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_SHIFT (30U)
/*! I3C1_RX_FLEXIO_SHFT6 - I3C1_RX / FLEXIO_SHFT6 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C1_RX_FLEXIO_SHFT6_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_MASK (0x80000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_SHIFT (31U)
/*! I3C1_TX_FLEXIO_SHFT7 - I3C1_TX / FLEXIO_SHFT7 enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_I3C1_TX_FLEXIO_SHFT7_MASK)
/*! @} */

/*! @name DMAC1_REQ_ENA1 - DMAC1 request enable 1 */
/*! @{ */
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK (0x1U)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT (0U)
/*! FLEXIO_SHFT0_FLEXCOMM11_RX - FLEXIO_SHFT0_FLEXCOMM11_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK (0x2U)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT (1U)
/*! FLEXIO_SHFT1_FLEXCOMM11_TX - FLEXIO_SHFT1_FLEXCOMM11_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK (0x4U)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT (2U)
/*! FLEXIO_SHFT2_FLEXCOMM12_RX - FLEXIO_SHFT2_FLEXCOMM12_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK (0x8U)
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT (3U)
/*! FLEXIO_SHFT3_FLEXCOMM12_TX - FLEXIO_SHFT3_FLEXCOMM12_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_MASK (0x10U)
#define INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_SHIFT (4U)
/*! HASHCRYPT_IN - HASHCRYPT_IN
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN(x)  (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_HASHCRYPT_IN_MASK)
/*! @} */

/*! @name DMAC1_REQ_ENA0_SET - DMAC1 request enable set 0 */
/*! @{ */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_MASK (0x1U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT (0U)
/*! FLEXCOMM0_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_MASK (0x2U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT (1U)
/*! FLEXCOMM0_TX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM0_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_MASK (0x4U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT (2U)
/*! FLEXCOMM1_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_MASK (0x8U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT (3U)
/*! FLEXCOMM1_TX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM1_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_MASK (0x10U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT (4U)
/*! FLEXCOMM2_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_MASK (0x20U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT (5U)
/*! FLEXCOMM2_TX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM2_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_MASK (0x40U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT (6U)
/*! FLEXCOMM3_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_MASK (0x80U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT (7U)
/*! FLEXCOMM3_TX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM3_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_MASK (0x100U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT (8U)
/*! FLEXCOMM4_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_MASK (0x200U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT (9U)
/*! FLEXCOMM4_TX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM4_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_MASK (0x400U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT (10U)
/*! FLEXCOMM5_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_MASK (0x800U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT (11U)
/*! FLEXCOMM5_TX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM5_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_MASK (0x1000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT (12U)
/*! FLEXCOMM6_RX
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_MASK (0x2000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT (13U)
/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM6_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_MASK (0x4000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT (14U)
/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_MASK (0x8000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT (15U)
/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM7_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM13_TX_DMA_MASK (0x800000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM13_TX_DMA_SHIFT (23U)
/*! DMIC0_CH3_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_DMIC0_CH3_FLEXCOMM13_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_MASK (0x1000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_SHIFT (24U)
/*! I3C0_RX - I3C RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_MASK (0x2000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_SHIFT (25U)
/*! I3C0_TX - I3C TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C0_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_MASK (0x4000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT (26U)
/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_MASK (0x8000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT (27U)
/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable set
 *  0b0..No effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM14_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK (0x10000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT (28U)
/*! FLEXCOMM16_RX_FLEXIO_SHFT4 - FLEXCOMM16 RX / FLEXIO_SHFT4 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK (0x20000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT (29U)
/*! FLEXCOMM16_TX_FLEXIO_SHFT5 - FLEXCOMM16 RX / FLEXIO_SHFT5 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_MASK (0x40000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_SHIFT (30U)
/*! I3C1_RX_FLEXIO_SHFT6 - I3C1_RX / FLEXIO_SHFT6 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_RX_FLEXIO_SHFT6_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_MASK (0x80000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_SHIFT (31U)
/*! I3C1_TX_FLEXIO_SHFT7 - I3C1_TX / FLEXIO_SHFT7 enable
 *  0b0..No effect
 *  0b1..Sets the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_SET_I3C1_TX_FLEXIO_SHFT7_MASK)
/*! @} */

/*! @name DMAC1_REQ_ENA1_SET - DMAC1 request enable set 1 */
/*! @{ */
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK (0x1U)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT (0U)
/*! FLEXIO_SHFT0_FLEXCOMM11_RX - FLEXIO_SHFT_FLEXCOMM_RX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK (0x2U)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT (1U)
/*! FLEXIO_SHFT1_FLEXCOMM11_TX - FLEXIO_SHFT_FLEXCOMM_TX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK (0x4U)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT (2U)
/*! FLEXIO_SHFT2_FLEXCOMM12_RX - FLEXIO_SHFT2_FLEXCOMM12_RX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK (0x8U)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT (3U)
/*! FLEXIO_SHFT3_FLEXCOMM12_TX - FLEXIO_SHFT3_FLEXCOMM12_TX
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_MASK (0x10U)
#define INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT (4U)
/*! HASHCRYPT_IN - HASHCRYPT_IN
 *  0b0..No Effect
 *  0b1..Sets the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_SET_HASHCRYPT_IN_MASK)
/*! @} */

/*! @name DMAC1_REQ_ENA0_CLR - DMAC1 request enable clear 0 */
/*! @{ */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK (0x1U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT (0U)
/*! FLEXCOMM0_RX - FLEXCOMM0 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK (0x2U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT (1U)
/*! FLEXCOMM0_TX - FLEXCOMM0 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM0_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK (0x4U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT (2U)
/*! FLEXCOMM1_RX - FLEXCOMM1 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK (0x8U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT (3U)
/*! FLEXCOMM1_TX - FLEXCOMM1 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM1_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK (0x10U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT (4U)
/*! FLEXCOMM2_RX - FLEXCOMM2 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK (0x20U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT (5U)
/*! FLEXCOMM2_TX - FLEXCOMM2 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM2_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK (0x40U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT (6U)
/*! FLEXCOMM3_RX - FLEXCOMM3 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK (0x80U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT (7U)
/*! FLEXCOMM3_TX - FLEXCOMM3 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM3_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK (0x100U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT (8U)
/*! FLEXCOMM4_RX - FLEXCOMM4 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK (0x200U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT (9U)
/*! FLEXCOMM4_TX - FLEXCOMM4 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM4_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK (0x400U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT (10U)
/*! FLEXCOMM5_RX - FLEXCOMM5 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK (0x800U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT (11U)
/*! FLEXCOMM5_TX - FLEXCOMM5 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM5_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK (0x1000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT (12U)
/*! FLEXCOMM6_RX - FLEXCOMM6 RX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK (0x2000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT (13U)
/*! FLEXCOMM6_TX - FLEXCOMM6 TX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM6_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK (0x4000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT (14U)
/*! FLEXCOMM7_RX - FLEXCOMM7 RX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK (0x8000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT (15U)
/*! FLEXCOMM7_TX - FLEXCOMM7 TX enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM7_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK (0x10000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT (16U)
/*! DMIC0_CH0_FLEXCOMM8_RX_DMA - DMIC0 channel 0 / FLEXCOMM8_RX_DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH0_FLEXCOMM8_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK (0x20000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT (17U)
/*! DMIC0_CH1_FLEXCOMM8_TX_DMA - DMIC0 channel 1 / FLEXCOMM8 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH1_FLEXCOMM8_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK (0x40000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT (18U)
/*! DMIC0_CH2_FLEXCOMM9_RX_DMA - DMIC0 channel 2 / FLEXCOMM9 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH2_FLEXCOMM9_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK (0x80000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT (19U)
/*! DMIC0_CH3_FLEXCOMM9_TX_DMA - DMIC0 channel 3 / FLEXCOMM9 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH3_FLEXCOMM9_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK (0x100000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT (20U)
/*! DMIC0_CH4_FLEXCOMM10_RX_DMA - DMIC0 channel 4 / FLEXCOMM10 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH4_FLEXCOMM10_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK (0x200000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT (21U)
/*! DMIC0_CH5_FLEXCOMM10_TX_DMA - DMIC0 channel 5 / FLEXCOMM10 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH5_FLEXCOMM10_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK (0x400000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT (22U)
/*! DMIC0_CH6_FLEXCOMM13_RX_DMA - DMIC0 channel 6 / FLEXCOMM13 RX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH6_FLEXCOMM13_RX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK (0x800000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT (23U)
/*! DMIC0_CH7_FLEXCOMM13_TX_DMA - DMIC0 channel 7 / FLEXCOMM13 TX DMA enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_DMIC0_CH7_FLEXCOMM13_TX_DMA_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_MASK (0x1000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_SHIFT (24U)
/*! I3C0_RX - I3C RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_MASK (0x2000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_SHIFT (25U)
/*! I3C0_TX - I3C TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C0_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK (0x4000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT (26U)
/*! FLEXCOMM14_RX - FLEXCOMM14 RX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK (0x8000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT (27U)
/*! FLEXCOMM14_TX - FLEXCOMM14 TX enable clear
 *  0b0..No effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM14_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK (0x10000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT (28U)
/*! FLEXCOMM16_RX_FLEXIO_SHFT4 - FLEXCOMM16 RX / FLEXIO_SHFT4 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_RX_FLEXIO_SHFT4_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK (0x20000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT (29U)
/*! FLEXCOMM16_TX_FLEXIO_SHFT5 - FLEXCOMM16 RX / FLEXIO_SHFT5 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_FLEXCOMM16_TX_FLEXIO_SHFT5_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_MASK (0x40000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_SHIFT (30U)
/*! I3C1_RX_FLEXIO_SHFT6 - I3C1_RX / FLEXIO_SHFT6 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_RX_FLEXIO_SHFT6_MASK)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_MASK (0x80000000U)
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_SHIFT (31U)
/*! I3C1_TX_FLEXIO_SHFT7 - I3C1_TX / FLEXIO_SHFT7 enable
 *  0b0..No effect
 *  0b1..Clears the ENA0 bit
 */
#define INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA0_CLR_I3C1_TX_FLEXIO_SHFT7_MASK)
/*! @} */

/*! @name DMAC1_REQ_ENA1_CLR - DMAC1 request enable 1 clear */
/*! @{ */
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK (0x1U)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT (0U)
/*! FLEXIO_SHFT0_FLEXCOMM11_RX - FLEXIO_SHFT0_FLEXCOMM11_RX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT0_FLEXCOMM11_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK (0x2U)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT (1U)
/*! FLEXIO_SHFT1_FLEXCOMM11_TX - FLEXIO_SHFT1_FLEXCOMM11_TX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT1_FLEXCOMM11_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK (0x4U)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT (2U)
/*! FLEXIO_SHFT2_FLEXCOMM12_RX - FLEXIO_SHFT2_FLEXCOMM12_RX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT2_FLEXCOMM12_RX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK (0x8U)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT (3U)
/*! FLEXIO_SHFT3_FLEXCOMM12_TX - FLEXIO_SHFT3_FLEXCOMM12_TX
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_FLEXIO_SHFT3_FLEXCOMM12_TX_MASK)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_MASK (0x10U)
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT (4U)
/*! HASHCRYPT_IN - HASHCRYPT_IN
 *  0b0..No effect
 *  0b1..Clears the ENA1 Bit
 */
#define INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_SHIFT)) & INPUTMUX_DMAC1_REQ_ENA1_CLR_HASHCRYPT_IN_MASK)
/*! @} */

/*! @name DMAC0_ITRIG_ENA0 - DMAC0 Input Trigger Enable 0 */
/*! @{ */
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_MASK (0x1U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_SHIFT (0U)
/*! GPIO_INT0 - GPIO_INT0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_MASK (0x2U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_SHIFT (1U)
/*! GPIO_INT1 - GPIO_INT1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_MASK (0x4U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_SHIFT (2U)
/*! GPIO_INT2 - GPIO_INT2
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT2_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_MASK (0x8U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_SHIFT (3U)
/*! GPIO_INT3 - GPIO_INT3
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_GPIO_INT3_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_MASK (0x10U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT (4U)
/*! T0_DMAREQ_M0 - T0_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_MASK (0x20U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT (5U)
/*! T0_DMAREQ_M1 - T0_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T0_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_MASK (0x40U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT (6U)
/*! T1_DMAREQ_M0 - T1_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_MASK (0x80U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT (7U)
/*! T1_DMAREQ_M1 - T1_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T1_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_MASK (0x100U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT (8U)
/*! T2_DMAREQ_M0 - T2_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_MASK (0x200U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT (9U)
/*! T2_DMAREQ_M1 - T2_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T2_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_MASK (0x400U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT (10U)
/*! T3_DMAREQ_M0 - T3_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_MASK (0x800U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT (11U)
/*! T3_DMAREQ_M1 - T3_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T3_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_MASK (0x1000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT (12U)
/*! T4_DMAREQ_M0 - T4_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_MASK (0x2000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT (13U)
/*! T4_DMAREQ_M1 - T4_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_T4_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_MASK (0x4000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT (14U)
/*! DMA_TRIGOUT_A - DMA_TRIGOUT_A
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_A_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_MASK (0x8000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT (15U)
/*! DMA_TRIGOUT_B - DMA_TRIGOUT_B
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_B_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_MASK (0x10000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT (16U)
/*! DMA_TRIGOUT_C - DMA_TRIGOUT_C
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_C_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_MASK (0x20000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT (17U)
/*! DMA_TRIGOUT_D - DMA_TRIGOUT_D
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_DMA_TRIGOUT_D_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_MASK (0x40000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT (18U)
/*! SCT_DMA_REQ0 - SCT_DMA_REQ0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_MASK (0x80000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT (19U)
/*! SCT_DMA_REQ1 - SCT_DMA_REQ1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SCT_DMA_REQ1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_MASK (0x100000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT (20U)
/*! HASHCRYPT_OUT - HASHCRYPT_OUT
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_HASHCRYPT_OUT_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_MASK      (0x200000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_SHIFT     (21U)
/*! ACMP - ACMP
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_ACMP(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_ACMP_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_MASK (0x400000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_SHIFT (22U)
/*! FLEXSPI0_RX - FlexSPI0_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_RX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_MASK (0x800000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_SHIFT (23U)
/*! FLEXSPI0_TX - FlexSPI0_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI0_TX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_ADC_MASK       (0x1000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_ADC_SHIFT      (24U)
/*! ADC - ADC
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_ADC(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_ADC_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_ADC_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_MASK (0x2000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_SHIFT (25U)
/*! FLEXSPI1_RX - FlexSPI1_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_RX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT (26U)
/*! FLEXSPI1_TX - FlexSPI1_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK)
/*! @} */

/*! @name DMAC0_ITRIG_ENA0_SET - DMAC0 Input Trigger Enable 0 Set */
/*! @{ */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_MASK (0x1U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_SHIFT (0U)
/*! GPIO_INT0 - GPIO_INT0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_MASK (0x2U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_SHIFT (1U)
/*! GPIO_INT1 - GPIO_INT1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_MASK (0x4U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_SHIFT (2U)
/*! GPIO_INT2 - GPIO_INT2 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT2_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_MASK (0x8U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_SHIFT (3U)
/*! GPIO_INT3 - GPIO_INT3 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_GPIO_INT3_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK (0x10U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT (4U)
/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK (0x20U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT (5U)
/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK (0x40U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT (6U)
/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK (0x80U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT (7U)
/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK (0x100U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT (8U)
/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK (0x200U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT (9U)
/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK (0x400U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT (10U)
/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK (0x800U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT (11U)
/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK (0x1000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT (12U)
/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK (0x2000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT (13U)
/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK (0x4000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT (14U)
/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_Aset
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK (0x8000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT (15U)
/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK (0x10000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT (16U)
/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK (0x20000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT (17U)
/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK (0x40000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT (18U)
/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK (0x80000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT (19U)
/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK (0x100000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT (20U)
/*! HASHCRYPT_OUT - HASHCRYPT_OUT set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_MASK  (0x200000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_SHIFT (21U)
/*! ACMP - ACMP set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_ACMP_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK (0x400000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT (22U)
/*! FLEXSPI0_RX - FlexSPI0_RX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK (0x800000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT (23U)
/*! FLEXSPI0_TX - FlexSPI0_TX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_MASK   (0x1000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_SHIFT  (24U)
/*! ADC - ADC set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_ADC_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK (0x2000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT (25U)
/*! FLEXSPI1_RX - FlexSPI1_RX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK (0x4000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT (26U)
/*! FLEXSPI1_TX - FlexSPI1_TX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK)
/*! @} */

/*! @name DMAC0_ITRIG_ENA0_CLR - DMAC0 Input Trigger Enable 0 Clear */
/*! @{ */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_MASK (0x1U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT (0U)
/*! GPIO_INT0 - GPIO_INT0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_MASK (0x2U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT (1U)
/*! GPIO_INT1 - GPIO_INT1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_MASK (0x4U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT (2U)
/*! GPIO_INT2 - GPIO_INT2 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT2_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_MASK (0x8U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT (3U)
/*! GPIO_INT3 - GPIO_INT3 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_GPIO_INT3_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK (0x10U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT (4U)
/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK (0x20U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT (5U)
/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK (0x40U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT (6U)
/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK (0x80U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT (7U)
/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK (0x100U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT (8U)
/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK (0x200U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT (9U)
/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK (0x400U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT (10U)
/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK (0x800U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT (11U)
/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK (0x1000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT (12U)
/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK (0x2000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT (13U)
/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK (0x4000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT (14U)
/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_A clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK (0x8000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT (15U)
/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK (0x10000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT (16U)
/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK (0x20000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT (17U)
/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK (0x40000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT (18U)
/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK (0x80000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT (19U)
/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK (0x100000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT (20U)
/*! HASHCRYPT_OUT - HASHCRYPT_OUT clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK  (0x200000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT (21U)
/*! ACMP - ACMP clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK (0x400000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT (22U)
/*! FLEXSPI0_RX - FlexSPI0_RX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK (0x800000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT (23U)
/*! FLEXSPI0_TX - FlexSPI0_TX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_MASK   (0x1000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_SHIFT  (24U)
/*! ADC - ADC clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ADC_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK (0x2000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT (25U)
/*! FLEXSPI1_RX - FlexSPI1_RX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK (0x4000000U)
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT (26U)
/*! FLEXSPI1_TX - FlexSPI1_TX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK)
/*! @} */

/*! @name DMAC1_ITRIG_ENA0 - DMAC1 Input Trigger Enable 0 */
/*! @{ */
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_MASK (0x1U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_SHIFT (0U)
/*! GPIO_INT0 - GPIO_INT0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_MASK (0x2U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_SHIFT (1U)
/*! GPIO_INT1 - GPIO_INT1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_MASK (0x4U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_SHIFT (2U)
/*! GPIO_INT2 - GPIO_INT2
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT2_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_MASK (0x8U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_SHIFT (3U)
/*! GPIO_INT3 - GPIO_INT3
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3(x)   (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_GPIO_INT3_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_MASK (0x10U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT (4U)
/*! T0_DMAREQ_M0 - T0_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_MASK (0x20U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT (5U)
/*! T0_DMAREQ_M1 - T0_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T0_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_MASK (0x40U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT (6U)
/*! T1_DMAREQ_M0 - T1_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_MASK (0x80U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT (7U)
/*! T1_DMAREQ_M1 - T1_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T1_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_MASK (0x100U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT (8U)
/*! T2_DMAREQ_M0 - T2_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_MASK (0x200U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT (9U)
/*! T2_DMAREQ_M1 - T2_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T2_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_MASK (0x400U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT (10U)
/*! T3_DMAREQ_M0 - T3_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_MASK (0x800U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT (11U)
/*! T3_DMAREQ_M1 - T3_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T3_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_MASK (0x1000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT (12U)
/*! T4_DMAREQ_M0 - T4_DMAREQ_M0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_MASK (0x2000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT (13U)
/*! T4_DMAREQ_M1 - T4_DMAREQ_M1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_T4_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_MASK (0x4000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT (14U)
/*! DMA_TRIGOUT_A - DMA_TRIGOUT_A
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_A_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_MASK (0x8000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT (15U)
/*! DMA_TRIGOUT_B - DMA_TRIGOUT_B
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_B_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_MASK (0x10000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT (16U)
/*! DMA_TRIGOUT_C - DMA_TRIGOUT_C
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_C_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_MASK (0x20000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT (17U)
/*! DMA_TRIGOUT_D - DMA_TRIGOUT_D
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_DMA_TRIGOUT_D_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_MASK (0x40000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT (18U)
/*! SCT_DMA_REQ0 - SCT_DMA_REQ0
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_MASK (0x80000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT (19U)
/*! SCT_DMA_REQ1 - SCT_DMA_REQ1
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SCT_DMA_REQ1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_MASK (0x100000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT (20U)
/*! HASHCRYPT_OUT - HASHCRYPT_OUT
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_HASHCRYPT_OUT_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_MASK      (0x200000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_SHIFT     (21U)
/*! ACMP - ACMP
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_ACMP(x)        (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_ACMP_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_MASK (0x400000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_SHIFT (22U)
/*! FLEXSPI0_RX - FlexSPI0_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_RX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_MASK (0x800000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_SHIFT (23U)
/*! FLEXSPI0_TX - FlexSPI0_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI0_TX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_ADC_MASK       (0x1000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_ADC_SHIFT      (24U)
/*! ADC - ADC
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_ADC(x)         (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_ADC_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_ADC_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_MASK (0x2000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_SHIFT (25U)
/*! FLEXSPI1_RX - FlexSPI1_RX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_RX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_SHIFT (26U)
/*! FLEXSPI1_TX - FlexSPI1_TX
 *  0b0..Disable
 *  0b1..Enable
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_FLEXSPI1_TX_MASK)
/*! @} */

/*! @name DMAC1_ITRIG_ENA0_SET - DMAC1 Input Trigger Enable 0 set */
/*! @{ */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_MASK (0x1U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_SHIFT (0U)
/*! GPIO_INT0 - GPIO_INT0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_MASK (0x2U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_SHIFT (1U)
/*! GPIO_INT1 - GPIO_INT1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_MASK (0x4U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_SHIFT (2U)
/*! GPIO_INT2 - GPIO_INT2 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT2_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_MASK (0x8U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_SHIFT (3U)
/*! GPIO_INT3 - GPIO_INT3 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_GPIO_INT3_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK (0x10U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT (4U)
/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK (0x20U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT (5U)
/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T0_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK (0x40U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT (6U)
/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK (0x80U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT (7U)
/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T1_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK (0x100U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT (8U)
/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK (0x200U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT (9U)
/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T2_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK (0x400U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT (10U)
/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK (0x800U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT (11U)
/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T3_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK (0x1000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT (12U)
/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK (0x2000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT (13U)
/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_T4_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK (0x4000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT (14U)
/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_A set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_A_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK (0x8000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT (15U)
/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_B_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK (0x10000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT (16U)
/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_C_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK (0x20000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT (17U)
/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SDMA0_TRIGOUT_D_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK (0x40000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT (18U)
/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK (0x80000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT (19U)
/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_SCT_DMA_REQ1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK (0x100000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT (20U)
/*! HASHCRYPT_OUT - HASHCRYPT_OUT set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_HASHCRYPT_OUT_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_MASK  (0x200000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_SHIFT (21U)
/*! ACMP - ACMP set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_ACMP_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK (0x400000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT (22U)
/*! FLEXSPI0_RX - FlexSPI0_RX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_RX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK (0x800000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT (23U)
/*! FLEXSPI0_TX - FlexSPI0_TX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI0_TX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_MASK   (0x1000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_SHIFT  (24U)
/*! ADC - ADC set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_ADC_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK (0x2000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT (25U)
/*! FLEXSPI1_RX - FlexSPI1_RX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_RX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK (0x4000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT (26U)
/*! FLEXSPI1_TX - FlexSPI1_TX set
 *  0b0..No Effect
 *  0b1..Sets the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_SET_FLEXSPI1_TX_MASK)
/*! @} */

/*! @name DMAC1_ITRIG_ENA0_CLR - DMAC1 Input Trigger Enable 0 clear */
/*! @{ */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_MASK (0x1U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT (0U)
/*! GPIO_INT0 - GPIO_INT0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_MASK (0x2U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT (1U)
/*! GPIO_INT1 - GPIO_INT1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_MASK (0x4U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT (2U)
/*! GPIO_INT2 - GPIO_INT2 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT2_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_MASK (0x8U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT (3U)
/*! GPIO_INT3 - GPIO_INT3 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_GPIO_INT3_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK (0x10U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT (4U)
/*! T0_DMAREQ_M0 - T0_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK (0x20U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT (5U)
/*! T0_DMAREQ_M1 - T0_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T0_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK (0x40U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT (6U)
/*! T1_DMAREQ_M0 - T1_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK (0x80U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT (7U)
/*! T1_DMAREQ_M1 - T1_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T1_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK (0x100U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT (8U)
/*! T2_DMAREQ_M0 - T2_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK (0x200U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT (9U)
/*! T2_DMAREQ_M1 - T2_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T2_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK (0x400U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT (10U)
/*! T3_DMAREQ_M0 - T3_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK (0x800U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT (11U)
/*! T3_DMAREQ_M1 - T3_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T3_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK (0x1000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT (12U)
/*! T4_DMAREQ_M0 - T4_DMAREQ_M0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK (0x2000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT (13U)
/*! T4_DMAREQ_M1 - T4_DMAREQ_M1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_T4_DMAREQ_M1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK (0x4000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT (14U)
/*! SDMA0_TRIGOUT_A - SDMA0_TRIGOUT_A clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_A_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK (0x8000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT (15U)
/*! SDMA0_TRIGOUT_B - SDMA0_TRIGOUT_B clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_B_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK (0x10000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT (16U)
/*! SDMA0_TRIGOUT_C - SDMA0_TRIGOUT_C clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_C_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK (0x20000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT (17U)
/*! SDMA0_TRIGOUT_D - SDMA0_TRIGOUT_D clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SDMA0_TRIGOUT_D_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK (0x40000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT (18U)
/*! SCT_DMA_REQ0 - SCT_DMA_REQ0 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ0_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK (0x80000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT (19U)
/*! SCT_DMA_REQ1 - SCT_DMA_REQ1 clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_SCT_DMA_REQ1_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK (0x100000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT (20U)
/*! HASHCRYPT_OUT - HASHCRYPT_OUTclear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_HASHCRYPT_OUT_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_MASK  (0x200000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_SHIFT (21U)
/*! ACMP - ACMP clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP(x)    (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ACMP_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK (0x400000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT (22U)
/*! FLEXSPI0_RX - FlexSPI0_RXclear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_RX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK (0x800000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT (23U)
/*! FLEXSPI0_TX - FlexSPI0_TX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI0_TX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_MASK   (0x1000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_SHIFT  (24U)
/*! ADC - ADC clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC(x)     (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_ADC_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK (0x2000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT (25U)
/*! FLEXSPI1_RX - FlexSPI1_RX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_RX_MASK)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK (0x4000000U)
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT (26U)
/*! FLEXSPI1_TX - FlexSPI1_TX clear
 *  0b0..No Effect
 *  0b1..Clears the ENA0 Bit
 */
#define INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC1_ITRIG_ENA0_CLR_FLEXSPI1_TX_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group INPUTMUX_Register_Masks */


/* INPUTMUX - Peripheral instance base addresses */
/** Peripheral INPUTMUX base address */
#define INPUTMUX_BASE                            (0x40026000u)
/** Peripheral INPUTMUX base pointer */
#define INPUTMUX                                 ((INPUTMUX_Type *)INPUTMUX_BASE)
/** Array initializer of INPUTMUX peripheral base addresses */
#define INPUTMUX_BASE_ADDRS                      { INPUTMUX_BASE }
/** Array initializer of INPUTMUX peripheral base pointers */
#define INPUTMUX_BASE_PTRS                       { INPUTMUX }

/*!
 * @}
 */ /* end of group INPUTMUX_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- IOPCTL Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL_Peripheral_Access_Layer IOPCTL Peripheral Access Layer
 * @{
 */

/** IOPCTL - Register Layout Typedef */
typedef struct {
  __IO uint32_t PIO[8][32];                        /**< IOPCTL configuration, array offset: 0x0, array step: index*0x80, index2*0x4 */
  __IO uint32_t FC15_I2C_SCL;                      /**< Flexcomm 15 SCL, offset: 0x400 */
  __IO uint32_t FC15_I2C_SDA;                      /**< Flexcomm 15 SDA, offset: 0x404 */
} IOPCTL_Type;

/* ----------------------------------------------------------------------------
   -- IOPCTL Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup IOPCTL_Register_Masks IOPCTL Register Masks
 * @{
 */

/*! @name PIO - IOPCTL configuration */
/*! @{ */
#define IOPCTL_PIO_FSEL_MASK                     (0xFU)
#define IOPCTL_PIO_FSEL_SHIFT                    (0U)
/*! FSEL - Function Selector (Digital Function)
 *  0b0000..Function 0
 *  0b0001..Function 1
 *  0b0010..Function 2
 *  0b0011..Function 3
 *  0b0100..Function 4
 *  0b0101..Function 5
 *  0b0110..Function 6
 *  0b0111..Function 7
 *  0b1000..Function 8
 *  0b1001..Function 9
 *  0b1010..Function 10
 *  0b1011..Function 11
 *  0b1100..Function 12
 *  0b1101..Function 13
 *  0b1110..Function 14
 *  0b1111..Function 15
 */
#define IOPCTL_PIO_FSEL(x)                       (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FSEL_SHIFT)) & IOPCTL_PIO_FSEL_MASK)
#define IOPCTL_PIO_PUPDENA_MASK                  (0x10U)
#define IOPCTL_PIO_PUPDENA_SHIFT                 (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define IOPCTL_PIO_PUPDENA(x)                    (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_PUPDENA_SHIFT)) & IOPCTL_PIO_PUPDENA_MASK)
#define IOPCTL_PIO_PUPDSEL_MASK                  (0x20U)
#define IOPCTL_PIO_PUPDSEL_SHIFT                 (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Pull-down
 *  0b1..Pull-up
 */
#define IOPCTL_PIO_PUPDSEL(x)                    (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_PUPDSEL_SHIFT)) & IOPCTL_PIO_PUPDSEL_MASK)
#define IOPCTL_PIO_IBENA_MASK                    (0x40U)
#define IOPCTL_PIO_IBENA_SHIFT                   (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Input buffer disabled
 *  0b1..Input buffer enabled
 */
#define IOPCTL_PIO_IBENA(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK)
#define IOPCTL_PIO_SLEWRATE_MASK                 (0x80U)
#define IOPCTL_PIO_SLEWRATE_SHIFT                (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Standard mode, output slew rate is not controlled.
 *  0b1..Slow mode, output slew rate control is enabled, limiting the output rate change and maximum toggle
 *       frequency. See device datasheet for details.
 */
#define IOPCTL_PIO_SLEWRATE(x)                   (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK)
#define IOPCTL_PIO_FULLDRIVE_MASK                (0x100U)
#define IOPCTL_PIO_FULLDRIVE_SHIFT               (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL_PIO_FULLDRIVE(x)                  (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK)
#define IOPCTL_PIO_AMENA_MASK                    (0x200U)
#define IOPCTL_PIO_AMENA_SHIFT                   (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Analog multiplexor disabled, required for digital pin function
 *  0b1..Analog multiplexor enabled, required for analog pin function
 */
#define IOPCTL_PIO_AMENA(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK)
#define IOPCTL_PIO_ODENA_MASK                    (0x400U)
#define IOPCTL_PIO_ODENA_SHIFT                   (10U)
/*! ODENA - Open-drain mode enable
 *  0b0..Normal push-pull output
 *  0b1..Simulated open-drain output (high drive disabled)
 */
#define IOPCTL_PIO_ODENA(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK)
#define IOPCTL_PIO_IIENA_MASK                    (0x800U)
#define IOPCTL_PIO_IIENA_SHIFT                   (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disabled, Input function is not inverted
 *  0b1..Enabled, Input is function inverted
 */
#define IOPCTL_PIO_IIENA(x)                      (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL_PIO_IIENA_MASK)
/*! @} */

/* The count of IOPCTL_PIO */
#define IOPCTL_PIO_COUNT                         (8U)

/* The count of IOPCTL_PIO */
#define IOPCTL_PIO_COUNT2                        (32U)

/*! @name FC15_I2C_SCL - Flexcomm 15 SCL */
/*! @{ */
#define IOPCTL_FC15_I2C_SCL_FSEL_MASK            (0xFU)
#define IOPCTL_FC15_I2C_SCL_FSEL_SHIFT           (0U)
/*! FSEL - Function Selector (Digital Function)
 *  0b0000..Function 0
 *  0b0001..Function 1
 *  0b0010..Function 2
 *  0b0011..Function 3
 *  0b0100..Function 4
 *  0b0101..Function 5
 *  0b0110..Function 6
 *  0b0111..Function 7
 *  0b1000..Function 8
 *  0b1001..Function 9
 *  0b1010..Function 10
 *  0b1011..Function 11
 *  0b1100..Function 12
 *  0b1101..Function 13
 *  0b1110..Function 14
 *  0b1111..Function 15
 */
#define IOPCTL_FC15_I2C_SCL_FSEL(x)              (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_FSEL_SHIFT)) & IOPCTL_FC15_I2C_SCL_FSEL_MASK)
#define IOPCTL_FC15_I2C_SCL_PUPDENA_MASK         (0x10U)
#define IOPCTL_FC15_I2C_SCL_PUPDENA_SHIFT        (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define IOPCTL_FC15_I2C_SCL_PUPDENA(x)           (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_PUPDENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_PUPDENA_MASK)
#define IOPCTL_FC15_I2C_SCL_PUPDSEL_MASK         (0x20U)
#define IOPCTL_FC15_I2C_SCL_PUPDSEL_SHIFT        (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Pull-down
 *  0b1..Pull-up
 */
#define IOPCTL_FC15_I2C_SCL_PUPDSEL(x)           (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_PUPDSEL_SHIFT)) & IOPCTL_FC15_I2C_SCL_PUPDSEL_MASK)
#define IOPCTL_FC15_I2C_SCL_IBENA_MASK           (0x40U)
#define IOPCTL_FC15_I2C_SCL_IBENA_SHIFT          (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Input buffer disabled
 *  0b1..Input buffer enabled
 */
#define IOPCTL_FC15_I2C_SCL_IBENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_IBENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_IBENA_MASK)
#define IOPCTL_FC15_I2C_SCL_SLEWRATE_MASK        (0x80U)
#define IOPCTL_FC15_I2C_SCL_SLEWRATE_SHIFT       (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Standard mode, output slew rate is not controlled.
 *  0b1..Slow mode, output slew rate control is enabled, limiting the output rate change and maximum toggle
 *       frequency. See device datasheet for details.
 */
#define IOPCTL_FC15_I2C_SCL_SLEWRATE(x)          (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_SLEWRATE_SHIFT)) & IOPCTL_FC15_I2C_SCL_SLEWRATE_MASK)
#define IOPCTL_FC15_I2C_SCL_FULLDRIVE_MASK       (0x100U)
#define IOPCTL_FC15_I2C_SCL_FULLDRIVE_SHIFT      (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL_FC15_I2C_SCL_FULLDRIVE(x)         (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_FULLDRIVE_SHIFT)) & IOPCTL_FC15_I2C_SCL_FULLDRIVE_MASK)
#define IOPCTL_FC15_I2C_SCL_AMENA_MASK           (0x200U)
#define IOPCTL_FC15_I2C_SCL_AMENA_SHIFT          (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Analog multiplexor disabled, required for digital pin function
 *  0b1..Analog multiplexor enabled, required for analog pin function
 */
#define IOPCTL_FC15_I2C_SCL_AMENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_AMENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_AMENA_MASK)
#define IOPCTL_FC15_I2C_SCL_ODENA_MASK           (0x400U)
#define IOPCTL_FC15_I2C_SCL_ODENA_SHIFT          (10U)
/*! ODENA - Open-drain mode enable
 *  0b0..Normal push-pull output
 *  0b1..Simulated open-drain output (high drive disabled)
 */
#define IOPCTL_FC15_I2C_SCL_ODENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_ODENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_ODENA_MASK)
#define IOPCTL_FC15_I2C_SCL_IIENA_MASK           (0x800U)
#define IOPCTL_FC15_I2C_SCL_IIENA_SHIFT          (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disabled, Input function is not inverted
 *  0b1..Enabled, Input is function inverted
 */
#define IOPCTL_FC15_I2C_SCL_IIENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SCL_IIENA_SHIFT)) & IOPCTL_FC15_I2C_SCL_IIENA_MASK)
/*! @} */

/*! @name FC15_I2C_SDA - Flexcomm 15 SDA */
/*! @{ */
#define IOPCTL_FC15_I2C_SDA_FSEL_MASK            (0xFU)
#define IOPCTL_FC15_I2C_SDA_FSEL_SHIFT           (0U)
/*! FSEL - Function Selector (Digital Function)
 *  0b0000..Function 0
 *  0b0001..Function 1
 *  0b0010..Function 2
 *  0b0011..Function 3
 *  0b0100..Function 4
 *  0b0101..Function 5
 *  0b0110..Function 6
 *  0b0111..Function 7
 *  0b1000..Function 8
 *  0b1001..Function 9
 *  0b1010..Function 10
 *  0b1011..Function 11
 *  0b1100..Function 12
 *  0b1101..Function 13
 *  0b1110..Function 14
 *  0b1111..Function 15
 */
#define IOPCTL_FC15_I2C_SDA_FSEL(x)              (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_FSEL_SHIFT)) & IOPCTL_FC15_I2C_SDA_FSEL_MASK)
#define IOPCTL_FC15_I2C_SDA_PUPDENA_MASK         (0x10U)
#define IOPCTL_FC15_I2C_SDA_PUPDENA_SHIFT        (4U)
/*! PUPDENA - Pullup / Pulldown Enable
 *  0b0..Disable
 *  0b1..Enable
 */
#define IOPCTL_FC15_I2C_SDA_PUPDENA(x)           (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_PUPDENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_PUPDENA_MASK)
#define IOPCTL_FC15_I2C_SDA_PUPDSEL_MASK         (0x20U)
#define IOPCTL_FC15_I2C_SDA_PUPDSEL_SHIFT        (5U)
/*! PUPDSEL - Pullup or Pulldown Selector
 *  0b0..Pull-down
 *  0b1..Pull-up
 */
#define IOPCTL_FC15_I2C_SDA_PUPDSEL(x)           (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_PUPDSEL_SHIFT)) & IOPCTL_FC15_I2C_SDA_PUPDSEL_MASK)
#define IOPCTL_FC15_I2C_SDA_IBENA_MASK           (0x40U)
#define IOPCTL_FC15_I2C_SDA_IBENA_SHIFT          (6U)
/*! IBENA - Input Buffer Enable
 *  0b0..Input buffer disabled
 *  0b1..Input buffer enabled
 */
#define IOPCTL_FC15_I2C_SDA_IBENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_IBENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_IBENA_MASK)
#define IOPCTL_FC15_I2C_SDA_SLEWRATE_MASK        (0x80U)
#define IOPCTL_FC15_I2C_SDA_SLEWRATE_SHIFT       (7U)
/*! SLEWRATE - Slew Rate Control
 *  0b0..Standard mode, output slew rate is not controlled.
 *  0b1..Slow mode, output slew rate control is enabled, limiting the output rate change and maximum toggle
 *       frequency. See device datasheet for details.
 */
#define IOPCTL_FC15_I2C_SDA_SLEWRATE(x)          (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_SLEWRATE_SHIFT)) & IOPCTL_FC15_I2C_SDA_SLEWRATE_MASK)
#define IOPCTL_FC15_I2C_SDA_FULLDRIVE_MASK       (0x100U)
#define IOPCTL_FC15_I2C_SDA_FULLDRIVE_SHIFT      (8U)
/*! FULLDRIVE - Drive Selector
 *  0b0..Normal output drive
 *  0b1..Full output drive, twice the drive of normal mode.
 */
#define IOPCTL_FC15_I2C_SDA_FULLDRIVE(x)         (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_FULLDRIVE_SHIFT)) & IOPCTL_FC15_I2C_SDA_FULLDRIVE_MASK)
#define IOPCTL_FC15_I2C_SDA_AMENA_MASK           (0x200U)
#define IOPCTL_FC15_I2C_SDA_AMENA_SHIFT          (9U)
/*! AMENA - Analog Mux Enable
 *  0b0..Analog multiplexor disabled, required for digital pin function
 *  0b1..Analog multiplexor enabled, required for analog pin function
 */
#define IOPCTL_FC15_I2C_SDA_AMENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_AMENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_AMENA_MASK)
#define IOPCTL_FC15_I2C_SDA_ODENA_MASK           (0x400U)
#define IOPCTL_FC15_I2C_SDA_ODENA_SHIFT          (10U)
/*! ODENA - Open-drain mode enable
 *  0b0..Normal push-pull output
 *  0b1..Simulated open-drain output (high drive disabled)
 */
#define IOPCTL_FC15_I2C_SDA_ODENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_ODENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_ODENA_MASK)
#define IOPCTL_FC15_I2C_SDA_IIENA_MASK           (0x800U)
#define IOPCTL_FC15_I2C_SDA_IIENA_SHIFT          (11U)
/*! IIENA - Input Invert Enable
 *  0b0..Disabled, Input function is not inverted
 *  0b1..Enabled, Input is function inverted
 */
#define IOPCTL_FC15_I2C_SDA_IIENA(x)             (((uint32_t)(((uint32_t)(x)) << IOPCTL_FC15_I2C_SDA_IIENA_SHIFT)) & IOPCTL_FC15_I2C_SDA_IIENA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group IOPCTL_Register_Masks */


/* IOPCTL - Peripheral instance base addresses */
/** Peripheral IOPCTL base address */
#define IOPCTL_BASE                              (0x40004000u)
/** Peripheral IOPCTL base pointer */
#define IOPCTL                                   ((IOPCTL_Type *)IOPCTL_BASE)
/** Array initializer of IOPCTL peripheral base addresses */
#define IOPCTL_BASE_ADDRS                        { IOPCTL_BASE }
/** Array initializer of IOPCTL peripheral base pointers */
#define IOPCTL_BASE_PTRS                         { IOPCTL }

/*!
 * @}
 */ /* end of group IOPCTL_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- LCDIF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
 * @{
 */

/** LCDIF - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[4672];
  __IO uint32_t FRAMEBUFFERCONFIG0;                /**< Frame Buffer and Timing control, offset: 0x1240 */
       uint8_t RESERVED_1[28];
  __IO uint32_t FRAMEBUFFERADDRESS0;               /**< Starting address of the frame buffer, offset: 0x1260 */
       uint8_t RESERVED_2[28];
  __IO uint32_t FRAMEBUFFERSTRIDE0;                /**< Stride of the frame buffer in bytes, offset: 0x1280 */
       uint8_t RESERVED_3[28];
  __IO uint32_t FRAMEBUFFERORIGIN0;                /**< Pixel origin inside the frame buffer for the top-left panel pixel, offset: 0x12A0 */
       uint8_t RESERVED_4[188];
  __IO uint32_t DISPLAYDITHERCONFIG0;              /**< Configuration register for dithering, offset: 0x1360 */
       uint8_t RESERVED_5[28];
  __IO uint32_t DISPLAYDITHERTABLELOW0;            /**< Dither table low, offset: 0x1380 */
       uint8_t RESERVED_6[28];
  __IO uint32_t DISPLAYDITHERTABLEHIGH0;           /**< Dither table high, offset: 0x13A0 */
       uint8_t RESERVED_7[28];
  __IO uint32_t PANELCONFIG0;                      /**< Panel configuration, offset: 0x13C0 */
       uint8_t RESERVED_8[28];
  __IO uint32_t PANELTIMING0;                      /**< Timing for hardware panel sequencing, offset: 0x13E0 */
       uint8_t RESERVED_9[28];
  __IO uint32_t HDISPLAY0;                         /**< Horizontal Total and Display End counters, offset: 0x1400 */
       uint8_t RESERVED_10[28];
  __IO uint32_t HSYNC0;                            /**< Horizontal Sync counters, offset: 0x1420 */
       uint8_t RESERVED_11[28];
  __IO uint32_t HCOUNTER10;                        /**< Horizontal Programmable Counter 1, offset: 0x1440 */
       uint8_t RESERVED_12[28];
  __IO uint32_t HCOUNTER20;                        /**< Horizontal Programmable Counter 2, offset: 0x1460 */
       uint8_t RESERVED_13[28];
  __IO uint32_t VDISPLAY0;                         /**< Vertical Total and Display End counters, offset: 0x1480 */
       uint8_t RESERVED_14[28];
  __IO uint32_t VSYNC0;                            /**< Vertical Sync counters, offset: 0x14A0 */
       uint8_t RESERVED_15[28];
  __I  uint32_t DISPLAYCURRENTLOCATION0;           /**< Current x,y location of display controller, offset: 0x14C0 */
       uint8_t RESERVED_16[28];
  __IO uint32_t GAMMAINDEX0;                       /**< Index into gamma table, offset: 0x14E0 */
       uint8_t RESERVED_17[28];
  __IO uint32_t GAMMADATA0;                        /**< Translation values for the gamma table, offset: 0x1500 */
       uint8_t RESERVED_18[28];
  __IO uint32_t CURSORCONFIG;                      /**< Configuration register for the cursor, offset: 0x1520 */
       uint8_t RESERVED_19[12];
  __IO uint32_t CURSORADDRESS;                     /**< Address of the cursor shape, offset: 0x1530 */
       uint8_t RESERVED_20[12];
  __IO uint32_t CURSORLOCATION;                    /**< Location of the cursor on the owning display, offset: 0x1540 */
       uint8_t RESERVED_21[12];
  __IO uint32_t CURSORBACKGROUND;                  /**< The background color for Masked cursors, offset: 0x1550 */
       uint8_t RESERVED_22[12];
  __IO uint32_t CURSORFOREGROUND;                  /**< The foreground color for Masked cursors, offset: 0x1560 */
       uint8_t RESERVED_23[156];
  __IO uint32_t DISPLAYINTR;                       /**< Display interrupt register, offset: 0x1600 */
       uint8_t RESERVED_24[12];
  __IO uint32_t DISPLAYINTRENABLE;                 /**< The interrupt enable register for display_0 (and display_1 if present), offset: 0x1610 */
       uint8_t RESERVED_25[12];
  __IO uint32_t DBICONFIG0;                        /**< Configuration register for DBI output, offset: 0x1620 */
       uint8_t RESERVED_26[28];
  __O  uint32_t DBIIFRESET0;                       /**< Reset DBI interface to idle state, offset: 0x1640 */
       uint8_t RESERVED_27[28];
  __IO uint32_t DBIWRCHAR10;                       /**< DBI write AC characteristics definition register 1, offset: 0x1660 */
       uint8_t RESERVED_28[28];
  __IO uint32_t DBIWRCHAR20;                       /**< DBI write AC characteristics definition register 2, offset: 0x1680 */
       uint8_t RESERVED_29[28];
  __O  uint32_t DBICMD0;                           /**< DBI Command in/out port, offset: 0x16A0 */
       uint8_t RESERVED_30[28];
  __IO uint32_t DPICONFIG0;                        /**< The configuration register for DPI output, offset: 0x16C0 */
       uint8_t RESERVED_31[44];
  __I  uint32_t DCCHIPREV;                         /**< Revision for the chip in BCD, offset: 0x16F0 */
       uint8_t RESERVED_32[12];
  __I  uint32_t DCCHIPDATE;                        /**< Shows the release date for the IP in YYYYMMDD (year, month), offset: 0x1700 */
       uint8_t RESERVED_33[28];
  __I  uint32_t DCCHIPPATCHREV;                    /**< Patch revision, offset: 0x1720 */
       uint8_t RESERVED_34[28];
  __IO uint32_t DCTILEINCFG0;                      /**< Tile input configuration, offset: 0x1740 */
       uint8_t RESERVED_35[28];
  __IO uint32_t DCTILEUVFRAMEBUFFERADR0;           /**< UV frame buffer address when tile input, offset: 0x1760 */
       uint8_t RESERVED_36[28];
  __IO uint32_t DCTILEUVFRAMEBUFFERSTR0;           /**< UV frame buffer stride when tile input, offset: 0x1780 */
       uint8_t RESERVED_37[44];
  __I  uint32_t DCPRODUCTID;                       /**< Product ID, offset: 0x17B0 */
       uint8_t RESERVED_38[44];
  __IO uint32_t DBITYPECCFG0;                      /**< DBI Type C write timing definition., offset: 0x17E0 */
       uint8_t RESERVED_39[28];
  __IO uint32_t DCSTATUS0;                         /**< , offset: 0x1800 */
       uint8_t RESERVED_40[28];
  __IO uint32_t DEBUGCOUNTERSELECT0;               /**< , offset: 0x1820 */
       uint8_t RESERVED_41[28];
  __IO uint32_t DEBUGCOUNTERVALUE0;                /**< Debug Counter Value as specified in DebugCounterSelect, offset: 0x1840 */
} LCDIF_Type;

/* ----------------------------------------------------------------------------
   -- LCDIF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
 * @{
 */

/*! @name FRAMEBUFFERCONFIG0 - Frame Buffer and Timing control */
/*! @{ */
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK     (0x7U)
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT    (0U)
/*! FORMAT - The format of the frame buffer.
 */
#define LCDIF_FRAMEBUFFERCONFIG0_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FORMAT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FORMAT_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_MODE_MASK       (0x10U)
#define LCDIF_FRAMEBUFFERCONFIG0_MODE_SHIFT      (4U)
/*! MODE - Mode of the frame buffer.
 *  0b0..LINEAR
 *  0b1..TILE4x4 INPUT
 */
#define LCDIF_FRAMEBUFFERCONFIG0_MODE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_MODE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_MODE_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_MASK     (0x100U)
#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_SHIFT    (8U)
/*! OUTPUT - When Output is enabled, pixels will be displayed. When Output is disabled, all pixels
 *    will be black. This allows a panel to have correct timing but without any pixels.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_FRAMEBUFFERCONFIG0_OUTPUT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_OUTPUT_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_MASK (0x200U)
#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_SHIFT (9U)
/*! SWITCHPANEL - When SwitchPanel of panel 0 is enabled, output channel 0 will show the image of
 *    panel 1,not panel 0's. When SwitchPanel of panel 0 is disabeld,output channel 0 will show its
 *    original image which is from panel 0. When SwitchPanel of panel 1 is enabled, output channel 1
 *    will show the image of panel 0,not panel 1's. When SwitchPanle of panel 1 is disabled,output
 *    channel 1 will show the original image which is from panel 1. disabled(normal) enabled(switch)
 *    output channel 0 panel 0 panel 1 output channel 1 panel 1 panel 0.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_SWITCHPANEL_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA_MASK      (0x1000U)
#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA_SHIFT     (12U)
/*! GAMMA
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_FRAMEBUFFERCONFIG0_GAMMA(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_GAMMA_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_GAMMA_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_VALID_MASK      (0x10000U)
#define LCDIF_FRAMEBUFFERCONFIG0_VALID_SHIFT     (16U)
#define LCDIF_FRAMEBUFFERCONFIG0_VALID(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_VALID_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_VALID_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_RESET_MASK      (0x100000U)
#define LCDIF_FRAMEBUFFERCONFIG0_RESET_SHIFT     (20U)
/*! RESET
 *  0b0..For DBI, this field should be = 0.
 *  0b1..Enable DPI Timing, start a DPI transfer.
 */
#define LCDIF_FRAMEBUFFERCONFIG0_RESET(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_RESET_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_RESET_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_MASK  (0x1000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_SHIFT (24U)
#define LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_UNDERFLOW_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_MASK (0x10000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_SHIFT (28U)
#define LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_FLIP_IN_PROGRESS_MASK)
#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_MASK (0x20000000U)
#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_SHIFT (29U)
/*! BACK_PRESSURE_DISABLE - 0=NO; 1=YES;
 */
#define LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_SHIFT)) & LCDIF_FRAMEBUFFERCONFIG0_BACK_PRESSURE_DISABLE_MASK)
/*! @} */

/*! @name FRAMEBUFFERADDRESS0 - Starting address of the frame buffer */
/*! @{ */
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK   (0x7FFFFFFFU)
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT  (0U)
/*! ADDRESS - ADDRESS
 */
#define LCDIF_FRAMEBUFFERADDRESS0_ADDRESS(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_ADDRESS_MASK)
#define LCDIF_FRAMEBUFFERADDRESS0_TYPE_MASK      (0x80000000U)
#define LCDIF_FRAMEBUFFERADDRESS0_TYPE_SHIFT     (31U)
/*! TYPE - 0=SYSTEM; 1=VIRTUAL_SYSTEM;
 */
#define LCDIF_FRAMEBUFFERADDRESS0_TYPE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERADDRESS0_TYPE_SHIFT)) & LCDIF_FRAMEBUFFERADDRESS0_TYPE_MASK)
/*! @} */

/*! @name FRAMEBUFFERSTRIDE0 - Stride of the frame buffer in bytes */
/*! @{ */
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK     (0x1FFFFU)
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT    (0U)
/*! STRIDE - Number of bytes from start of one line to next line. This value needs to be 128 byte aligned.
 */
#define LCDIF_FRAMEBUFFERSTRIDE0_STRIDE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_SHIFT)) & LCDIF_FRAMEBUFFERSTRIDE0_STRIDE_MASK)
/*! @} */

/*! @name FRAMEBUFFERORIGIN0 - Pixel origin inside the frame buffer for the top-left panel pixel */
/*! @{ */
#define LCDIF_FRAMEBUFFERORIGIN0_X_MASK          (0x7FFU)
#define LCDIF_FRAMEBUFFERORIGIN0_X_SHIFT         (0U)
/*! X - X origin of frame buffer for panning.
 */
#define LCDIF_FRAMEBUFFERORIGIN0_X(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERORIGIN0_X_SHIFT)) & LCDIF_FRAMEBUFFERORIGIN0_X_MASK)
#define LCDIF_FRAMEBUFFERORIGIN0_Y_MASK          (0x7FF0000U)
#define LCDIF_FRAMEBUFFERORIGIN0_Y_SHIFT         (16U)
/*! Y - Y origin of frame buffer for panning.
 */
#define LCDIF_FRAMEBUFFERORIGIN0_Y(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_FRAMEBUFFERORIGIN0_Y_SHIFT)) & LCDIF_FRAMEBUFFERORIGIN0_Y_MASK)
/*! @} */

/*! @name DISPLAYDITHERCONFIG0 - Configuration register for dithering */
/*! @{ */
#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_MASK (0xFU)
#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_SHIFT (0U)
/*! BLUE_SIZE - Number of important bits for the blue channel for the panel. Start counting from MSB.
 */
#define LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_BLUE_SIZE_MASK)
#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_MASK (0xF00U)
#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_SHIFT (8U)
/*! GREEN_SIZE - Number of important bits for the green channel for the panel. Start counting from MSB.
 */
#define LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_GREEN_SIZE_MASK)
#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_MASK (0xF0000U)
#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_SHIFT (16U)
/*! RED_SIZE - Number of important bits for the red channel for the panel. Start counting from MSB.
 */
#define LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_RED_SIZE_MASK)
#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE_MASK   (0x80000000U)
#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE_SHIFT  (31U)
/*! ENABLE - Enabling dithering allows R8G8B8 modes to show better on panels with less bits-per-pixel.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_DISPLAYDITHERCONFIG0_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERCONFIG0_ENABLE_SHIFT)) & LCDIF_DISPLAYDITHERCONFIG0_ENABLE_MASK)
/*! @} */

/*! @name DISPLAYDITHERTABLELOW0 - Dither table low */
/*! @{ */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK  (0xFU)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT (0U)
/*! Y0_X0 - Dither threshold value for x,y=0,0.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X0_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK  (0xF0U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT (4U)
/*! Y0_X1 - Dither threshold value for x,y=1,0.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X1_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK  (0xF00U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT (8U)
/*! Y0_X2 - Dither threshold value for x,y=2,0.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X2_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK  (0xF000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT (12U)
/*! Y0_X3 - Dither threshold value for x,y=3,0.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y0_X3_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK  (0xF0000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT (16U)
/*! Y1_X0 - Dither threshold value for x,y=0,1.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X0_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK  (0xF00000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT (20U)
/*! Y1_X1 - Dither threshold value for x,y=1,1.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X1_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK  (0xF000000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT (24U)
/*! Y1_X2 - Dither threshold value for x,y=2,1.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X2_MASK)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK  (0xF0000000U)
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT (28U)
/*! Y1_X3 - Dither threshold value for x,y=3,1.
 */
#define LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLELOW0_Y1_X3_MASK)
/*! @} */

/*! @name DISPLAYDITHERTABLEHIGH0 - Dither table high */
/*! @{ */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK (0xFU)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT (0U)
/*! Y2_X0 - Dither threshold value for x,y=0,2.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X0_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK (0xF0U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT (4U)
/*! Y2_X1 - Dither threshold value for x,y=1,2.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X1_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK (0xF00U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT (8U)
/*! Y2_X2 - Dither threshold value for x,y=2,2.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X2_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK (0xF000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT (12U)
/*! Y2_X3 - Dither threshold value for x,y=3,2.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y2_X3_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK (0xF0000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT (16U)
/*! Y3_X0 - Dither threshold value for x,y=0,3.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X0_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK (0xF00000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT (20U)
/*! Y3_X1 - Dither threshold value for x,y=1,3.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X1_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK (0xF000000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT (24U)
/*! Y3_X2 - Dither threshold value for x,y=2,3.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X2_MASK)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK (0xF0000000U)
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT (28U)
/*! Y3_X3 - Dither threshold value for x,y=3,3.
 */
#define LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_SHIFT)) & LCDIF_DISPLAYDITHERTABLEHIGH0_Y3_X3_MASK)
/*! @} */

/*! @name PANELCONFIG0 - Panel configuration */
/*! @{ */
#define LCDIF_PANELCONFIG0_DE_MASK               (0x1U)
#define LCDIF_PANELCONFIG0_DE_SHIFT              (0U)
/*! DE - Data Enable enabled/disabled.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_PANELCONFIG0_DE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_SHIFT)) & LCDIF_PANELCONFIG0_DE_MASK)
#define LCDIF_PANELCONFIG0_DE_POLARITY_MASK      (0x2U)
#define LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT     (1U)
/*! DE_POLARITY - Data Enable polarity.
 *  0b0..POSITIVE
 *  0b1..NEGATIVE
 */
#define LCDIF_PANELCONFIG0_DE_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DE_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DE_POLARITY_MASK)
#define LCDIF_PANELCONFIG0_DATA_ENABLE_MASK      (0x10U)
#define LCDIF_PANELCONFIG0_DATA_ENABLE_SHIFT     (4U)
/*! DATA_ENABLE - Data enabled/disabled.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_PANELCONFIG0_DATA_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DATA_ENABLE_SHIFT)) & LCDIF_PANELCONFIG0_DATA_ENABLE_MASK)
#define LCDIF_PANELCONFIG0_DATA_POLARITY_MASK    (0x20U)
#define LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT   (5U)
/*! DATA_POLARITY - Data polarity.
 *  0b0..POSITIVE
 *  0b1..NEGATIVE
 */
#define LCDIF_PANELCONFIG0_DATA_POLARITY(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_DATA_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_DATA_POLARITY_MASK)
#define LCDIF_PANELCONFIG0_CLOCK_MASK            (0x100U)
#define LCDIF_PANELCONFIG0_CLOCK_SHIFT           (8U)
/*! CLOCK - Clock enable/disable.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_PANELCONFIG0_CLOCK(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_MASK)
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK   (0x200U)
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT  (9U)
/*! CLOCK_POLARITY - Clock polarity.
 *  0b0..POSITIVE
 *  0b1..NEGATIVE
 */
#define LCDIF_PANELCONFIG0_CLOCK_POLARITY(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_CLOCK_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_CLOCK_POLARITY_MASK)
#define LCDIF_PANELCONFIG0_POWER_MASK            (0x1000U)
#define LCDIF_PANELCONFIG0_POWER_SHIFT           (12U)
/*! POWER - Power enable/disable.
 */
#define LCDIF_PANELCONFIG0_POWER(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_POWER_SHIFT)) & LCDIF_PANELCONFIG0_POWER_MASK)
#define LCDIF_PANELCONFIG0_POWER_POLARITY_MASK   (0x2000U)
#define LCDIF_PANELCONFIG0_POWER_POLARITY_SHIFT  (13U)
/*! POWER_POLARITY - Power polarity.
 */
#define LCDIF_PANELCONFIG0_POWER_POLARITY(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_POWER_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_POWER_POLARITY_MASK)
#define LCDIF_PANELCONFIG0_BACKLIGHT_MASK        (0x10000U)
#define LCDIF_PANELCONFIG0_BACKLIGHT_SHIFT       (16U)
/*! BACKLIGHT - Backlight enabled/disbaled.
 */
#define LCDIF_PANELCONFIG0_BACKLIGHT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_BACKLIGHT_SHIFT)) & LCDIF_PANELCONFIG0_BACKLIGHT_MASK)
#define LCDIF_PANELCONFIG0_BACKLIGHT_POLARITY_MASK (0x20000U)
#define LCDIF_PANELCONFIG0_BACKLIGHT_POLARITY_SHIFT (17U)
/*! BACKLIGHT_POLARITY - Backlight polarity.
 */
#define LCDIF_PANELCONFIG0_BACKLIGHT_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_BACKLIGHT_POLARITY_SHIFT)) & LCDIF_PANELCONFIG0_BACKLIGHT_POLARITY_MASK)
#define LCDIF_PANELCONFIG0_SEQUENCING_MASK       (0x80000000U)
#define LCDIF_PANELCONFIG0_SEQUENCING_SHIFT      (31U)
/*! SEQUENCING - Enable software or hardware panel sequencing.
 *  0b0..HARDWARE
 *  0b1..SOFTWARE
 */
#define LCDIF_PANELCONFIG0_SEQUENCING(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELCONFIG0_SEQUENCING_SHIFT)) & LCDIF_PANELCONFIG0_SEQUENCING_MASK)
/*! @} */

/*! @name PANELTIMING0 - Timing for hardware panel sequencing */
/*! @{ */
#define LCDIF_PANELTIMING0_POWER_ENABLE_MASK     (0xFU)
#define LCDIF_PANELTIMING0_POWER_ENABLE_SHIFT    (0U)
/*! POWER_ENABLE - Number of VSYNCsto wait after power has been enabled.
 */
#define LCDIF_PANELTIMING0_POWER_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_POWER_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_POWER_ENABLE_MASK)
#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_MASK (0xF0U)
#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_SHIFT (4U)
/*! BACKLIGHT_ENABLE - Number of VSYNCs to wait after backlight has been enabled.
 */
#define LCDIF_PANELTIMING0_BACKLIGHT_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_BACKLIGHT_ENABLE_MASK)
#define LCDIF_PANELTIMING0_CLOCK_ENABLE_MASK     (0xF00U)
#define LCDIF_PANELTIMING0_CLOCK_ENABLE_SHIFT    (8U)
/*! CLOCK_ENABLE - Number of VSYNCs to wait after clock has been enabled.
 */
#define LCDIF_PANELTIMING0_CLOCK_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_CLOCK_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_CLOCK_ENABLE_MASK)
#define LCDIF_PANELTIMING0_DATA_ENABLE_MASK      (0xF000U)
#define LCDIF_PANELTIMING0_DATA_ENABLE_SHIFT     (12U)
/*! DATA_ENABLE - Number of VSYNCs to wait after data has been enabled.
 */
#define LCDIF_PANELTIMING0_DATA_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_DATA_ENABLE_SHIFT)) & LCDIF_PANELTIMING0_DATA_ENABLE_MASK)
#define LCDIF_PANELTIMING0_DATA_DISABLE_MASK     (0xF0000U)
#define LCDIF_PANELTIMING0_DATA_DISABLE_SHIFT    (16U)
/*! DATA_DISABLE - Number of VSYNCs to wait after data has been disabled.
 */
#define LCDIF_PANELTIMING0_DATA_DISABLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_DATA_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_DATA_DISABLE_MASK)
#define LCDIF_PANELTIMING0_CLOCK_DISABLE_MASK    (0xF00000U)
#define LCDIF_PANELTIMING0_CLOCK_DISABLE_SHIFT   (20U)
/*! CLOCK_DISABLE - Number of VSYNCs to wait after clock has been disabled.
 */
#define LCDIF_PANELTIMING0_CLOCK_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_CLOCK_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_CLOCK_DISABLE_MASK)
#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_MASK (0xF000000U)
#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_SHIFT (24U)
/*! BACKLIGHT_DISABLE - Number of VSYNCs to wait after backlight has been disabled.
 */
#define LCDIF_PANELTIMING0_BACKLIGHT_DISABLE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_BACKLIGHT_DISABLE_MASK)
#define LCDIF_PANELTIMING0_POWER_DISABLE_MASK    (0xF0000000U)
#define LCDIF_PANELTIMING0_POWER_DISABLE_SHIFT   (28U)
/*! POWER_DISABLE - Number of VSYNCs to wait after power has been disabled.
 */
#define LCDIF_PANELTIMING0_POWER_DISABLE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PANELTIMING0_POWER_DISABLE_SHIFT)) & LCDIF_PANELTIMING0_POWER_DISABLE_MASK)
/*! @} */

/*! @name HDISPLAY0 - Horizontal Total and Display End counters */
/*! @{ */
#define LCDIF_HDISPLAY0_DISPLAY_END_MASK         (0x1FFFU)
#define LCDIF_HDISPLAY0_DISPLAY_END_SHIFT        (0U)
/*! DISPLAY_END - Number of visible horizontal pixels.
 */
#define LCDIF_HDISPLAY0_DISPLAY_END(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_HDISPLAY0_DISPLAY_END_MASK)
#define LCDIF_HDISPLAY0_TOTAL_MASK               (0x1FFF0000U)
#define LCDIF_HDISPLAY0_TOTAL_SHIFT              (16U)
/*! TOTAL - Total number of horizontal pixels.
 */
#define LCDIF_HDISPLAY0_TOTAL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_HDISPLAY0_TOTAL_SHIFT)) & LCDIF_HDISPLAY0_TOTAL_MASK)
/*! @} */

/*! @name HSYNC0 - Horizontal Sync counters */
/*! @{ */
#define LCDIF_HSYNC0_START_MASK                  (0x1FFFU)
#define LCDIF_HSYNC0_START_SHIFT                 (0U)
/*! START - Start of horizontal sync pulse.
 */
#define LCDIF_HSYNC0_START(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_START_SHIFT)) & LCDIF_HSYNC0_START_MASK)
#define LCDIF_HSYNC0_END_MASK                    (0x1FFF0000U)
#define LCDIF_HSYNC0_END_SHIFT                   (16U)
/*! END - End of horizontal sync pulse.
 */
#define LCDIF_HSYNC0_END(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_END_SHIFT)) & LCDIF_HSYNC0_END_MASK)
#define LCDIF_HSYNC0_PULSE_MASK                  (0x40000000U)
#define LCDIF_HSYNC0_PULSE_SHIFT                 (30U)
/*! PULSE - Horizontal sync pulse control.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_HSYNC0_PULSE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_PULSE_SHIFT)) & LCDIF_HSYNC0_PULSE_MASK)
#define LCDIF_HSYNC0_POLARITY_MASK               (0x80000000U)
#define LCDIF_HSYNC0_POLARITY_SHIFT              (31U)
/*! POLARITY - Polarity of the horizontal sync pulse
 *  0b0..POSITIVE
 *  0b1..NEGATIVE
 */
#define LCDIF_HSYNC0_POLARITY(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYNC0_POLARITY_SHIFT)) & LCDIF_HSYNC0_POLARITY_MASK)
/*! @} */

/*! @name HCOUNTER10 - Horizontal Programmable Counter 1 */
/*! @{ */
#define LCDIF_HCOUNTER10_START_MASK              (0xFFFU)
#define LCDIF_HCOUNTER10_START_SHIFT             (0U)
/*! START - Start of horizontal counter 1.
 */
#define LCDIF_HCOUNTER10_START(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER10_START_SHIFT)) & LCDIF_HCOUNTER10_START_MASK)
#define LCDIF_HCOUNTER10_END_MASK                (0xFFF0000U)
#define LCDIF_HCOUNTER10_END_SHIFT               (16U)
/*! END - End of horizontal counter 1.
 */
#define LCDIF_HCOUNTER10_END(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER10_END_SHIFT)) & LCDIF_HCOUNTER10_END_MASK)
#define LCDIF_HCOUNTER10_PULSE_MASK              (0x40000000U)
#define LCDIF_HCOUNTER10_PULSE_SHIFT             (30U)
/*! PULSE - Horizontal counter 1 control.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_HCOUNTER10_PULSE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER10_PULSE_SHIFT)) & LCDIF_HCOUNTER10_PULSE_MASK)
#define LCDIF_HCOUNTER10_POLARITY_MASK           (0x80000000U)
#define LCDIF_HCOUNTER10_POLARITY_SHIFT          (31U)
/*! POLARITY - Polarity of the pulse.
 *  0b0..POSITIVE
 *  0b1..ACTIVE-LOW
 */
#define LCDIF_HCOUNTER10_POLARITY(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER10_POLARITY_SHIFT)) & LCDIF_HCOUNTER10_POLARITY_MASK)
/*! @} */

/*! @name HCOUNTER20 - Horizontal Programmable Counter 2 */
/*! @{ */
#define LCDIF_HCOUNTER20_END_MASK                (0xFFF0000U)
#define LCDIF_HCOUNTER20_END_SHIFT               (16U)
/*! END - End of horizontal counter 2.
 */
#define LCDIF_HCOUNTER20_END(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER20_END_SHIFT)) & LCDIF_HCOUNTER20_END_MASK)
#define LCDIF_HCOUNTER20_PULSE_MASK              (0x40000000U)
#define LCDIF_HCOUNTER20_PULSE_SHIFT             (30U)
/*! PULSE - Horizontal counter 2 control.
 */
#define LCDIF_HCOUNTER20_PULSE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER20_PULSE_SHIFT)) & LCDIF_HCOUNTER20_PULSE_MASK)
#define LCDIF_HCOUNTER20_POLARITY_MASK           (0x80000000U)
#define LCDIF_HCOUNTER20_POLARITY_SHIFT          (31U)
/*! POLARITY - Polarity of the pulse.
 */
#define LCDIF_HCOUNTER20_POLARITY(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_HCOUNTER20_POLARITY_SHIFT)) & LCDIF_HCOUNTER20_POLARITY_MASK)
/*! @} */

/*! @name VDISPLAY0 - Vertical Total and Display End counters */
/*! @{ */
#define LCDIF_VDISPLAY0_DISPLAY_END_MASK         (0xFFFU)
#define LCDIF_VDISPLAY0_DISPLAY_END_SHIFT        (0U)
/*! DISPLAY_END - Number of visible vertical lines.
 */
#define LCDIF_VDISPLAY0_DISPLAY_END(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_DISPLAY_END_SHIFT)) & LCDIF_VDISPLAY0_DISPLAY_END_MASK)
#define LCDIF_VDISPLAY0_TOTAL_MASK               (0xFFF0000U)
#define LCDIF_VDISPLAY0_TOTAL_SHIFT              (16U)
/*! TOTAL - Total number of vertical lines.
 */
#define LCDIF_VDISPLAY0_TOTAL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDISPLAY0_TOTAL_SHIFT)) & LCDIF_VDISPLAY0_TOTAL_MASK)
/*! @} */

/*! @name VSYNC0 - Vertical Sync counters */
/*! @{ */
#define LCDIF_VSYNC0_START_MASK                  (0xFFFU)
#define LCDIF_VSYNC0_START_SHIFT                 (0U)
/*! START - Start of the vertical sync pulse.
 */
#define LCDIF_VSYNC0_START(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_START_SHIFT)) & LCDIF_VSYNC0_START_MASK)
#define LCDIF_VSYNC0_END_MASK                    (0xFFF0000U)
#define LCDIF_VSYNC0_END_SHIFT                   (16U)
/*! END - End of the vertical sync pulse.
 */
#define LCDIF_VSYNC0_END(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_END_SHIFT)) & LCDIF_VSYNC0_END_MASK)
#define LCDIF_VSYNC0_PULSE_MASK                  (0x40000000U)
#define LCDIF_VSYNC0_PULSE_SHIFT                 (30U)
/*! PULSE - Vertical sync pulse control.
 *  0b0..DISABLED
 *  0b1..ENABLED
 */
#define LCDIF_VSYNC0_PULSE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_PULSE_SHIFT)) & LCDIF_VSYNC0_PULSE_MASK)
#define LCDIF_VSYNC0_POLARITY_MASK               (0x80000000U)
#define LCDIF_VSYNC0_POLARITY_SHIFT              (31U)
/*! POLARITY - Polarity of the vertical sync pulse.
 *  0b0..POSITIVE
 *  0b1..ACTIVE-LOW
 */
#define LCDIF_VSYNC0_POLARITY(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYNC0_POLARITY_SHIFT)) & LCDIF_VSYNC0_POLARITY_MASK)
/*! @} */

/*! @name DISPLAYCURRENTLOCATION0 - Current x,y location of display controller */
/*! @{ */
#define LCDIF_DISPLAYCURRENTLOCATION0_X_MASK     (0xFFFFU)
#define LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT    (0U)
/*! X - Current X location.
 */
#define LCDIF_DISPLAYCURRENTLOCATION0_X(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_X_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_X_MASK)
#define LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK     (0xFFFF0000U)
#define LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT    (16U)
/*! Y - Current Y location.
 */
#define LCDIF_DISPLAYCURRENTLOCATION0_Y(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYCURRENTLOCATION0_Y_SHIFT)) & LCDIF_DISPLAYCURRENTLOCATION0_Y_MASK)
/*! @} */

/*! @name GAMMAINDEX0 - Index into gamma table */
/*! @{ */
#define LCDIF_GAMMAINDEX0_INDEX_MASK             (0xFFU)
#define LCDIF_GAMMAINDEX0_INDEX_SHIFT            (0U)
/*! INDEX - Index into gamma table.
 */
#define LCDIF_GAMMAINDEX0_INDEX(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMAINDEX0_INDEX_SHIFT)) & LCDIF_GAMMAINDEX0_INDEX_MASK)
/*! @} */

/*! @name GAMMADATA0 - Translation values for the gamma table */
/*! @{ */
#define LCDIF_GAMMADATA0_BLUE_MASK               (0xFFU)
#define LCDIF_GAMMADATA0_BLUE_SHIFT              (0U)
/*! BLUE - Blue translation value.
 */
#define LCDIF_GAMMADATA0_BLUE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_BLUE_SHIFT)) & LCDIF_GAMMADATA0_BLUE_MASK)
#define LCDIF_GAMMADATA0_GREEN_MASK              (0xFF00U)
#define LCDIF_GAMMADATA0_GREEN_SHIFT             (8U)
/*! GREEN - Green translation value.
 */
#define LCDIF_GAMMADATA0_GREEN(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_GREEN_SHIFT)) & LCDIF_GAMMADATA0_GREEN_MASK)
#define LCDIF_GAMMADATA0_RED_MASK                (0xFF0000U)
#define LCDIF_GAMMADATA0_RED_SHIFT               (16U)
/*! RED - Red translation value.
 */
#define LCDIF_GAMMADATA0_RED(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_GAMMADATA0_RED_SHIFT)) & LCDIF_GAMMADATA0_RED_MASK)
/*! @} */

/*! @name CURSORCONFIG - Configuration register for the cursor */
/*! @{ */
#define LCDIF_CURSORCONFIG_FORMAT_MASK           (0x3U)
#define LCDIF_CURSORCONFIG_FORMAT_SHIFT          (0U)
/*! FORMAT - Format of the cursor.
 */
#define LCDIF_CURSORCONFIG_FORMAT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FORMAT_SHIFT)) & LCDIF_CURSORCONFIG_FORMAT_MASK)
#define LCDIF_CURSORCONFIG_DISPLAY_MASK          (0x10U)
#define LCDIF_CURSORCONFIG_DISPLAY_SHIFT         (4U)
/*! DISPLAY - Display Controller owning the cursor.
 *  0b0..DISPLAY0
 *  0b1..DISPLAY1
 */
#define LCDIF_CURSORCONFIG_DISPLAY(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_DISPLAY_SHIFT)) & LCDIF_CURSORCONFIG_DISPLAY_MASK)
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK       (0x1F00U)
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT      (8U)
/*! HOT_SPOT_Y - Vertical offset to cursor hotspot.
 */
#define LCDIF_CURSORCONFIG_HOT_SPOT_Y(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_Y_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_Y_MASK)
#define LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK       (0x1F0000U)
#define LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT      (16U)
/*! HOT_SPOT_X - Horizontal offset to cursor hotspot.
 */
#define LCDIF_CURSORCONFIG_HOT_SPOT_X(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_HOT_SPOT_X_SHIFT)) & LCDIF_CURSORCONFIG_HOT_SPOT_X_MASK)
#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_MASK (0x80000000U)
#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_SHIFT (31U)
/*! FLIP_IN_PROGRESS - When the cursor address gets written to, this bit gets set to one.
 */
#define LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_SHIFT)) & LCDIF_CURSORCONFIG_FLIP_IN_PROGRESS_MASK)
/*! @} */

/*! @name CURSORADDRESS - Address of the cursor shape */
/*! @{ */
#define LCDIF_CURSORADDRESS_ADDRESS_MASK         (0x7FFFFFFFU)
#define LCDIF_CURSORADDRESS_ADDRESS_SHIFT        (0U)
/*! ADDRESS - ADDRESS
 */
#define LCDIF_CURSORADDRESS_ADDRESS(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_ADDRESS_SHIFT)) & LCDIF_CURSORADDRESS_ADDRESS_MASK)
#define LCDIF_CURSORADDRESS_TYPE_MASK            (0x80000000U)
#define LCDIF_CURSORADDRESS_TYPE_SHIFT           (31U)
/*! TYPE - 0=SYSTEM; 1=VIRTUAL_SYSTEM
 */
#define LCDIF_CURSORADDRESS_TYPE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORADDRESS_TYPE_SHIFT)) & LCDIF_CURSORADDRESS_TYPE_MASK)
/*! @} */

/*! @name CURSORLOCATION - Location of the cursor on the owning display */
/*! @{ */
#define LCDIF_CURSORLOCATION_X_MASK              (0x1FFFU)
#define LCDIF_CURSORLOCATION_X_SHIFT             (0U)
/*! X - X location of cursor's hotspot.
 */
#define LCDIF_CURSORLOCATION_X(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_X_SHIFT)) & LCDIF_CURSORLOCATION_X_MASK)
#define LCDIF_CURSORLOCATION_Y_MASK              (0xFFF0000U)
#define LCDIF_CURSORLOCATION_Y_SHIFT             (16U)
/*! Y - Y location of cursor's hotspot.
 */
#define LCDIF_CURSORLOCATION_Y(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORLOCATION_Y_SHIFT)) & LCDIF_CURSORLOCATION_Y_MASK)
/*! @} */

/*! @name CURSORBACKGROUND - The background color for Masked cursors */
/*! @{ */
#define LCDIF_CURSORBACKGROUND_BLUE_MASK         (0xFFU)
#define LCDIF_CURSORBACKGROUND_BLUE_SHIFT        (0U)
/*! BLUE - Blue value.
 */
#define LCDIF_CURSORBACKGROUND_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_BLUE_SHIFT)) & LCDIF_CURSORBACKGROUND_BLUE_MASK)
#define LCDIF_CURSORBACKGROUND_GREEN_MASK        (0xFF00U)
#define LCDIF_CURSORBACKGROUND_GREEN_SHIFT       (8U)
/*! GREEN - Green value.
 */
#define LCDIF_CURSORBACKGROUND_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_GREEN_SHIFT)) & LCDIF_CURSORBACKGROUND_GREEN_MASK)
#define LCDIF_CURSORBACKGROUND_RED_MASK          (0xFF0000U)
#define LCDIF_CURSORBACKGROUND_RED_SHIFT         (16U)
/*! RED - Red value.
 */
#define LCDIF_CURSORBACKGROUND_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORBACKGROUND_RED_SHIFT)) & LCDIF_CURSORBACKGROUND_RED_MASK)
/*! @} */

/*! @name CURSORFOREGROUND - The foreground color for Masked cursors */
/*! @{ */
#define LCDIF_CURSORFOREGROUND_BLUE_MASK         (0xFFU)
#define LCDIF_CURSORFOREGROUND_BLUE_SHIFT        (0U)
/*! BLUE - Blue value.
 */
#define LCDIF_CURSORFOREGROUND_BLUE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_BLUE_SHIFT)) & LCDIF_CURSORFOREGROUND_BLUE_MASK)
#define LCDIF_CURSORFOREGROUND_GREEN_MASK        (0xFF00U)
#define LCDIF_CURSORFOREGROUND_GREEN_SHIFT       (8U)
/*! GREEN - Green value.
 */
#define LCDIF_CURSORFOREGROUND_GREEN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_GREEN_SHIFT)) & LCDIF_CURSORFOREGROUND_GREEN_MASK)
#define LCDIF_CURSORFOREGROUND_RED_MASK          (0xFF0000U)
#define LCDIF_CURSORFOREGROUND_RED_SHIFT         (16U)
/*! RED - Red value.
 */
#define LCDIF_CURSORFOREGROUND_RED(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CURSORFOREGROUND_RED_SHIFT)) & LCDIF_CURSORFOREGROUND_RED_MASK)
/*! @} */

/*! @name DISPLAYINTR - Display interrupt register */
/*! @{ */
#define LCDIF_DISPLAYINTR_DISP0_MASK             (0x1U)
#define LCDIF_DISPLAYINTR_DISP0_SHIFT            (0U)
/*! DISP0 - Display0 interrupt
 */
#define LCDIF_DISPLAYINTR_DISP0(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_DISP0_SHIFT)) & LCDIF_DISPLAYINTR_DISP0_MASK)
#define LCDIF_DISPLAYINTR_CURSOR_MASK            (0x100U)
#define LCDIF_DISPLAYINTR_CURSOR_SHIFT           (8U)
/*! CURSOR - Cursor interrupt
 */
#define LCDIF_DISPLAYINTR_CURSOR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_CURSOR_SHIFT)) & LCDIF_DISPLAYINTR_CURSOR_MASK)
#define LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_MASK (0x1000U)
#define LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_SHIFT (12U)
/*! DISP0_DBI_CFG_ERROR - Display0 DBI configure error
 */
#define LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_SHIFT)) & LCDIF_DISPLAYINTR_DISP0_DBI_CFG_ERROR_MASK)
/*! @} */

/*! @name DISPLAYINTRENABLE - The interrupt enable register for display_0 (and display_1 if present) */
/*! @{ */
#define LCDIF_DISPLAYINTRENABLE_DISP0_MASK       (0x1U)
#define LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT      (0U)
/*! DISP0 - Display0 interrupt enable
 */
#define LCDIF_DISPLAYINTRENABLE_DISP0(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DISPLAYINTRENABLE_DISP0_SHIFT)) & LCDIF_DISPLAYINTRENABLE_DISP0_MASK)
/*! @} */

/*! @name DBICONFIG0 - Configuration register for DBI output */
/*! @{ */
#define LCDIF_DBICONFIG0_DBI_TYPE_MASK           (0x3U)
#define LCDIF_DBICONFIG0_DBI_TYPE_SHIFT          (0U)
/*! DBI_TYPE - DBI Type select 0=TYPE_AFIXED_E; 1=TYPE_ACLOCK_E; 2=TYPE_B; 3=TYPE_C;
 */
#define LCDIF_DBICONFIG0_DBI_TYPE(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_TYPE_SHIFT)) & LCDIF_DBICONFIG0_DBI_TYPE_MASK)
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK    (0x3CU)
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT   (2U)
/*! DBI_DATA_FORMAT - DBI interface data format.
 */
#define LCDIF_DBICONFIG0_DBI_DATA_FORMAT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_DATA_FORMAT_SHIFT)) & LCDIF_DBICONFIG0_DBI_DATA_FORMAT_MASK)
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK     (0x40U)
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT    (6U)
/*! BUS_OUTPUT_SEL - Output bus select 0=DPI; 1=DBI;
 */
#define LCDIF_DBICONFIG0_BUS_OUTPUT_SEL(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_SHIFT)) & LCDIF_DBICONFIG0_BUS_OUTPUT_SEL_MASK)
#define LCDIF_DBICONFIG0_DBIX_POLARITY_MASK      (0x80U)
#define LCDIF_DBICONFIG0_DBIX_POLARITY_SHIFT     (7U)
/*! DBIX_POLARITY - D/CX Pin polarity 0=DEFAULT; 1=REVERSE;
 */
#define LCDIF_DBICONFIG0_DBIX_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBIX_POLARITY_SHIFT)) & LCDIF_DBICONFIG0_DBIX_POLARITY_MASK)
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK   (0xF00U)
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT  (8U)
/*! DBI_AC_TIME_UNIT - Time unit for AC characteristics
 */
#define LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_SHIFT)) & LCDIF_DBICONFIG0_DBI_AC_TIME_UNIT_MASK)
#define LCDIF_DBICONFIG0_DBI_TYPEC_OPT_MASK      (0x3000U)
#define LCDIF_DBICONFIG0_DBI_TYPEC_OPT_SHIFT     (12U)
/*! DBI_TYPEC_OPT - Options for DBI Type C Interface Read/Write Sequence; 0: Option 1; 1: Option 2; 2: Option 3.
 */
#define LCDIF_DBICONFIG0_DBI_TYPEC_OPT(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICONFIG0_DBI_TYPEC_OPT_SHIFT)) & LCDIF_DBICONFIG0_DBI_TYPEC_OPT_MASK)
/*! @} */

/*! @name DBIIFRESET0 - Reset DBI interface to idle state */
/*! @{ */
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK (0x1U)
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT (0U)
/*! DBI_IF_LEVEL_RESET - Reset DBI interface to idle state 1=RESET;
 */
#define LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_SHIFT)) & LCDIF_DBIIFRESET0_DBI_IF_LEVEL_RESET_MASK)
/*! @} */

/*! @name DBIWRCHAR10 - DBI write AC characteristics definition register 1 */
/*! @{ */
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK     (0xFFU)
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT    (0U)
/*! DBI_WR_PERIOD - Single write period duration.
 */
#define LCDIF_DBIWRCHAR10_DBI_WR_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_PERIOD_MASK)
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK (0xF00U)
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT (8U)
/*! DBI_WR_EOR_WR_ASSERT - Cycle number=Setting*(DbiAcTimeUnit+1).
 */
#define LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_EOR_WR_ASSERT_MASK)
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK  (0xF000U)
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT (12U)
/*! DBI_WR_CS_ASSERT - Cycle number=Setting*(DbiAcTimeUnit+1).
 */
#define LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_SHIFT)) & LCDIF_DBIWRCHAR10_DBI_WR_CS_ASSERT_MASK)
/*! @} */

/*! @name DBIWRCHAR20 - DBI write AC characteristics definition register 2 */
/*! @{ */
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK (0xFFU)
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT (0U)
/*! DBI_WR_EOR_WR_DE_ASRT - Cycle number=Setting*(DbiAcTimeUnit+1).
 */
#define LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_EOR_WR_DE_ASRT_MASK)
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK (0xFF00U)
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT (8U)
/*! DBI_WR_CS_DE_ASRT - Cycle number=Setting*(DbiAcTimeUnit+1).
 */
#define LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_SHIFT)) & LCDIF_DBIWRCHAR20_DBI_WR_CS_DE_ASRT_MASK)
/*! @} */

/*! @name DBICMD0 - DBI Command in/out port */
/*! @{ */
#define LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK      (0xFFFFU)
#define LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT     (0U)
/*! DBI_COMMAND_WORD - The type of data contained in this word is specified using DBI_COMMANDFLAG[bits 31:30].
 */
#define LCDIF_DBICMD0_DBI_COMMAND_WORD(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMAND_WORD_SHIFT)) & LCDIF_DBICMD0_DBI_COMMAND_WORD_MASK)
#define LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK       (0xC0000000U)
#define LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT      (30U)
/*! DBI_COMMANDFLAG - DBI command flag.
 */
#define LCDIF_DBICMD0_DBI_COMMANDFLAG(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_DBICMD0_DBI_COMMANDFLAG_SHIFT)) & LCDIF_DBICMD0_DBI_COMMANDFLAG_MASK)
/*! @} */

/*! @name DPICONFIG0 - The configuration register for DPI output */
/*! @{ */
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK    (0x7U)
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT   (0U)
/*! DPI_DATA_FORMAT - DPI interface data format.
 */
#define LCDIF_DPICONFIG0_DPI_DATA_FORMAT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DPICONFIG0_DPI_DATA_FORMAT_SHIFT)) & LCDIF_DPICONFIG0_DPI_DATA_FORMAT_MASK)
/*! @} */

/*! @name DCCHIPREV - Revision for the chip in BCD */
/*! @{ */
#define LCDIF_DCCHIPREV_REV_MASK                 (0xFFFFFFFFU)
#define LCDIF_DCCHIPREV_REV_SHIFT                (0U)
/*! REV - Revision.
 */
#define LCDIF_DCCHIPREV_REV(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPREV_REV_SHIFT)) & LCDIF_DCCHIPREV_REV_MASK)
/*! @} */

/*! @name DCCHIPDATE - Shows the release date for the IP in YYYYMMDD (year, month) */
/*! @{ */
#define LCDIF_DCCHIPDATE_DATE_MASK               (0xFFFFFFFFU)
#define LCDIF_DCCHIPDATE_DATE_SHIFT              (0U)
/*! DATE - Date.
 */
#define LCDIF_DCCHIPDATE_DATE(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPDATE_DATE_SHIFT)) & LCDIF_DCCHIPDATE_DATE_MASK)
/*! @} */

/*! @name DCCHIPPATCHREV - Patch revision */
/*! @{ */
#define LCDIF_DCCHIPPATCHREV_PATCH_REV_MASK      (0xFFFFFFFFU)
#define LCDIF_DCCHIPPATCHREV_PATCH_REV_SHIFT     (0U)
/*! PATCH_REV - Patch revision.
 */
#define LCDIF_DCCHIPPATCHREV_PATCH_REV(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCCHIPPATCHREV_PATCH_REV_SHIFT)) & LCDIF_DCCHIPPATCHREV_PATCH_REV_MASK)
/*! @} */

/*! @name DCTILEINCFG0 - Tile input configuration */
/*! @{ */
#define LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK      (0x3U)
#define LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT     (0U)
/*! TILE_FORMAT - Tile input data format 0 means non-tile input
 */
#define LCDIF_DCTILEINCFG0_TILE_FORMAT(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_TILE_FORMAT_SHIFT)) & LCDIF_DCTILEINCFG0_TILE_FORMAT_MASK)
#define LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK     (0xCU)
#define LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT    (2U)
/*! YUV_STANDARD - YUV standard select.
 */
#define LCDIF_DCTILEINCFG0_YUV_STANDARD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV_STANDARD_SHIFT)) & LCDIF_DCTILEINCFG0_YUV_STANDARD_MASK)
#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN_MASK      (0x10U)
#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN_SHIFT     (4U)
/*! YUV2_RGB_EN - YUV2RGB module enable
 */
#define LCDIF_DCTILEINCFG0_YUV2_RGB_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_YUV2_RGB_EN_SHIFT)) & LCDIF_DCTILEINCFG0_YUV2_RGB_EN_MASK)
#define LCDIF_DCTILEINCFG0_CFG_MODE_EN_MASK      (0x20U)
#define LCDIF_DCTILEINCFG0_CFG_MODE_EN_SHIFT     (5U)
/*! CFG_MODE_EN - Configuration mode enable 0=DISABLE; 1=ENABLE;
 */
#define LCDIF_DCTILEINCFG0_CFG_MODE_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEINCFG0_CFG_MODE_EN_SHIFT)) & LCDIF_DCTILEINCFG0_CFG_MODE_EN_MASK)
/*! @} */

/*! @name DCTILEUVFRAMEBUFFERADR0 - UV frame buffer address when tile input */
/*! @{ */
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK (0xFFFFFFFFU)
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT (0U)
/*! ADDRESS - UV frame buffer address when tile input
 */
#define LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERADR0_ADDRESS_MASK)
/*! @} */

/*! @name DCTILEUVFRAMEBUFFERSTR0 - UV frame buffer stride when tile input */
/*! @{ */
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK (0xFFFFU)
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT (0U)
/*! STRIDE - UV frame buffer stride when tile input
 */
#define LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_SHIFT)) & LCDIF_DCTILEUVFRAMEBUFFERSTR0_STRIDE_MASK)
/*! @} */

/*! @name DCPRODUCTID - Product ID */
/*! @{ */
#define LCDIF_DCPRODUCTID_PRODUCT_ID_MASK        (0xFFFFFFFFU)
#define LCDIF_DCPRODUCTID_PRODUCT_ID_SHIFT       (0U)
/*! PRODUCT_ID - Product ID.
 */
#define LCDIF_DCPRODUCTID_PRODUCT_ID(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_DCPRODUCTID_PRODUCT_ID_SHIFT)) & LCDIF_DCPRODUCTID_PRODUCT_ID_MASK)
/*! @} */

/*! @name DBITYPECCFG0 - DBI Type C write timing definition. */
/*! @{ */
#define LCDIF_DBITYPECCFG0_TAS_MASK              (0xFU)
#define LCDIF_DBITYPECCFG0_TAS_SHIFT             (0U)
/*! TAS - Divide counter for Tas (address setup time).
 */
#define LCDIF_DBITYPECCFG0_TAS(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_DBITYPECCFG0_TAS_SHIFT)) & LCDIF_DBITYPECCFG0_TAS_MASK)
#define LCDIF_DBITYPECCFG0_SCL_TWRL_MASK         (0xFF0U)
#define LCDIF_DBITYPECCFG0_SCL_TWRL_SHIFT        (4U)
/*! SCL_TWRL - Divide counter for Twrl (SCL L duration (write)).
 */
#define LCDIF_DBITYPECCFG0_SCL_TWRL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_DBITYPECCFG0_SCL_TWRL_SHIFT)) & LCDIF_DBITYPECCFG0_SCL_TWRL_MASK)
#define LCDIF_DBITYPECCFG0_SCL_TWRH_MASK         (0xFF000U)
#define LCDIF_DBITYPECCFG0_SCL_TWRH_SHIFT        (12U)
/*! SCL_TWRH - Divide counter for Twrl (SCL H duration (write)).
 */
#define LCDIF_DBITYPECCFG0_SCL_TWRH(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_DBITYPECCFG0_SCL_TWRH_SHIFT)) & LCDIF_DBITYPECCFG0_SCL_TWRH_MASK)
#define LCDIF_DBITYPECCFG0_SCL_SEL_MASK          (0x100000U)
#define LCDIF_DBITYPECCFG0_SCL_SEL_SHIFT         (20U)
/*! SCL_SEL - Determine the source of output Scl.
 */
#define LCDIF_DBITYPECCFG0_SCL_SEL(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_DBITYPECCFG0_SCL_SEL_SHIFT)) & LCDIF_DBITYPECCFG0_SCL_SEL_MASK)
/*! @} */

/*! @name DCSTATUS0 -  */
/*! @{ */
#define LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_MASK (0x1U)
#define LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_SHIFT (0U)
/*! DBI_TYPEC_FIFO_FULL - DBI Type C afifo full.
 */
#define LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_SHIFT)) & LCDIF_DCSTATUS0_DBI_TYPEC_FIFO_FULL_MASK)
/*! @} */

/*! @name DEBUGCOUNTERSELECT0 -  */
/*! @{ */
#define LCDIF_DEBUGCOUNTERSELECT0_SELECT_MASK    (0xFFU)
#define LCDIF_DEBUGCOUNTERSELECT0_SELECT_SHIFT   (0U)
/*! SELECT - Write a value to this field to pick up from 0~255 counters.
 */
#define LCDIF_DEBUGCOUNTERSELECT0_SELECT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_DEBUGCOUNTERSELECT0_SELECT_SHIFT)) & LCDIF_DEBUGCOUNTERSELECT0_SELECT_MASK)
/*! @} */

/*! @name DEBUGCOUNTERVALUE0 - Debug Counter Value as specified in DebugCounterSelect */
/*! @{ */
#define LCDIF_DEBUGCOUNTERVALUE0_VALUE_MASK      (0xFFFFFFFFU)
#define LCDIF_DEBUGCOUNTERVALUE0_VALUE_SHIFT     (0U)
/*! VALUE - Selected debug counter value
 */
#define LCDIF_DEBUGCOUNTERVALUE0_VALUE(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_DEBUGCOUNTERVALUE0_VALUE_SHIFT)) & LCDIF_DEBUGCOUNTERVALUE0_VALUE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group LCDIF_Register_Masks */


/* LCDIF - Peripheral instance base addresses */
/** Peripheral LCDIF base address */
#define LCDIF_BASE                               (0x40210000u)
/** Peripheral LCDIF base pointer */
#define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
/** Array initializer of LCDIF peripheral base addresses */
#define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
/** Array initializer of LCDIF peripheral base pointers */
#define LCDIF_BASE_PTRS                          { LCDIF }

/*!
 * @}
 */ /* end of group LCDIF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer
 * @{
 */

/** MIPI_DSI_HOST - Register Layout Typedef */
typedef struct {
  __IO uint32_t DSI_HOST_CFG_NUM_LANES;            /**< , offset: 0x0 */
  __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK;    /**< , offset: 0x4 */
  __IO uint32_t DSI_HOST_CFG_T_PRE;                /**< , offset: 0x8 */
  __IO uint32_t DSI_HOST_CFG_T_POST;               /**< , offset: 0xC */
  __IO uint32_t DSI_HOST_CFG_TX_GAP;               /**< , offset: 0x10 */
  __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP;      /**< , offset: 0x14 */
  __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */
  __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT;         /**< , offset: 0x1C */
  __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT;       /**< , offset: 0x20 */
  __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT;       /**< , offset: 0x24 */
  __IO uint32_t DSI_HOST_CFG_TWAKEUP;              /**< , offset: 0x28 */
  __I  uint32_t DSI_HOST_CFG_STATUS_OUT;           /**< , offset: 0x2C */
  __I  uint32_t DSI_HOST_RX_ERROR_STATUS;          /**< , offset: 0x30 */
       uint8_t RESERVED_0[204];
  __IO uint32_t DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x100 */
  __IO uint32_t DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x104 */
       uint8_t RESERVED_1[248];
  __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< , offset: 0x200 */
  __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x204 */
  __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< , offset: 0x208 */
  __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT;     /**< , offset: 0x20C */
  __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY;   /**< , offset: 0x210 */
  __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY;   /**< , offset: 0x214 */
  __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE;       /**< , offset: 0x218 */
  __IO uint32_t DSI_HOST_CFG_DPI_HFP;              /**< , offset: 0x21C */
  __IO uint32_t DSI_HOST_CFG_DPI_HBP;              /**< , offset: 0x220 */
  __IO uint32_t DSI_HOST_CFG_DPI_HSA;              /**< , offset: 0x224 */
  __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< , offset: 0x228 */
  __IO uint32_t DSI_HOST_CFG_DPI_VBP;              /**< , offset: 0x22C */
  __IO uint32_t DSI_HOST_CFG_DPI_VFP;              /**< , offset: 0x230 */
  __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE;        /**< , offset: 0x234 */
  __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< , offset: 0x238 */
  __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE;          /**< , offset: 0x23C */
  __IO uint32_t DSI_HOST_CFG_DPI_VC;               /**< , offset: 0x240 */
       uint8_t RESERVED_2[60];
  __IO uint32_t DSI_HOST_TX_PAYLOAD;               /**< , offset: 0x280 */
  __IO uint32_t DSI_HOST_PKT_CONTROL;              /**< , offset: 0x284 */
  __IO uint32_t DSI_HOST_SEND_PACKET;              /**< , offset: 0x288 */
  __I  uint32_t DSI_HOST_PKT_STATUS;               /**< , offset: 0x28C */
  __I  uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL;        /**< , offset: 0x290 */
  __I  uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL;        /**< , offset: 0x294 */
  __I  uint32_t DSI_HOST_PKT_RX_PAYLOAD;           /**< , offset: 0x298 */
  __I  uint32_t DSI_HOST_PKT_RX_PKT_HEADER;        /**< , offset: 0x29C */
  __I  uint32_t DSI_HOST_IRQ_STATUS;               /**< , offset: 0x2A0 */
  __I  uint32_t DSI_HOST_IRQ_STATUS2;              /**< , offset: 0x2A4 */
  __IO uint32_t DSI_HOST_IRQ_MASK;                 /**< , offset: 0x2A8 */
  __IO uint32_t DSI_HOST_IRQ_MASK2;                /**< , offset: 0x2AC */
       uint8_t RESERVED_3[80];
  __IO uint32_t DPHY_PD_DPHY;                      /**< , offset: 0x300 */
  __IO uint32_t DPHY_M_PRG_HS_PREPARE;             /**< , offset: 0x304 */
  __IO uint32_t DPHY_MC_PRG_HS_PREPARE;            /**< , offset: 0x308 */
  __IO uint32_t DPHY_M_PRG_HS_ZERO;                /**< , offset: 0x30C */
  __IO uint32_t DPHY_MC_PRG_HS_ZERO;               /**< , offset: 0x310 */
  __IO uint32_t DPHY_M_PRG_HS_TRAIL;               /**< , offset: 0x314 */
  __IO uint32_t DPHY_MC_PRG_HS_TRAIL;              /**< , offset: 0x318 */
  __IO uint32_t DPHY_TST;                          /**< , offset: 0x31C */
  __IO uint32_t DPHY_RTERM_SEL;                    /**< , offset: 0x320 */
  __IO uint32_t DPHY_AUTO_PD_EN;                   /**< , offset: 0x324 */
  __IO uint32_t DPHY_RXLPRP;                       /**< , offset: 0x328 */
  __IO uint32_t DPHY_RXCDRP;                       /**< , offset: 0x32C */
} MIPI_DSI_HOST_Type;

/* ----------------------------------------------------------------------------
   -- MIPI_DSI_HOST Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks
 * @{
 */

/*! @name DSI_HOST_CFG_NUM_LANES -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U)
/*! dsi_host_cfg_num_lanes - Sets the number of active lanes that are to be used for transmitting data.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U)
/*! dsi_host_cfg_noncontinuous_clk - Sets the Host Controller into non-continuous MIPI clock mode.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_T_PRE -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0x7FU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U)
/*! dsi_host_cfg_t_pre - Sets the number of byte clock periods ('clk_byte' input) that the
 *    controller will wait after enabling the clock lane for HS operation before enabling the data lanes for
 *    HS operation.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK (0xFFFFFF80U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT (7U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_T_POST -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0x7FU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U)
/*! dsi_host_cfg_t_post - Sets the number of byte clock periods ('clk_byte' input) to wait before
 *    putting the clock lane into LP mode after the data lanes have been detected to be in Stop State.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK (0xFFFFFF80U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT (7U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_TX_GAP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK (0x7FU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT (0U)
/*! dsi_host_cfg_tx_gap - Sets the number of byte clock periods ('clk_byte' input) that the
 *    controller will wait after the clock lane has been put into LP mode before enabling the clock lane for
 *    HS mode again.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_gap_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK (0xFFFFFF80U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT (7U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_AUTOINSERT_EOTP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U)
/*! dsi_host_cfg_autoinsert_eotp - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U)
/*! dsi_host_cfg_extra_cmds_after_eotp - Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK (0xFFFFFF00U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT (8U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_HTX_TO_COUNT -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U)
/*! dsi_host_cfg_htx_to_count - Sets the value of the DSI Host High Speed TX timeout count in
 *    clk_byte clock periods that once reached will initiate a timeout error and follow the recovery
 *    procedure documented in the DSI specification.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK (0xFF000000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT (24U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_LRX_H_TO_COUNT -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U)
/*! dsi_host_cfg_lrx_h_to_count - Sets the value of the DSI Host low power RX timeout count in
 *    clk_byte clock periods that once reached will initiate a timeout error and follow the recovery
 *    procedure documented in the DSI specification.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK (0xFF000000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT (24U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_BTA_H_TO_COUNT -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U)
/*! dsi_host_cfg_bta_h_to_count - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in
 *    clk_byte clock periods that once reached will initiate a timeout error.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK (0xFF000000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT (24U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_TWAKEUP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U)
/*! dsi_host_cfg_twakeup - DPHY Twakeup timing parameter.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK (0xFFF80000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT (19U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_STATUS_OUT -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT (0U)
/*! dsi_host_cfg_status_out - Status Register
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK)
/*! @} */

/*! @name DSI_HOST_RX_ERROR_STATUS -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU)
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U)
/*! dsi_host_rx_error_status - Status Register for Host receive error detection, ECC errors, CRC
 *    errors and for timeout indicators [0] ECC single bit error detected [1] ECC multi bit error
 *    detected [6:2] Errored bit position for single bit ECC error [7] CRC error detected [8] High Speed
 *    forward TX timeout detected [9] Reverse Low power data receive timeout detected [10] BTA
 *    timeout detected
 */
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK)
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK (0xFFFFF800U)
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT (11U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_SHIFT (0U)
/*! dsi_host_cfg_dbi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dbi_pixel_payload_size_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_PAYLOAD_SIZE_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_SHIFT (0U)
/*! dsi_host_cfg_dbi_pixel_fifo_send_level - In order to optimize DSI utility, the DBI bridge buffers a cerntain number of DBI pixels before initiating a DSI packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dbi_pixel_fifo_send_level_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DBI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U)
/*! dsi_host_cfg_dpi_pixel_payload_size - Maximum number of pixels that should be sent as one DSI packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U)
/*! dsi_host_cfg_dpi_pixel_fifo_send_level - In order to optimize DSI utility, the DPI bridge buffers a cerntain number of DPI pixels before initiating a DSI packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U)
/*! dsi_host_cfg_dpi_interface_color_coding - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK (0xFFFFFFF8U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT (3U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U)
/*! dsi_host_cfg_dpi_pixel_format - Sets the DSI packet type of the pixels.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U)
/*! dsi_host_cfg_dpi_vsync_polarity - Sets polarity of dpi_vsync_input 0 - active low 1 - active high
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U)
/*! dsi_host_cfg_dpi_hsync_polarity - Sets polarity of dpi_hsync_input 0 - active low 1 - active high
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_VIDEO_MODE -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U)
/*! dsi_host_cfg_dpi_video_mode - Select DSI video mode that the host DPI module should generate packets for.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_HFP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U)
/*! dsi_host_cfg_dpi_hfp - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_HBP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U)
/*! dsi_host_cfg_dpi_hbp - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_HSA -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U)
/*! dsi_host_cfg_dpi_hsa - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U)
/*! dsi_host_cfg_dpi_enable_mult_pkts - Enable Multiple packets per video line.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_VBP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U)
/*! dsi_host_cfg_dpi_vbp - Sets the number of lines in the vertical back porch.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK (0xFFFFFF00U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT (8U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_VFP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U)
/*! dsi_host_cfg_dpi_vfp - Sets the number of lines in the vertical front porch.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK (0xFFFFFF00U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT (8U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_BLLP_MODE -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U)
/*! dsi_host_cfg_dpi_bllp_mode - Optimize bllp periods to Low Power mode when possible 0 - blanking
 *    packets are sent during BLLP periods 1 - LP mode is used for BLLP periods
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U)
/*! dsi_host_cfg_dpi_use_null_pkt_bllp - Selects type of blanking packet to be sent during bllp
 *    region 0 - Blanking packet used in bllp region 1 - Null packet used in bllp region
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_VACTIVE -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U)
/*! dsi_host_cfg_dpi_vactive - Sets the number of lines in the vertical active aread.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK (0xFFFFC000U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT (14U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_CFG_DPI_VC -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U)
/*! dsi_host_cfg_dpi_vc - Sets the Virtual Channel (VC) of packets that will be sent to the receive packet interface.
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_TX_PAYLOAD -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U)
/*! dsi_host_tx_payload - Tx Payload data write register.
 */
#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK)
/*! @} */

/*! @name DSI_HOST_PKT_CONTROL -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U)
/*! dsi_host_pkt_control - Tx packet control register.
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK)
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK (0xF8000000U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT (27U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_SEND_PACKET -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U)
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U)
/*! dsi_host_send_packet - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
 */
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK)
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_PKT_STATUS -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U)
/*! dsi_host_pkt_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx
 *    packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow
 *    [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header
 *    has been received [8] - all rx packet payload data has been received
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK)
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK (0xFFFFFE00U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT (9U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_PKT_FIFO_WR_LEVEL -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U)
/*! dsi_host_pkt_fifo_wr_level - Write level of APB to pkt interface fifo
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_PKT_FIFO_RD_LEVEL -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U)
/*! dsi_host_pkt_fifo_rd_level - Read level of APB to pkt interface fifo
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK (0xFFFF0000U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT (16U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_PKT_RX_PAYLOAD -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U)
/*! dsi_host_pkt_rx_payload - APB to pkt interface rx payload read
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK)
/*! @} */

/*! @name DSI_HOST_PKT_RX_PKT_HEADER -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U)
/*! dsi_host_pkt_rx_pkt_header - APB to pkt interface rx packet header [15:0] word count [21:16] data type [23:22] Virtual Channel
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK (0xFF000000U)
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT (24U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_IRQ_STATUS -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U)
/*! dsi_host_irq_status - Status of APB to packet interface [0] - state machine not idle [1] - Tx
 *    packet done [2] - dphy direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow
 *    [4] - tx fifo underflow [5] - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header
 *    has been received [8] - all rx packet payload data has been received [28:9] - map directory to
 *    dsi host controller status_out port bit descriptions [29] - high speed tx timeout, host
 *    controller hs_tx_timeout port [30] - low power rx timeout, host controller lp_rx_timeout port [31] -
 *    host bta timeout, host controller host_bta_timeout port
 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK)
/*! @} */

/*! @name DSI_HOST_IRQ_STATUS2 -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U)
/*! dsi_host_irq_status2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status.
 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK (0xFFFFFFF8U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT (3U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_reserved_MASK)
/*! @} */

/*! @name DSI_HOST_IRQ_MASK -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U)
/*! dsi_host_irq_mask - irq mask [0] - state machine not idle [1] - Tx packet done [2] - dphy
 *    direction 0 - tx had control, 1 - rx has control [3] - tx fifo overflow [4] - tx fifo underflow [5]
 *    - rx fifo overflow [6] - rx fifo underflow [7] - rx packet header has been received [8] - all
 *    rx packet payload data has been received [28:9] - map directory to dsi host controller
 *    status_out port bit descriptions [29] - high speed tx timeout, host controller hs_tx_timeout port
 *    [30] - low power rx timeout, host controller lp_rx_timeout port [31] - host bta timeout, host
 *    controller host_bta_timeout port
 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK)
/*! @} */

/*! @name DSI_HOST_IRQ_MASK2 -  */
/*! @{ */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U)
/*! dsi_host_irq_mask2 - irq mask 2 [0] - single bit ecc error [1] - multi bit ecc error [2] - crc error
 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK (0xFFFFFFF8U)
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT (3U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_reserved_MASK)
/*! @} */

/*! @name DPHY_PD_DPHY -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT (0U)
/*! dphy_pd_dphy - DPHY PD_DPHY input control, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_DPHY_dphy_pd_dphy_MASK)
#define MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_PD_DPHY_reserved(x)   (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_DPHY_reserved_MASK)
/*! @} */

/*! @name DPHY_M_PRG_HS_PREPARE -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U)
/*! dphy_m_prg_hs_prepare - DPHY m_PRG_HS_PREPARE input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_reserved_MASK)
/*! @} */

/*! @name DPHY_MC_PRG_HS_PREPARE -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U)
/*! dphy_mc_prg_hs_prepare - DPHY mc_PRG_HS_PREPARE input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_reserved_MASK)
/*! @} */

/*! @name DPHY_M_PRG_HS_ZERO -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U)
/*! dphy_m_prg_hs_zero - DPHY m_PRG_HS_ZERO input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK (0xFFFFFFE0U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT (5U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_reserved_MASK)
/*! @} */

/*! @name DPHY_MC_PRG_HS_ZERO -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U)
/*! dphy_mc_prg_hs_zero - DPHY mc_PRG_HS_ZERO input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK (0xFFFFFFC0U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT (6U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_reserved_MASK)
/*! @} */

/*! @name DPHY_M_PRG_HS_TRAIL -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U)
/*! dphy_m_prg_hs_trail - DPHY m_PRG_HS_TRAIL input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U)
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT (4U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_reserved_MASK)
/*! @} */

/*! @name DPHY_MC_PRG_HS_TRAIL -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U)
/*! dphy_mc_prg_hs_trail - DPHY mc_PRG_HS_TRAIL input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK (0xFFFFFFF0U)
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT (4U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_reserved_MASK)
/*! @} */

/*! @name DPHY_TST -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK     (0x3FU)
#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT    (0U)
/*! dphy_tst - DPHY TST input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_TST_dphy_tst(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK)
#define MIPI_DSI_HOST_DPHY_TST_reserved_MASK     (0xFFFFFFC0U)
#define MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT    (6U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_TST_reserved(x)       (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_reserved_MASK)
/*! @} */

/*! @name DPHY_RTERM_SEL -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT (0U)
/*! dphy_rterm_sel - DPHY RTERM_SEL input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_SHIFT)) & MIPI_DSI_HOST_DPHY_RTERM_SEL_dphy_rterm_sel_MASK)
#define MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RTERM_SEL_reserved_MASK)
/*! @} */

/*! @name DPHY_AUTO_PD_EN -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U)
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U)
/*! dphy_auto_pd_en - DPHY AUTO_PD_EN input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK)
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK (0xFFFFFFFEU)
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT (1U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_reserved_MASK)
/*! @} */

/*! @name DPHY_RXLPRP -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U)
/*! dphy_rxlprp - DPHY RXLPRP input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK)
#define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK  (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_RXLPRP_reserved(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_reserved_MASK)
/*! @} */

/*! @name DPHY_RXCDRP -  */
/*! @{ */
#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U)
#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U)
/*! dphy_rxcdrp - DPHY RXCDRP input, see DPHY datasheet
 */
#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK)
#define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK  (0xFFFFFFFCU)
#define MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT (2U)
/*! reserved - reserved
 */
#define MIPI_DSI_HOST_DPHY_RXCDRP_reserved(x)    (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_reserved_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_reserved_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Register_Masks */


/* MIPI_DSI_HOST - Peripheral instance base addresses */
/** Peripheral MIPI_DSI_HOST base address */
#define MIPI_DSI_HOST_BASE                       (0x40031000u)
/** Peripheral MIPI_DSI_HOST base pointer */
#define MIPI_DSI_HOST                            ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE)
/** Array initializer of MIPI_DSI_HOST peripheral base addresses */
#define MIPI_DSI_HOST_BASE_ADDRS                 { MIPI_DSI_HOST_BASE }
/** Array initializer of MIPI_DSI_HOST peripheral base pointers */
#define MIPI_DSI_HOST_BASE_PTRS                  { MIPI_DSI_HOST }

/*!
 * @}
 */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- MRT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
 * @{
 */

/** MRT - Register Layout Typedef */
typedef struct {
  struct {                                         /* offset: 0x0, array step: 0x10 */
    __IO uint32_t INTVAL;                            /**< Time Interval Value, array offset: 0x0, array step: 0x10 */
    __I  uint32_t TIMER;                             /**< Timer, array offset: 0x4, array step: 0x10 */
    __IO uint32_t CTRL;                              /**< Control, array offset: 0x8, array step: 0x10 */
    __IO uint32_t STAT;                              /**< Status, array offset: 0xC, array step: 0x10 */
  } CHANNEL[4];
       uint8_t RESERVED_0[176];
  __IO uint32_t MODCFG;                            /**< Module Configuration, offset: 0xF0 */
  __I  uint32_t IDLE_CH;                           /**< Idle Channel, offset: 0xF4 */
  __IO uint32_t IRQ_FLAG;                          /**< Global Interrupt Flag, offset: 0xF8 */
  __I  uint32_t ID_CODE;                           /**< Multi-Rate Timer ID code, offset: 0xFC */
} MRT_Type;

/* ----------------------------------------------------------------------------
   -- MRT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MRT_Register_Masks MRT Register Masks
 * @{
 */

/*! @name CHANNEL_INTVAL - Time Interval Value */
/*! @{ */
#define MRT_CHANNEL_INTVAL_IVALUE_MASK           (0xFFFFFFU)
#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT          (0U)
/*! IVALUE - Time interval load value.
 */
#define MRT_CHANNEL_INTVAL_IVALUE(x)             (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
#define MRT_CHANNEL_INTVAL_LOAD_MASK             (0x80000000U)
#define MRT_CHANNEL_INTVAL_LOAD_SHIFT            (31U)
/*! LOAD - Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register.
 *  0b0..No force load.
 *  0b1..Force load. T
 */
#define MRT_CHANNEL_INTVAL_LOAD(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
/*! @} */

/* The count of MRT_CHANNEL_INTVAL */
#define MRT_CHANNEL_INTVAL_COUNT                 (4U)

/*! @name CHANNEL_TIMER - Timer */
/*! @{ */
#define MRT_CHANNEL_TIMER_VALUE_MASK             (0xFFFFFFU)
#define MRT_CHANNEL_TIMER_VALUE_SHIFT            (0U)
/*! VALUE - Holds the current timer value of the down-counter.
 */
#define MRT_CHANNEL_TIMER_VALUE(x)               (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_TIMER */
#define MRT_CHANNEL_TIMER_COUNT                  (4U)

/*! @name CHANNEL_CTRL - Control */
/*! @{ */
#define MRT_CHANNEL_CTRL_INTEN_MASK              (0x1U)
#define MRT_CHANNEL_CTRL_INTEN_SHIFT             (0U)
/*! INTEN - Enable the TIMER n interrupt.
 *  0b0..Disabled. TIMER n interrupt is disabled.
 *  0b1..Enabled. TIMER n interrupt is enabled.
 */
#define MRT_CHANNEL_CTRL_INTEN(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
#define MRT_CHANNEL_CTRL_MODE_MASK               (0x6U)
#define MRT_CHANNEL_CTRL_MODE_SHIFT              (1U)
/*! MODE - Selects the timer mode
 *  0b00..Repeat interrupt mode
 *  0b01..One-shot interrupt mode
 *  0b10..One-shot stall mode
 *  0b11..Reserved
 */
#define MRT_CHANNEL_CTRL_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_CTRL */
#define MRT_CHANNEL_CTRL_COUNT                   (4U)

/*! @name CHANNEL_STAT - Status */
/*! @{ */
#define MRT_CHANNEL_STAT_INTFLAG_MASK            (0x1U)
#define MRT_CHANNEL_STAT_INTFLAG_SHIFT           (0U)
/*! INTFLAG - Monitors the interrupt flag
 *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
 *  0b1..Pending interrupt.
 */
#define MRT_CHANNEL_STAT_INTFLAG(x)              (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
#define MRT_CHANNEL_STAT_RUN_MASK                (0x2U)
#define MRT_CHANNEL_STAT_RUN_SHIFT               (1U)
/*! RUN - Indicates the state of TIMER n . RUN bit is read-only.
 *  0b0..Idle state. TIMER n has stopped.
 *  0b1..Running. TIMER n is running.
 */
#define MRT_CHANNEL_STAT_RUN(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
#define MRT_CHANNEL_STAT_INUSE_MASK              (0x4U)
#define MRT_CHANNEL_STAT_INUSE_SHIFT             (2U)
/*! INUSE - Channel-In-Use flag. Operating details depend on the operating mode bit
 *    (MODCFG.MULTITASK), and affects the use of the Idle Channel register (IDLE_CH).
 *  0b0..This timer channel is not in use.
 *  0b1..This timer channel is in use.
 */
#define MRT_CHANNEL_STAT_INUSE(x)                (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
/*! @} */

/* The count of MRT_CHANNEL_STAT */
#define MRT_CHANNEL_STAT_COUNT                   (4U)

/*! @name MODCFG - Module Configuration */
/*! @{ */
#define MRT_MODCFG_NOC_MASK                      (0xFU)
#define MRT_MODCFG_NOC_SHIFT                     (0U)
/*! NOC - Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded)
 */
#define MRT_MODCFG_NOC(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
#define MRT_MODCFG_NOB_MASK                      (0x1F0U)
#define MRT_MODCFG_NOB_SHIFT                     (4U)
/*! NOB - Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this device)
 */
#define MRT_MODCFG_NOB(x)                        (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
#define MRT_MODCFG_MULTITASK_MASK                (0x80000000U)
#define MRT_MODCFG_MULTITASK_SHIFT               (31U)
/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.
 *  0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.
 *  0b1..Multi-task mode
 */
#define MRT_MODCFG_MULTITASK(x)                  (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
/*! @} */

/*! @name IDLE_CH - Idle Channel */
/*! @{ */
#define MRT_IDLE_CH_CHAN_MASK                    (0xF0U)
#define MRT_IDLE_CH_CHAN_SHIFT                   (4U)
/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
 *    positioned so that it can be used as an offset from the MRT base address, to access the
 *    registers for the allocated channel. If all timer channels are running, then CHAN = 0xF.
 */
#define MRT_IDLE_CH_CHAN(x)                      (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
/*! @} */

/*! @name IRQ_FLAG - Global Interrupt Flag */
/*! @{ */
#define MRT_IRQ_FLAG_GFLAG0_MASK                 (0x1U)
#define MRT_IRQ_FLAG_GFLAG0_SHIFT                (0U)
/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
 *  0b0..No pending interrupt. Writing a zero is equivalent to no operation.
 *  0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
 *       the INTEN bit in the CONTROL0 register is also set to 1, then the interrupt for timer channel 0 and the
 *       global interrupt are generated. Writing a 1 to GFLAG0 bit clears the interrupt request.
 */
#define MRT_IRQ_FLAG_GFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
#define MRT_IRQ_FLAG_GFLAG1_MASK                 (0x2U)
#define MRT_IRQ_FLAG_GFLAG1_SHIFT                (1U)
/*! GFLAG1 - Monitors the interrupt flag of TIMER1, and acts similarly to channel 0.
 */
#define MRT_IRQ_FLAG_GFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
#define MRT_IRQ_FLAG_GFLAG2_MASK                 (0x4U)
#define MRT_IRQ_FLAG_GFLAG2_SHIFT                (2U)
/*! GFLAG2 - Monitors the interrupt flag of TIMER2, and acts similarly to channel 0.
 */
#define MRT_IRQ_FLAG_GFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
#define MRT_IRQ_FLAG_GFLAG3_MASK                 (0x8U)
#define MRT_IRQ_FLAG_GFLAG3_SHIFT                (3U)
/*! GFLAG3 - Monitors the interrupt flag of TIMER3, and acts similarly to channel 0.
 */
#define MRT_IRQ_FLAG_GFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
/*! @} */

/*! @name ID_CODE - Multi-Rate Timer ID code */
/*! @{ */
#define MRT_ID_CODE_ID_CODE_MASK                 (0xFFFFFFFFU)
#define MRT_ID_CODE_ID_CODE_SHIFT                (0U)
/*! ID_CODE - Multi-Rate Timer ID code
 */
#define MRT_ID_CODE_ID_CODE(x)                   (((uint32_t)(((uint32_t)(x)) << MRT_ID_CODE_ID_CODE_SHIFT)) & MRT_ID_CODE_ID_CODE_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MRT_Register_Masks */


/* MRT - Peripheral instance base addresses */
/** Peripheral MRT0 base address */
#define MRT0_BASE                                (0x4002D000u)
/** Peripheral MRT0 base pointer */
#define MRT0                                     ((MRT_Type *)MRT0_BASE)
/** Array initializer of MRT peripheral base addresses */
#define MRT_BASE_ADDRS                           { MRT0_BASE }
/** Array initializer of MRT peripheral base pointers */
#define MRT_BASE_PTRS                            { MRT0 }
/** Interrupt vectors for the MRT peripheral type */
#define MRT_IRQS                                 { MRT0_IRQn }

/*!
 * @}
 */ /* end of group MRT_Peripheral_Access_Layer */

/*!
 * @brief Power mode definition.
 */
typedef enum _mu_power_mode
{
    kMU_PowerModeRun = 0x00U,   /*!< Run mode.           */
    kMU_PowerModeWait = 0x01U,  /*!< WAIT mode.          */
} mu_power_mode_t;


/* ----------------------------------------------------------------------------
   -- MU Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
 * @{
 */

/** MU - Register Layout Typedef */
typedef struct {
  __I  uint32_t VER;                               /**< Version ID Register, offset: 0x0 */
  __I  uint32_t PAR;                               /**< Parameter Register, offset: 0x4 */
       uint8_t RESERVED_0[24];
  __IO uint32_t TR[4];                             /**< Transmit Register, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_1[16];
  __I  uint32_t RR[4];                             /**< Receive Register, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_2[16];
  __IO uint32_t SR;                                /**< Status Register, offset: 0x60 */
  __IO uint32_t CR;                                /**< Control Register, offset: 0x64 */
} MU_Type;

/* ----------------------------------------------------------------------------
   -- MU Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup MU_Register_Masks MU Register Masks
 * @{
 */

/*! @name VER - Version ID Register */
/*! @{ */
#define MU_VER_FEATURE_MASK                      (0xFFFFU)
#define MU_VER_FEATURE_SHIFT                     (0U)
/*! FEATURE - Feature Specification Number
 *  0b000000000000x1xx..Core Control and Status Registers are implemented in both MUA and MUB.
 *  0b000000000000xx1x..RAIP/RAIE register bits are implemented.
 *  0b000000000000xxx0..Standard features implemented
 */
#define MU_VER_FEATURE(x)                        (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK)
#define MU_VER_MINOR_MASK                        (0xFF0000U)
#define MU_VER_MINOR_SHIFT                       (16U)
/*! MINOR - Minor Version Number
 */
#define MU_VER_MINOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK)
#define MU_VER_MAJOR_MASK                        (0xFF000000U)
#define MU_VER_MAJOR_SHIFT                       (24U)
/*! MAJOR - Major Version Number
 */
#define MU_VER_MAJOR(x)                          (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK)
/*! @} */

/*! @name PAR - Parameter Register */
/*! @{ */
#define MU_PAR_PARAMETER_MASK                    (0xFFFFFFFFU)
#define MU_PAR_PARAMETER_SHIFT                   (0U)
/*! PARAMETER - This bitfield contains the parameter settings of MUB.
 */
#define MU_PAR_PARAMETER(x)                      (((uint32_t)(((uint32_t)(x)) << MU_PAR_PARAMETER_SHIFT)) & MU_PAR_PARAMETER_MASK)
/*! @} */

/*! @name TR - Transmit Register */
/*! @{ */
#define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
#define MU_TR_DATA_SHIFT                         (0U)
/*! DATA - DATA
 */
#define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
/*! @} */

/* The count of MU_TR */
#define MU_TR_COUNT                              (4U)

/*! @name RR - Receive Register */
/*! @{ */
#define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
#define MU_RR_DATA_SHIFT                         (0U)
/*! DATA - DATA
 */
#define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
/*! @} */

/* The count of MU_RR */
#define MU_RR_COUNT                              (4U)

/*! @name SR - Status Register */
/*! @{ */
#define MU_SR_Fn_MASK                            (0x7U)
#define MU_SR_Fn_SHIFT                           (0U)
/*! Fn - Fn
 *  0b000..Fn bit in the MUA CR register is written 0 (default).
 *  0b001..Fn bit in the MUA CR register is written 1.
 */
#define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
#define MU_SR_EP_MASK                            (0x10U)
#define MU_SR_EP_SHIFT                           (4U)
/*! EP - EP
 *  0b0..The MUB side event is not pending (default).
 *  0b1..The MUB side event is pending.
 */
#define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
#define MU_SR_PM_MASK                            (0x60U)
#define MU_SR_PM_SHIFT                           (5U)
/*! PM - PM
 *  0b00..The MUA processor is in Run Mode.
 *  0b01..The MUA processor is in WAIT Mode.
 *  0b10..The MUA processor is in STOP/VLPS Mode.
 *  0b11..The MUA processor is in LLS/VLLS Mode.
 */
#define MU_SR_PM(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK)
#define MU_SR_RS_MASK                            (0x80U)
#define MU_SR_RS_SHIFT                           (7U)
/*! RS - RS
 *  0b0..The MUA side of the MU is not in reset.
 *  0b1..The MUA side of the MU is in reset.
 */
#define MU_SR_RS(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
#define MU_SR_FUP_MASK                           (0x100U)
#define MU_SR_FUP_SHIFT                          (8U)
/*! FUP - FUP
 *  0b0..No flags updated, initiated by the MUB, in progress (default)
 *  0b1..MUB initiated flags update, processing
 */
#define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
#define MU_SR_TEn_MASK                           (0xF00000U)
#define MU_SR_TEn_SHIFT                          (20U)
/*! TEn - TEn
 *  0b0000..MUB TRn register is not empty.
 *  0b0001..MUB TRn register is empty (default).
 */
#define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
#define MU_SR_RFn_MASK                           (0xF000000U)
#define MU_SR_RFn_SHIFT                          (24U)
/*! RFn - RFn
 *  0b0000..MUB RRn register is not full (default).
 *  0b0001..MUB RRn register has received data from MUA TRn register and is ready to be read by the MUB.
 */
#define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
#define MU_SR_GIPn_MASK                          (0xF0000000U)
#define MU_SR_GIPn_SHIFT                         (28U)
/*! GIPn - GIPn
 *  0b0000..MUB general purpose interrupt n is not pending. (default)
 *  0b0001..MUB general purpose interrupt n is pending.
 */
#define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
/*! @} */

/*! @name CR - Control Register */
/*! @{ */
#define MU_CR_Fn_MASK                            (0x7U)
#define MU_CR_Fn_SHIFT                           (0U)
/*! Fn - Fn
 *  0b000..Clears the Fn bit in the SR register.
 *  0b001..Sets the Fn bit in the SR register.
 */
#define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
#define MU_CR_GIRn_MASK                          (0xF0000U)
#define MU_CR_GIRn_SHIFT                         (16U)
/*! GIRn - GIRn
 *  0b0000..MUB General Interrupt n is not requested to the MUA (default).
 *  0b0001..MUB General Interrupt n is requested to the MUA.
 */
#define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
#define MU_CR_TIEn_MASK                          (0xF00000U)
#define MU_CR_TIEn_SHIFT                         (20U)
/*! TIEn - TIEn
 *  0b0000..Disables MUB Transmit Interrupt n. (default)
 *  0b0001..Enables MUB Transmit Interrupt n.
 */
#define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
#define MU_CR_RIEn_MASK                          (0xF000000U)
#define MU_CR_RIEn_SHIFT                         (24U)
/*! RIEn - RIEn
 *  0b0000..Disables MUB Receive Interrupt n. (default)
 *  0b0001..Enables MUB Receive Interrupt n.
 */
#define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
#define MU_CR_GIEn_MASK                          (0xF0000000U)
#define MU_CR_GIEn_SHIFT                         (28U)
/*! GIEn - GIEn
 *  0b0000..Disables MUB General Interrupt n. (default)
 *  0b0001..Enables MUB General Interrupt n.
 */
#define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group MU_Register_Masks */


/* MU - Peripheral instance base addresses */
/** Peripheral MUB base address */
#define MUB_BASE                                 (0x40111000u)
/** Peripheral MUB base pointer */
#define MUB                                      ((MU_Type *)MUB_BASE)
/** Array initializer of MU peripheral base addresses */
#define MU_BASE_ADDRS                            { MUB_BASE }
/** Array initializer of MU peripheral base pointers */
#define MU_BASE_PTRS                             { MUB }

/*!
 * @}
 */ /* end of group MU_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OCOTP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
 * @{
 */

/** OCOTP - Register Layout Typedef */
typedef struct {
  __IO uint32_t OTP_SHADOW[496];                   /**< OTP shadow register N, array offset: 0x0, array step: 0x4 */
  __IO uint32_t MTR[16];                           /**< MTR register N, array offset: 0x7C0, array step: 0x4 */
  __IO uint32_t OTP_CTRL;                          /**< Control/address register, offset: 0x800 */
  __IO uint32_t OTP_PDN;                           /**< Power-down register, offset: 0x804 */
  __IO uint32_t OTP_WRITE_DATA;                    /**< OTP programming data register, offset: 0x808 */
  __IO uint32_t OTP_READ_CTRL;                     /**< OTP read start register, offset: 0x80C */
  __I  uint32_t OTP_READ_DATA;                     /**< OTP read data register, offset: 0x810 */
  __IO uint32_t OTP_CLK_DIV;                       /**< OTP clock divider register, offset: 0x814 */
       uint8_t RESERVED_0[4];
  __IO uint32_t OTP_CRC_ADDR;                      /**< CRC address range register, offset: 0x81C */
  __I  uint32_t OTP_CRC_VALUE;                     /**< CRC result register, offset: 0x820 */
  __IO uint32_t OTP_STATUS;                        /**< Status register, offset: 0x824 */
  __IO uint32_t OTP_STARTWORD;                     /**< OTP STARTWORD register, offset: 0x828 */
  __I  uint32_t OTP_VERSION;                       /**< VERSION ID register, offset: 0x82C */
} OCOTP_Type;

/* ----------------------------------------------------------------------------
   -- OCOTP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
 * @{
 */

/*! @name OTP_SHADOW - OTP shadow register N */
/*! @{ */
#define OCOTP_OTP_SHADOW_shadow_MASK             (0xFFFFFFFFU)
#define OCOTP_OTP_SHADOW_shadow_SHIFT            (0U)
/*! shadow - OTP shadow register
 */
#define OCOTP_OTP_SHADOW_shadow(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_SHADOW_shadow_SHIFT)) & OCOTP_OTP_SHADOW_shadow_MASK)
/*! @} */

/* The count of OCOTP_OTP_SHADOW */
#define OCOTP_OTP_SHADOW_COUNT                   (496U)

/*! @name OTP_MTR_MTR - MTR register N */
/*! @{ */
#define OCOTP_OTP_MTR_MTR_MTR_MASK               (0xFFFFFFFFU)
#define OCOTP_OTP_MTR_MTR_MTR_SHIFT              (0U)
/*! MTR - MTR register
 */
#define OCOTP_OTP_MTR_MTR_MTR(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_MTR_MTR_MTR_SHIFT)) & OCOTP_OTP_MTR_MTR_MTR_MASK)
/*! @} */

/* The count of OCOTP_OTP_MTR_MTR */
#define OCOTP_OTP_MTR_MTR_COUNT                  (16U)

/*! @name OTP_CTRL - Control/address register */
/*! @{ */
#define OCOTP_OTP_CTRL_ADDR_MASK                 (0x1FFU)
#define OCOTP_OTP_CTRL_ADDR_SHIFT                (0U)
/*! ADDR - OTP word address for read/programming
 */
#define OCOTP_OTP_CTRL_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_ADDR_SHIFT)) & OCOTP_OTP_CTRL_ADDR_MASK)
#define OCOTP_OTP_CTRL_RELOAD_SHADOWS_MASK       (0x800U)
#define OCOTP_OTP_CTRL_RELOAD_SHADOWS_SHIFT      (11U)
/*! RELOAD_SHADOWS - Set to force re-loading the shadow registers (HW/SW capability and LOCK). This
 *    operation will automatically set OTP_STATUS.BUSY. Once the shadow registers have been
 *    re-loaded, OTP_STATUS.BUSY and RELOAD_SHADOWS are automatically cleared by the controller
 */
#define OCOTP_OTP_CTRL_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_OTP_CTRL_RELOAD_SHADOWS_MASK)
#define OCOTP_OTP_CTRL_CRC_TEST_MASK             (0x1000U)
#define OCOTP_OTP_CTRL_CRC_TEST_SHIFT            (12U)
/*! CRC_TEST - Set to start CRC calculation. This operation will automatically set OTP_STATUS.BUSY.
 *    Once CRC is calculation done, OTP_STATUS.BUSY and CRC_TEST are automatically cleared by the
 *    controller
 */
#define OCOTP_OTP_CTRL_CRC_TEST(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_OTP_CTRL_CRC_TEST_MASK)
#define OCOTP_OTP_CTRL_SUPPADD_MASK              (0x4000U)
#define OCOTP_OTP_CTRL_SUPPADD_SHIFT             (14U)
/*! SUPPADD - This bit should be set when programming or reading the supplementary address space (aka test row)
 */
#define OCOTP_OTP_CTRL_SUPPADD(x)                (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_SUPPADD_SHIFT)) & OCOTP_OTP_CTRL_SUPPADD_MASK)
#define OCOTP_OTP_CTRL_WORDLOCK_MASK             (0x8000U)
#define OCOTP_OTP_CTRL_WORDLOCK_SHIFT            (15U)
/*! WORDLOCK - Set to write-lock the fuse word when it's being programming. When programming with
 *    ECC mode, it recommends to set this bit.
 */
#define OCOTP_OTP_CTRL_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_OTP_CTRL_WORDLOCK_MASK)
#define OCOTP_OTP_CTRL_WR_UNLOCK_MASK            (0xFFFF0000U)
#define OCOTP_OTP_CTRL_WR_UNLOCK_SHIFT           (16U)
/*! WR_UNLOCK - Write 0x3E77 to enable OTP write accesses. NOTE: The write operation must be
 *    unlocked for each word by writing 0x3E77 to WR_UNLOCK field. Then writing to OTP_WRITE_DATA register
 *    will automatically start the programming procedure.
 */
#define OCOTP_OTP_CTRL_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_OTP_CTRL_WR_UNLOCK_MASK)
/*! @} */

/*! @name OTP_PDN - Power-down register */
/*! @{ */
#define OCOTP_OTP_PDN_PDN_MASK                   (0x1U)
#define OCOTP_OTP_PDN_PDN_SHIFT                  (0U)
/*! PDN - This bit indicates the PDN value of OTP memory. Writing 1 to the bit to clear PDN. Writing
 *    0 has no effect. Note: Software need to write 1 to this bit to shut off power of OTP memory
 *    after system power up. At the beginning of every fuse operation, the controller will
 *    automatically turn-on power to the OPT memory. After every fuse operation, software also need to write 1
 *    to this bit to shut off power to the OTP memory to reduce power consumption.
 */
#define OCOTP_OTP_PDN_PDN(x)                     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_PDN_PDN_SHIFT)) & OCOTP_OTP_PDN_PDN_MASK)
/*! @} */

/*! @name OTP_WRITE_DATA - OTP programming data register */
/*! @{ */
#define OCOTP_OTP_WRITE_DATA_WRITE_DATA_MASK     (0xFFFFFFFFU)
#define OCOTP_OTP_WRITE_DATA_WRITE_DATA_SHIFT    (0U)
/*! WRITE_DATA - Fuse word programming data. After the write operation is unlocked in OTP_CTRL
 *    register, writing data to this register automatically start the programming procedure.
 */
#define OCOTP_OTP_WRITE_DATA_WRITE_DATA(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_WRITE_DATA_WRITE_DATA_SHIFT)) & OCOTP_OTP_WRITE_DATA_WRITE_DATA_MASK)
/*! @} */

/*! @name OTP_READ_CTRL - OTP read start register */
/*! @{ */
#define OCOTP_OTP_READ_CTRL_READ_MASK            (0x1U)
#define OCOTP_OTP_READ_CTRL_READ_SHIFT           (0U)
#define OCOTP_OTP_READ_CTRL_READ(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_READ_CTRL_READ_SHIFT)) & OCOTP_OTP_READ_CTRL_READ_MASK)
/*! @} */

/*! @name OTP_READ_DATA - OTP read data register */
/*! @{ */
#define OCOTP_OTP_READ_DATA_READ_DATA_MASK       (0xFFFFFFFFU)
#define OCOTP_OTP_READ_DATA_READ_DATA_SHIFT      (0U)
/*! READ_DATA - Fuse word read data from read operation
 */
#define OCOTP_OTP_READ_DATA_READ_DATA(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_READ_DATA_READ_DATA_SHIFT)) & OCOTP_OTP_READ_DATA_READ_DATA_MASK)
/*! @} */

/*! @name OTP_CLK_DIV - OTP clock divider register */
/*! @{ */
#define OCOTP_OTP_CLK_DIV_DIV_MASK               (0xFU)
#define OCOTP_OTP_CLK_DIV_DIV_SHIFT              (0U)
/*! DIV - Clock divider value by -1 encoding. It's used to generate the clock to OTP memory
 *    (otp_clk) with apb_clk. The maximum otp_clk frequency is 120Mhz. 0: Divide by 1
 *  0b0000..Divide by 1
 *  0b0001..Divide by 2
 *  0b0010..Divide by 3
 *  0b0011..Divide by 4
 *  0b0100..Divide by 5
 *  0b0101..Divide by 6
 *  0b0110..Divide by 7
 *  0b0111..Divide by 8
 *  0b1000..Divide by 9
 *  0b1001..Divide by 10
 *  0b1010..Divide by 11
 *  0b1011..Divide by 12
 *  0b1100..Divide by 13
 *  0b1101..Divide by 14
 *  0b1110..Divide by 15
 *  0b1111..Divide by 16
 */
#define OCOTP_OTP_CLK_DIV_DIV(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_DIV_SHIFT)) & OCOTP_OTP_CLK_DIV_DIV_MASK)
#define OCOTP_OTP_CLK_DIV_RESET_MASK             (0x20000000U)
#define OCOTP_OTP_CLK_DIV_RESET_SHIFT            (29U)
/*! RESET - Resets the divider counter. Can be used to make sure a new divider value is used right
 *    away rather than completing the previous count.
 */
#define OCOTP_OTP_CLK_DIV_RESET(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_RESET_SHIFT)) & OCOTP_OTP_CLK_DIV_RESET_MASK)
#define OCOTP_OTP_CLK_DIV_HALT_MASK              (0x40000000U)
#define OCOTP_OTP_CLK_DIV_HALT_SHIFT             (30U)
/*! HALT - Halts the divider counter. The intent is to allow the divider's clock source to be
 *    changed without the risk of a glitch at the output.
 */
#define OCOTP_OTP_CLK_DIV_HALT(x)                (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_HALT_SHIFT)) & OCOTP_OTP_CLK_DIV_HALT_MASK)
#define OCOTP_OTP_CLK_DIV_REQFLAG_MASK           (0x80000000U)
#define OCOTP_OTP_CLK_DIV_REQFLAG_SHIFT          (31U)
/*! REQFLAG - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete.
 */
#define OCOTP_OTP_CLK_DIV_REQFLAG(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CLK_DIV_REQFLAG_SHIFT)) & OCOTP_OTP_CLK_DIV_REQFLAG_MASK)
/*! @} */

/*! @name OTP_CRC_ADDR - CRC address range register */
/*! @{ */
#define OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_MASK   (0x1FFU)
#define OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_SHIFT  (0U)
/*! CRC_START_ADDR - CRC starting fuse word address
 */
#define OCOTP_OTP_CRC_ADDR_CRC_START_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_SHIFT)) & OCOTP_OTP_CRC_ADDR_CRC_START_ADDR_MASK)
#define OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_MASK     (0x1FF000U)
#define OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_SHIFT    (12U)
/*! CRC_END_ADDR - CRC ending fuse word address
 */
#define OCOTP_OTP_CRC_ADDR_CRC_END_ADDR(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_SHIFT)) & OCOTP_OTP_CRC_ADDR_CRC_END_ADDR_MASK)
#define OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_MASK     (0x7000000U)
#define OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_SHIFT    (24U)
/*! CRC_REF_ADDR - Specify which of the 8 CRC reference value to use for CRC calculation. When the
 *    CRC result for the fuse data from CRC_START_ADDR to CRC_END_ADDR and this CRC reference value
 *    is 0, the CRC check passes.
 */
#define OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_SHIFT)) & OCOTP_OTP_CRC_ADDR_CRC_REF_ADDR_MASK)
/*! @} */

/*! @name OTP_CRC_VALUE - CRC result register */
/*! @{ */
#define OCOTP_OTP_CRC_VALUE_CRC_VALUE_MASK       (0xFFFFFFFFU)
#define OCOTP_OTP_CRC_VALUE_CRC_VALUE_SHIFT      (0U)
/*! CRC_VALUE - The CRC result value. When it is locked, reading from it returns value 0xBADA_BADA
 */
#define OCOTP_OTP_CRC_VALUE_CRC_VALUE(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_CRC_VALUE_CRC_VALUE_SHIFT)) & OCOTP_OTP_CRC_VALUE_CRC_VALUE_MASK)
/*! @} */

/*! @name OTP_STATUS - Status register */
/*! @{ */
#define OCOTP_OTP_STATUS_DOUT_40_32_MASK         (0x1FFU)
#define OCOTP_OTP_STATUS_DOUT_40_32_SHIFT        (0U)
/*! DOUT_40_32 - OTP DOUT - output data bus [40:32]
 */
#define OCOTP_OTP_STATUS_DOUT_40_32(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_DOUT_40_32_SHIFT)) & OCOTP_OTP_STATUS_DOUT_40_32_MASK)
#define OCOTP_OTP_STATUS_SEC_MASK                (0x200U)
#define OCOTP_OTP_STATUS_SEC_SHIFT               (9U)
/*! SEC - OTP Single Error Corrected status of ECC during read operation. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_SEC(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_SEC_SHIFT)) & OCOTP_OTP_STATUS_SEC_MASK)
#define OCOTP_OTP_STATUS_DED_MASK                (0x400U)
#define OCOTP_OTP_STATUS_DED_SHIFT               (10U)
/*! DED - OTP Double Error Detection status of ECC during read operation. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_DED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_DED_SHIFT)) & OCOTP_OTP_STATUS_DED_MASK)
#define OCOTP_OTP_STATUS_LOCKED_MASK             (0x800U)
#define OCOTP_OTP_STATUS_LOCKED_SHIFT            (11U)
/*! LOCKED - OTP LOCKED status during read/write operation. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_LOCKED(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_LOCKED_SHIFT)) & OCOTP_OTP_STATUS_LOCKED_MASK)
#define OCOTP_OTP_STATUS_PROGFAIL_MASK           (0x1000U)
#define OCOTP_OTP_STATUS_PROGFAIL_SHIFT          (12U)
/*! PROGFAIL - OTP PROGFAIL status. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_PROGFAIL(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_PROGFAIL_SHIFT)) & OCOTP_OTP_STATUS_PROGFAIL_MASK)
#define OCOTP_OTP_STATUS_ACK_MASK                (0x2000U)
#define OCOTP_OTP_STATUS_ACK_SHIFT               (13U)
/*! ACK - OTP ACK value
 */
#define OCOTP_OTP_STATUS_ACK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_ACK_SHIFT)) & OCOTP_OTP_STATUS_ACK_MASK)
#define OCOTP_OTP_STATUS_PWOK_MASK               (0x4000U)
#define OCOTP_OTP_STATUS_PWOK_SHIFT              (14U)
/*! PWOK - OTP Power OK status. Indicate that power VDD are in the operating range.
 */
#define OCOTP_OTP_STATUS_PWOK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_PWOK_SHIFT)) & OCOTP_OTP_STATUS_PWOK_MASK)
#define OCOTP_OTP_STATUS_FLAGSTATE_MASK          (0xF0000U)
#define OCOTP_OTP_STATUS_FLAGSTATE_SHIFT         (16U)
/*! FLAGSTATE - OTP FLATSTATE[3:0] value
 *  0b0000..Power-down
 *  0b0001..Stand-by
 *  0b0010..Read and self-controlled phased
 *  0b0011..Programming
 *  0b0100..BIST stand-by
 *  0b0101..BIST1
 *  0b0110..BIST2
 *  0b0111..Reserved
 *  0b1000..Reserved
 *  0b1001..Reserved
 *  0b1010..Reserved
 *  0b1011..Programming Sequence Control
 *  0b1100..Reserved
 *  0b1101..Reserved
 *  0b1110..Reserved
 *  0b1111..Reserved
 */
#define OCOTP_OTP_STATUS_FLAGSTATE(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OTP_STATUS_FLAGSTATE_MASK)
#define OCOTP_OTP_STATUS_SEC_RELOAD_MASK         (0x100000U)
#define OCOTP_OTP_STATUS_SEC_RELOAD_SHIFT        (20U)
/*! SEC_RELOAD - OTP Single Error Corrected status of ECC during reload process. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_SEC_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OTP_STATUS_SEC_RELOAD_MASK)
#define OCOTP_OTP_STATUS_DED_RELOAD_MASK         (0x200000U)
#define OCOTP_OTP_STATUS_DED_RELOAD_SHIFT        (21U)
/*! DED_RELOAD - OTP Double Error Detect status of ECC during reload process. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_DED_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OTP_STATUS_DED_RELOAD_MASK)
#define OCOTP_OTP_STATUS_BUSY_MASK               (0x400000U)
#define OCOTP_OTP_STATUS_BUSY_SHIFT              (22U)
/*! BUSY - OTP controller status bit. When active, no new write or read access to OTP (including
 *    RELOAD_SHADOWS) can be performed. Cleared by the controller when the access completes. After
 *    reset (or after setting RELOAD_SHADOWS), this bit is set by the controller and cleared after all
 *    the shadow registers are successfully loaded.
 */
#define OCOTP_OTP_STATUS_BUSY(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_BUSY_SHIFT)) & OCOTP_OTP_STATUS_BUSY_MASK)
#define OCOTP_OTP_STATUS_ERROR_MASK              (0x800000U)
#define OCOTP_OTP_STATUS_ERROR_SHIFT             (23U)
/*! ERROR - Set by the controller when a read/write access to a locked region (OTP or shadow
 *    register) is requested. Writing 1 to clear it before any further access can be performed. This bit
 *    can only be set by the controller.
 */
#define OCOTP_OTP_STATUS_ERROR(x)                (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_ERROR_SHIFT)) & OCOTP_OTP_STATUS_ERROR_MASK)
#define OCOTP_OTP_STATUS_CRC_FAIL_MASK           (0x1000000U)
#define OCOTP_OTP_STATUS_CRC_FAIL_SHIFT          (24U)
/*! CRC_FAIL - CRC failed when set by hardware for CRC operation. Write 1 to clear.
 */
#define OCOTP_OTP_STATUS_CRC_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_CRC_FAIL_SHIFT)) & OCOTP_OTP_STATUS_CRC_FAIL_MASK)
#define OCOTP_OTP_STATUS_FUSE_LATCHED_MASK       (0x2000000U)
#define OCOTP_OTP_STATUS_FUSE_LATCHED_SHIFT      (25U)
/*! FUSE_LATCHED - Indicate all shadows registers have been loaded with their corresponding fuse
 *    words when set by the controller after reset.
 */
#define OCOTP_OTP_STATUS_FUSE_LATCHED(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_FUSE_LATCHED_SHIFT)) & OCOTP_OTP_STATUS_FUSE_LATCHED_MASK)
#define OCOTP_OTP_STATUS_CALIBRATED_MASK         (0x4000000U)
#define OCOTP_OTP_STATUS_CALIBRATED_SHIFT        (26U)
/*! CALIBRATED - OTP CALIBRATED status
 */
#define OCOTP_OTP_STATUS_CALIBRATED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STATUS_CALIBRATED_SHIFT)) & OCOTP_OTP_STATUS_CALIBRATED_MASK)
/*! @} */

/*! @name OTP_STARTWORD - OTP STARTWORD register */
/*! @{ */
#define OCOTP_OTP_STARTWORD_STARTWORD_MASK       (0xFFFFU)
#define OCOTP_OTP_STARTWORD_STARTWORD_SHIFT      (0U)
/*! STARTWORD - OTP memory STARTWORD value (i.e. test row word 0 value)
 */
#define OCOTP_OTP_STARTWORD_STARTWORD(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_STARTWORD_STARTWORD_SHIFT)) & OCOTP_OTP_STARTWORD_STARTWORD_MASK)
/*! @} */

/*! @name OTP_VERSION - VERSION ID register */
/*! @{ */
#define OCOTP_OTP_VERSION_STEP_VER_MASK          (0xFFFFU)
#define OCOTP_OTP_VERSION_STEP_VER_SHIFT         (0U)
/*! STEP_VER - OTP controller step version
 */
#define OCOTP_OTP_VERSION_STEP_VER(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_STEP_VER_SHIFT)) & OCOTP_OTP_VERSION_STEP_VER_MASK)
#define OCOTP_OTP_VERSION_MINOR_VER_MASK         (0xFF0000U)
#define OCOTP_OTP_VERSION_MINOR_VER_SHIFT        (16U)
/*! MINOR_VER - OTP controller minor version
 */
#define OCOTP_OTP_VERSION_MINOR_VER(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_MINOR_VER_SHIFT)) & OCOTP_OTP_VERSION_MINOR_VER_MASK)
#define OCOTP_OTP_VERSION_MAJOR_VER_MASK         (0xFF000000U)
#define OCOTP_OTP_VERSION_MAJOR_VER_SHIFT        (24U)
/*! MAJOR_VER - OTP controller major version
 */
#define OCOTP_OTP_VERSION_MAJOR_VER(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OTP_VERSION_MAJOR_VER_SHIFT)) & OCOTP_OTP_VERSION_MAJOR_VER_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OCOTP_Register_Masks */


/* OCOTP - Peripheral instance base addresses */
/** Peripheral OCOTP0 base address */
#define OCOTP0_BASE                              (0x40130000u)
/** Peripheral OCOTP0 base pointer */
#define OCOTP0                                   ((OCOTP_Type *)OCOTP0_BASE)
/** Array initializer of OCOTP peripheral base addresses */
#define OCOTP_BASE_ADDRS                         { OCOTP0_BASE }
/** Array initializer of OCOTP peripheral base pointers */
#define OCOTP_BASE_PTRS                          { OCOTP0 }

/*!
 * @}
 */ /* end of group OCOTP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OSTIMER Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer
 * @{
 */

/** OSTIMER - Register Layout Typedef */
typedef struct {
  __I  uint32_t EVTIMERL;                          /**< EVTIMER Low Register, offset: 0x0 */
  __I  uint32_t EVTIMERH;                          /**< EVTIMER High Register, offset: 0x4 */
  __I  uint32_t CAPTUREN_L;                        /**< Local Capture Low Register for CPUn, offset: 0x8 */
  __I  uint32_t CAPTUREN_H;                        /**< Local Capture High Register for CPUn, offset: 0xC */
  __IO uint32_t MATCHN_L;                          /**< Local Match Low Register for CPUn, offset: 0x10 */
  __IO uint32_t MATCHN_H;                          /**< Local Match High Register for CPUn, offset: 0x14 */
       uint8_t RESERVED_0[4];
  __IO uint32_t OSEVENT_CTRL;                      /**< OS Event Timer Control Register for CPUn, offset: 0x1C */
} OSTIMER_Type;

/* ----------------------------------------------------------------------------
   -- OSTIMER Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks
 * @{
 */

/*! @name EVTIMERL - EVTIMER Low Register */
/*! @{ */
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)
/*! EVTIMER_COUNT_VALUE - EVTimer Count value
 */
#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)
/*! @} */

/*! @name EVTIMERH - EVTIMER High Register */
/*! @{ */
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)
/*! EVTIMER_COUNT_VALUE - EVTimer Count value
 */
#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x)  (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)
/*! @} */

/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */
/*! @{ */
#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK   (0xFFFFFFFFU)
#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT  (0U)
/*! CAPTUREn_VALUE - EVTimer Capture value
 */
#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK)
/*! @} */

/*! @name CAPTUREN_H - Local Capture High Register for CPUn */
/*! @{ */
#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK   (0xFFFFFFFFU)
#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT  (0U)
/*! CAPTUREn_VALUE - EVTimer Capture value
 */
#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK)
/*! @} */

/*! @name MATCHN_L - Local Match Low Register for CPUn */
/*! @{ */
#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK       (0xFFFFFFFFU)
#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT      (0U)
/*! MATCHn_VALUE - EVTimer Match value
 */
#define OSTIMER_MATCHN_L_MATCHn_VALUE(x)         (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK)
/*! @} */

/*! @name MATCHN_H - Local Match High Register for CPUn */
/*! @{ */
#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK       (0xFFFFFFFFU)
#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT      (0U)
/*! MATCHn_VALUE - EVTimer Match value
 */
#define OSTIMER_MATCHN_H_MATCHn_VALUE(x)         (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK)
/*! @} */

/*! @name OSEVENT_CTRL - OS Event Timer Control Register for CPUn */
/*! @{ */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)
/*! OSTIMER_INTRFLAG - Interrupt Flag
 */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)
/*! OSTIMER_INTENA - Interrupt/Wake-up Request
 *  0b0..Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked.
 *  0b1..An interrupt/wake-up request to the domain processor will be asserted when the OSTIMER_INTR flag is set.
 */
#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x)   (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDYn_MASK  (0x4U)
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDYn_SHIFT (2U)
/*! MATCH_WR_RDYn - EVTimer Match Write Ready
 */
#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDYn(x)    (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDYn_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDYn_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group OSTIMER_Register_Masks */


/* OSTIMER - Peripheral instance base addresses */
/** Peripheral OSTIMER1 base address */
#define OSTIMER1_BASE                            (0x40114000u)
/** Peripheral OSTIMER1 base pointer */
#define OSTIMER1                                 ((OSTIMER_Type *)OSTIMER1_BASE)
/** Array initializer of OSTIMER peripheral base addresses */
#define OSTIMER_BASE_ADDRS                       { OSTIMER1_BASE }
/** Array initializer of OSTIMER peripheral base pointers */
#define OSTIMER_BASE_PTRS                        { OSTIMER1 }

/*!
 * @}
 */ /* end of group OSTIMER_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- OTFAD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
 * @{
 */

/** OTFAD - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[3072];
  __IO uint32_t CR;                                /**< Control Register, offset: 0xC00 */
  __IO uint32_t SR;                                /**< Status Register, offset: 0xC04 */
       uint8_t RESERVED_1[248];
  struct {                                         /* offset: 0xD00, array step: 0x40 */
    __IO uint32_t KEY[4];                            /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
    __IO uint32_t CTR[2];                            /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
    __IO uint32_t RGD_W0;                            /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
    __IO uint32_t RGD_W1;                            /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
         uint8_t RESERVED_0[32];
  } CTX[4];
} OTFAD_Type;

/* ----------------------------------------------------------------------------
   -- OTFAD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
 * @{
 */

/*! @name CR - Control Register */
/*! @{ */
#define OTFAD_CR_IRQE_MASK                       (0x1U)
#define OTFAD_CR_IRQE_SHIFT                      (0U)
/*! IRQE - IRQE
 *  0b0..SR[KBERR] = 1 does not generate an interrupt request.
 *  0b1..SR[KBERR] = 1 generates an interrupt request.
 */
#define OTFAD_CR_IRQE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_IRQE_SHIFT)) & OTFAD_CR_IRQE_MASK)
#define OTFAD_CR_FERR_MASK                       (0x2U)
#define OTFAD_CR_FERR_SHIFT                      (1U)
/*! FERR - Force Error
 *  0b0..No effect on the SR[KBERE] indicator.
 *  0b1..SR[KBERR] is immediately set after a write with this data bit set.
 */
#define OTFAD_CR_FERR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
#define OTFAD_CR_FLDM_MASK                       (0x8U)
#define OTFAD_CR_FLDM_SHIFT                      (3U)
/*! FLDM - Force Logically Disabled Mode
 *  0b0..No effect on the operating mode.
 *  0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
 */
#define OTFAD_CR_FLDM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
#define OTFAD_CR_KBSE_MASK                       (0x10U)
#define OTFAD_CR_KBSE_SHIFT                      (4U)
/*! KBSE - Key Blob Scramble Enable
 *  0b0..Key blob KEK scrambling is disabled.
 *  0b1..Key blob KEK scrambling is enabled.
 */
#define OTFAD_CR_KBSE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
#define OTFAD_CR_KBPE_MASK                       (0x20U)
#define OTFAD_CR_KBPE_SHIFT                      (5U)
/*! KBPE - Key Blob Processing Enable
 *  0b0..Key blob processing is disabled.
 *  0b1..Key blob processing is enabled.
 */
#define OTFAD_CR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
#define OTFAD_CR_KBCE_MASK                       (0x40U)
#define OTFAD_CR_KBCE_SHIFT                      (6U)
/*! KBCE - Key Blob CRC Enable
 *  0b0..CRC-32 during key blob processing is disabled.
 *  0b1..CRC-32 during key blob processing is enabled.
 */
#define OTFAD_CR_KBCE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBCE_SHIFT)) & OTFAD_CR_KBCE_MASK)
#define OTFAD_CR_RRAE_MASK                       (0x80U)
#define OTFAD_CR_RRAE_SHIFT                      (7U)
/*! RRAE - Restricted Register Access Enable
 *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
 *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
 */
#define OTFAD_CR_RRAE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
#define OTFAD_CR_SKBP_MASK                       (0x40000000U)
#define OTFAD_CR_SKBP_SHIFT                      (30U)
/*! SKBP - Start key blob processing
 *  0b0..Key blob processing is not initiated.
 *  0b1..Properly-enabled key blob processing is initiated.
 */
#define OTFAD_CR_SKBP(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
#define OTFAD_CR_GE_MASK                         (0x80000000U)
#define OTFAD_CR_GE_SHIFT                        (31U)
/*! GE - Global OTFAD Enable
 *  0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
 *  0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
 */
#define OTFAD_CR_GE(x)                           (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
/*! @} */

/*! @name SR - Status Register */
/*! @{ */
#define OTFAD_SR_KBERR_MASK                      (0x1U)
#define OTFAD_SR_KBERR_SHIFT                     (0U)
/*! KBERR - Key Blob Error
 *  0b0..No key blob error detected.
 *  0b1..One or more key blob errors has been detected.
 */
#define OTFAD_SR_KBERR(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
#define OTFAD_SR_MDPCP_MASK                      (0x2U)
#define OTFAD_SR_MDPCP_SHIFT                     (1U)
/*! MDPCP - MDPC Present
 */
#define OTFAD_SR_MDPCP(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
#define OTFAD_SR_MODE_MASK                       (0xCU)
#define OTFAD_SR_MODE_SHIFT                      (2U)
/*! MODE - Operating Mode
 *  0b00..Operating in Normal mode (NRM)
 *  0b01..Unused (reserved)
 *  0b10..Unused (reserved)
 *  0b11..Operating in Logically Disabled Mode (LDM)
 */
#define OTFAD_SR_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
#define OTFAD_SR_NCTX_MASK                       (0xF0U)
#define OTFAD_SR_NCTX_SHIFT                      (4U)
/*! NCTX - Number of Contexts
 */
#define OTFAD_SR_NCTX(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
#define OTFAD_SR_CTXER0_MASK                     (0x100U)
#define OTFAD_SR_CTXER0_SHIFT                    (8U)
/*! CTXER0 - Context Error
 *  0b0..No key blob error was detected for context "n".
 *  0b1..Either a key blob integrity error or a key blob CRC error was detected in context "n".
 */
#define OTFAD_SR_CTXER0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
#define OTFAD_SR_CTXER1_MASK                     (0x200U)
#define OTFAD_SR_CTXER1_SHIFT                    (9U)
/*! CTXER1 - Context Error
 *  0b0..No key blob error was detected for context "n".
 *  0b1..Either a key blob integrity error or a key blob CRC error was detected in context "n".
 */
#define OTFAD_SR_CTXER1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
#define OTFAD_SR_CTXER2_MASK                     (0x400U)
#define OTFAD_SR_CTXER2_SHIFT                    (10U)
/*! CTXER2 - Context Error
 *  0b0..No key blob error was detected for context "n".
 *  0b1..Either a key blob integrity error or a key blob CRC error was detected in context "n".
 */
#define OTFAD_SR_CTXER2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
#define OTFAD_SR_CTXER3_MASK                     (0x800U)
#define OTFAD_SR_CTXER3_SHIFT                    (11U)
/*! CTXER3 - Context Error
 *  0b0..No key blob error was detected for context "n".
 *  0b1..Either a key blob integrity error or a key blob CRC error was detected in context "n".
 */
#define OTFAD_SR_CTXER3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
#define OTFAD_SR_CTXIE0_MASK                     (0x10000U)
#define OTFAD_SR_CTXIE0_SHIFT                    (16U)
/*! CTXIE0 - Context Integrity Error
 *  0b0..No key blob integrity error was detected for context "n".
 *  0b1..A key blob integrity error was detected in context "n".
 */
#define OTFAD_SR_CTXIE0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
#define OTFAD_SR_CTXIE1_MASK                     (0x20000U)
#define OTFAD_SR_CTXIE1_SHIFT                    (17U)
/*! CTXIE1 - Context Integrity Error
 *  0b0..No key blob integrity error was detected for context "n".
 *  0b1..A key blob integrity error was detected in context "n".
 */
#define OTFAD_SR_CTXIE1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
#define OTFAD_SR_CTXIE2_MASK                     (0x40000U)
#define OTFAD_SR_CTXIE2_SHIFT                    (18U)
/*! CTXIE2 - Context Integrity Error
 *  0b0..No key blob integrity error was detected for context "n".
 *  0b1..A key blob integrity error was detected in context "n".
 */
#define OTFAD_SR_CTXIE2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
#define OTFAD_SR_CTXIE3_MASK                     (0x80000U)
#define OTFAD_SR_CTXIE3_SHIFT                    (19U)
/*! CTXIE3 - Context Integrity Error
 *  0b0..No key blob integrity error was detected for context "n".
 *  0b1..A key blob integrity error was detected in context "n".
 */
#define OTFAD_SR_CTXIE3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
#define OTFAD_SR_HRL_MASK                        (0xF000000U)
#define OTFAD_SR_HRL_SHIFT                       (24U)
/*! HRL - Hardware Revision Level
 */
#define OTFAD_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
#define OTFAD_SR_RRAM_MASK                       (0x10000000U)
#define OTFAD_SR_RRAM_SHIFT                      (28U)
/*! RRAM - Restricted Register Access Mode
 *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
 *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
 */
#define OTFAD_SR_RRAM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
#define OTFAD_SR_GEM_MASK                        (0x20000000U)
#define OTFAD_SR_GEM_SHIFT                       (29U)
/*! GEM - Global Enable Mode
 *  0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
 *  0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
 */
#define OTFAD_SR_GEM(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
#define OTFAD_SR_KBPE_MASK                       (0x40000000U)
#define OTFAD_SR_KBPE_SHIFT                      (30U)
/*! KBPE - Key Blob Processing Enable
 *  0b0..Key blob processing is not enabled.
 *  0b1..Key blob processing is enabled.
 */
#define OTFAD_SR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
#define OTFAD_SR_KBD_MASK                        (0x80000000U)
#define OTFAD_SR_KBD_SHIFT                       (31U)
/*! KBD - Key Blob Processing Done
 *  0b0..Key blob processing was not enabled, or is not complete.
 *  0b1..Key blob processing was enabled and is complete.
 */
#define OTFAD_SR_KBD(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
/*! @} */

/*! @name KEY - AES Key Word */
/*! @{ */
#define OTFAD_KEY_KEY_MASK                       (0xFFFFFFFFU)
#define OTFAD_KEY_KEY_SHIFT                      (0U)
/*! KEY - AES Key
 */
#define OTFAD_KEY_KEY(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
/*! @} */

/* The count of OTFAD_KEY */
#define OTFAD_KEY_COUNT                          (4U)

/* The count of OTFAD_KEY */
#define OTFAD_KEY_COUNT2                         (4U)

/*! @name CTR - AES Counter Word */
/*! @{ */
#define OTFAD_CTR_CTR_MASK                       (0xFFFFFFFFU)
#define OTFAD_CTR_CTR_SHIFT                      (0U)
/*! CTR - AES Counter
 */
#define OTFAD_CTR_CTR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
/*! @} */

/* The count of OTFAD_CTR */
#define OTFAD_CTR_COUNT                          (4U)

/* The count of OTFAD_CTR */
#define OTFAD_CTR_COUNT2                         (2U)

/*! @name RGD_W0 - AES Region Descriptor Word0 */
/*! @{ */
#define OTFAD_RGD_W0_SRTADDR_MASK                (0xFFFFFC00U)
#define OTFAD_RGD_W0_SRTADDR_SHIFT               (10U)
/*! SRTADDR - Start Address
 */
#define OTFAD_RGD_W0_SRTADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
/*! @} */

/* The count of OTFAD_RGD_W0 */
#define OTFAD_RGD_W0_COUNT                       (4U)

/*! @name RGD_W1 - AES Region Descriptor Word1 */
/*! @{ */
#define OTFAD_RGD_W1_VLD_MASK                    (0x1U)
#define OTFAD_RGD_W1_VLD_SHIFT                   (0U)
/*! VLD - Valid
 *  0b0..Context is invalid.
 *  0b1..Context is valid.
 */
#define OTFAD_RGD_W1_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
#define OTFAD_RGD_W1_ADE_MASK                    (0x2U)
#define OTFAD_RGD_W1_ADE_SHIFT                   (1U)
/*! ADE - AES Decryption Enable.
 *  0b0..Bypass the fetched data.
 *  0b1..Perform the CTR-AES128 mode decryption on the fetched data.
 */
#define OTFAD_RGD_W1_ADE(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
#define OTFAD_RGD_W1_RO_MASK                     (0x4U)
#define OTFAD_RGD_W1_RO_SHIFT                    (2U)
/*! RO - Read-Only
 *  0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
 *  0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
 */
#define OTFAD_RGD_W1_RO(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
#define OTFAD_RGD_W1_ENDADDR_MASK                (0xFFFFFC00U)
#define OTFAD_RGD_W1_ENDADDR_SHIFT               (10U)
/*! ENDADDR - End Address
 */
#define OTFAD_RGD_W1_ENDADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
/*! @} */

/* The count of OTFAD_RGD_W1 */
#define OTFAD_RGD_W1_COUNT                       (4U)


/*!
 * @}
 */ /* end of group OTFAD_Register_Masks */


/* OTFAD - Peripheral instance base addresses */
/** Peripheral OTFAD0 base address */
#define OTFAD0_BASE                              (0x40134000u)
/** Peripheral OTFAD0 base pointer */
#define OTFAD0                                   ((OTFAD_Type *)OTFAD0_BASE)
/** Array initializer of OTFAD peripheral base addresses */
#define OTFAD_BASE_ADDRS                         { OTFAD0_BASE }
/** Array initializer of OTFAD peripheral base pointers */
#define OTFAD_BASE_PTRS                          { OTFAD0 }

/*!
 * @}
 */ /* end of group OTFAD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PINT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
 * @{
 */

/** PINT - Register Layout Typedef */
typedef struct {
  __IO uint32_t ISEL;                              /**< Pin Interrupt Mode, offset: 0x0 */
  __IO uint32_t IENR;                              /**< Pin Interrupt Level or Rising Edge Interrupt Enable, offset: 0x4 */
  __O  uint32_t SIENR;                             /**< Pin Interrupt Level or Rising Edge Interrupt Set, offset: 0x8 */
  __IO uint32_t CIENR;                             /**< Pin Interrupt Level (Rising Edge Interrupt) Clear, offset: 0xC */
  __IO uint32_t IENF;                              /**< Pin Interrupt Active Level or Falling Edge Interrupt Enable, offset: 0x10 */
  __O  uint32_t SIENF;                             /**< Pin Interrupt Active Level or Falling Edge Interrupt Set, offset: 0x14 */
  __O  uint32_t CIENF;                             /**< Pin Interrupt Active Level or Falling Edge Interrupt Clear, offset: 0x18 */
  __IO uint32_t RISE;                              /**< Pin Interrupt Rising Edge, offset: 0x1C */
  __IO uint32_t FALL;                              /**< Pin Interrupt Falling Edge, offset: 0x20 */
  __IO uint32_t IST;                               /**< Pin Interrupt Status, offset: 0x24 */
  __IO uint32_t PMCTRL;                            /**< Pattern Match Interrupt Control, offset: 0x28 */
  __IO uint32_t PMSRC;                             /**< Pattern Match Interrupt Bit-Slice Source, offset: 0x2C */
  __IO uint32_t PMCFG;                             /**< Pattern Match Interrupt Bit Slice Configuration, offset: 0x30 */
} PINT_Type;

/* ----------------------------------------------------------------------------
   -- PINT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PINT_Register_Masks PINT Register Masks
 * @{
 */

/*! @name ISEL - Pin Interrupt Mode */
/*! @{ */
#define PINT_ISEL_PMODE_MASK                     (0xFFU)
#define PINT_ISEL_PMODE_SHIFT                    (0U)
/*! PMODE - Interrupt mode
 *  0b00000000..Edge-sensitive
 *  0b00000001..Level-sensitive
 */
#define PINT_ISEL_PMODE(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
/*! @} */

/*! @name IENR - Pin Interrupt Level or Rising Edge Interrupt Enable */
/*! @{ */
#define PINT_IENR_ENRL_MASK                      (0xFFU)
#define PINT_IENR_ENRL_SHIFT                     (0U)
/*! ENRL - Enable Interrupt
 *  0b00000000..Disable rising edge or level interrupt
 *  0b00000001..Enable rising edge or level interrupt
 */
#define PINT_IENR_ENRL(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
/*! @} */

/*! @name SIENR - Pin Interrupt Level or Rising Edge Interrupt Set */
/*! @{ */
#define PINT_SIENR_SETENRL_MASK                  (0xFFU)
#define PINT_SIENR_SETENRL_SHIFT                 (0U)
/*! SETENRL - Set bits in the IENR
 *  0b00000000..No operation
 *  0b00000001..Enable rising edge or level interrupt
 */
#define PINT_SIENR_SETENRL(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
/*! @} */

/*! @name CIENR - Pin Interrupt Level (Rising Edge Interrupt) Clear */
/*! @{ */
#define PINT_CIENR_CENRL_MASK                    (0xFFU)
#define PINT_CIENR_CENRL_SHIFT                   (0U)
/*! CENRL - Clear bits in the IENR
 *  0b00000000..No operation
 *  0b00000001..Disable rising edge or level interrupt
 */
#define PINT_CIENR_CENRL(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
/*! @} */

/*! @name IENF - Pin Interrupt Active Level or Falling Edge Interrupt Enable */
/*! @{ */
#define PINT_IENF_ENAF_MASK                      (0xFFU)
#define PINT_IENF_ENAF_SHIFT                     (0U)
/*! ENAF - Enable Interrupt
 *  0b00000000..Disable falling edge interrupt or set active interrupt level LOW
 *  0b00000001..Enable falling edge interrupt enabled or set active interrupt level HIGH
 */
#define PINT_IENF_ENAF(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
/*! @} */

/*! @name SIENF - Pin Interrupt Active Level or Falling Edge Interrupt Set */
/*! @{ */
#define PINT_SIENF_SETENAF_MASK                  (0xFFU)
#define PINT_SIENF_SETENAF_SHIFT                 (0U)
/*! SETENAF - Set bits in the IENF
 *  0b00000000..No operation
 *  0b00000001..Select HIGH-active interrupt or enable falling edge interrupt
 */
#define PINT_SIENF_SETENAF(x)                    (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
/*! @} */

/*! @name CIENF - Pin Interrupt Active Level or Falling Edge Interrupt Clear */
/*! @{ */
#define PINT_CIENF_CENAF_MASK                    (0xFFU)
#define PINT_CIENF_CENAF_SHIFT                   (0U)
/*! CENAF - Clear bits in the IENF
 *  0b00000000..No operation
 *  0b00000001..LOW-active interrupt selected or falling edge interrupt disabled
 */
#define PINT_CIENF_CENAF(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
/*! @} */

/*! @name RISE - Pin Interrupt Rising Edge */
/*! @{ */
#define PINT_RISE_RDET_MASK                      (0xFFU)
#define PINT_RISE_RDET_SHIFT                     (0U)
/*! RDET - Rising edge detect
 *  0b00000000..Read 0- No rising edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
 *  0b00000001..Read 1- a rising edge has been detected since Reset or the last time a one was written to this
 *              bit, Write 1- clear rising edge detection for this pin
 */
#define PINT_RISE_RDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
/*! @} */

/*! @name FALL - Pin Interrupt Falling Edge */
/*! @{ */
#define PINT_FALL_FDET_MASK                      (0xFFU)
#define PINT_FALL_FDET_SHIFT                     (0U)
/*! FDET - Falling edge detect
 *  0b00000000..Read 0- No falling edge has been detected on this pin since Reset or the last time a one was written to this bit, Write 0- no operation
 *  0b00000001..Read 1- a falling edge has been detected since Reset or the last time a one was written to this
 *              bit, Write 1- clear falling edge detection for this bit
 */
#define PINT_FALL_FDET(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
/*! @} */

/*! @name IST - Pin Interrupt Status */
/*! @{ */
#define PINT_IST_PSTAT_MASK                      (0xFFU)
#define PINT_IST_PSTAT_SHIFT                     (0U)
/*! PSTAT - Pin interrupt status
 *  0b00000000..Read 0- interrupt is not being requested for this pin, Write 0- no operation.
 *  0b00000001..Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear rising- and
 *              falling-edge detection for this pin, Write 1 (level-sensitive)- switch the active level for this pin
 *              (in the IENF register).
 */
#define PINT_IST_PSTAT(x)                        (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
/*! @} */

/*! @name PMCTRL - Pattern Match Interrupt Control */
/*! @{ */
#define PINT_PMCTRL_SEL_PMATCH_MASK              (0x1U)
#define PINT_PMCTRL_SEL_PMATCH_SHIFT             (0U)
/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function.
 *  0b0..Pin interrupt- interrupts are driven in response to the standard pin interrupt function.
 *  0b1..Pattern match- interrupts are driven in response to pattern matches.
 */
#define PINT_PMCTRL_SEL_PMATCH(x)                (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
#define PINT_PMCTRL_ENA_RXEV_MASK                (0x2U)
#define PINT_PMCTRL_ENA_RXEV_SHIFT               (1U)
/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolean expression evaluates to true.
 *  0b0..Disabled- RXEV output to the CPU is disabled.
 *  0b1..Enabled- RXEV output to the CPU is enabled.
 */
#define PINT_PMCTRL_ENA_RXEV(x)                  (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
#define PINT_PMCTRL_PMAT_MASK                    (0xFF000000U)
#define PINT_PMCTRL_PMAT_SHIFT                   (24U)
/*! PMAT - Pattern Matches
 *  0b00000001..The corresponding product term is matched by the current state of the appropriate inputs.
 */
#define PINT_PMCTRL_PMAT(x)                      (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
/*! @} */

/*! @name PMSRC - Pattern Match Interrupt Bit-Slice Source */
/*! @{ */
#define PINT_PMSRC_SRC0_MASK                     (0x700U)
#define PINT_PMSRC_SRC0_SHIFT                    (8U)
/*! SRC0 - Selects the input source for bit slice 0
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
#define PINT_PMSRC_SRC1_MASK                     (0x3800U)
#define PINT_PMSRC_SRC1_SHIFT                    (11U)
/*! SRC1 - Selects the input source for bit slice 1
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
#define PINT_PMSRC_SRC2_MASK                     (0x1C000U)
#define PINT_PMSRC_SRC2_SHIFT                    (14U)
/*! SRC2 - Selects the input source for bit slice 2
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
#define PINT_PMSRC_SRC3_MASK                     (0xE0000U)
#define PINT_PMSRC_SRC3_SHIFT                    (17U)
/*! SRC3 - Selects the input source for bit slice 3
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
#define PINT_PMSRC_SRC4_MASK                     (0x700000U)
#define PINT_PMSRC_SRC4_SHIFT                    (20U)
/*! SRC4 - Selects the input source for bit slice 4
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
#define PINT_PMSRC_SRC5_MASK                     (0x3800000U)
#define PINT_PMSRC_SRC5_SHIFT                    (23U)
/*! SRC5 - Selects the input source for bit slice 5
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
#define PINT_PMSRC_SRC6_MASK                     (0x1C000000U)
#define PINT_PMSRC_SRC6_SHIFT                    (26U)
/*! SRC6 - Selects the input source for bit slice 6
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
#define PINT_PMSRC_SRC7_MASK                     (0xE0000000U)
#define PINT_PMSRC_SRC7_SHIFT                    (29U)
/*! SRC7 - Selects the input source for bit slice 7
 *  0b000..Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slice n.
 *  0b001..Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slice n.
 *  0b010..Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slice n.
 *  0b011..Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slice n.
 *  0b100..Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slice n.
 *  0b101..Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slice n.
 *  0b110..Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slice n.
 *  0b111..Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slice n.
 */
#define PINT_PMSRC_SRC7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
/*! @} */

/*! @name PMCFG - Pattern Match Interrupt Bit Slice Configuration */
/*! @{ */
#define PINT_PMCFG_PROD_ENDPTS0_MASK             (0x1U)
#define PINT_PMCFG_PROD_ENDPTS0_SHIFT            (0U)
/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.
 *  0b0..No effect. Slice 0 is not an endpoint.
 *  0b1..Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS0(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
#define PINT_PMCFG_PROD_ENDPTS1_MASK             (0x2U)
#define PINT_PMCFG_PROD_ENDPTS1_SHIFT            (1U)
/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.
 *  0b0..No effect. Slice 1 is not an endpoint.
 *  0b1..Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS1(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
#define PINT_PMCFG_PROD_ENDPTS2_MASK             (0x4U)
#define PINT_PMCFG_PROD_ENDPTS2_SHIFT            (2U)
/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.
 *  0b0..No effect. Slice 2 is not an endpoint.
 *  0b1..Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS2(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
#define PINT_PMCFG_PROD_ENDPTS3_MASK             (0x8U)
#define PINT_PMCFG_PROD_ENDPTS3_SHIFT            (3U)
/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.
 *  0b0..No effect. Slice 3 is not an endpoint.
 *  0b1..Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS3(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
#define PINT_PMCFG_PROD_ENDPTS4_MASK             (0x10U)
#define PINT_PMCFG_PROD_ENDPTS4_SHIFT            (4U)
/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.
 *  0b0..No effect. Slice 4 is not an endpoint.
 *  0b1..Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS4(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
#define PINT_PMCFG_PROD_ENDPTS5_MASK             (0x20U)
#define PINT_PMCFG_PROD_ENDPTS5_SHIFT            (5U)
/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.
 *  0b0..No effect. Slice 5 is not an endpoint.
 *  0b1..Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS5(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
#define PINT_PMCFG_PROD_ENDPTS6_MASK             (0x40U)
#define PINT_PMCFG_PROD_ENDPTS6_SHIFT            (6U)
/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.
 *  0b0..No effect. Slice 6 is not an endpoint.
 *  0b1..Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.
 */
#define PINT_PMCFG_PROD_ENDPTS6(x)               (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
#define PINT_PMCFG_CFG0_MASK                     (0x700U)
#define PINT_PMCFG_CFG0_SHIFT                    (8U)
/*! CFG0 - Specifies the match contribution condition for bit slice 0.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG0(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
#define PINT_PMCFG_CFG1_MASK                     (0x3800U)
#define PINT_PMCFG_CFG1_SHIFT                    (11U)
/*! CFG1 - Specifies the match contribution condition for bit slice 1.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG1(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
#define PINT_PMCFG_CFG2_MASK                     (0x1C000U)
#define PINT_PMCFG_CFG2_SHIFT                    (14U)
/*! CFG2 - Specifies the match contribution condition for bit slice 2.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG2(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
#define PINT_PMCFG_CFG3_MASK                     (0xE0000U)
#define PINT_PMCFG_CFG3_SHIFT                    (17U)
/*! CFG3 - Specifies the match contribution condition for bit slice 3.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG3(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
#define PINT_PMCFG_CFG4_MASK                     (0x700000U)
#define PINT_PMCFG_CFG4_SHIFT                    (20U)
/*! CFG4 - Specifies the match contribution condition for bit slice 4.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG4(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
#define PINT_PMCFG_CFG5_MASK                     (0x3800000U)
#define PINT_PMCFG_CFG5_SHIFT                    (23U)
/*! CFG5 - Specifies the match contribution condition for bit slice 5.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG5(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
#define PINT_PMCFG_CFG6_MASK                     (0x1C000000U)
#define PINT_PMCFG_CFG6_SHIFT                    (26U)
/*! CFG6 - Specifies the match contribution condition for bit slice 6.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG6(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
#define PINT_PMCFG_CFG7_MASK                     (0xE0000000U)
#define PINT_PMCFG_CFG7_SHIFT                    (29U)
/*! CFG7 - Specifies the match contribution condition for bit slice 7.
 *  0b000..Constant HIGH
 *  0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last
 *         time the edge detection for this bit slice was cleared. This match condition is only cleared when the
 *         PMCFG or the PMSRC registers are written to.
 *  0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input
 *         has occurred since the last time the edge detection for this bit slice was cleared. This match condition
 *         is only cleared when the PMCFG or the PMSRC registers are written to.
 *  0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.
 *  0b101..Low level. Match occurs when there is a low level on the specified input.
 *  0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).
 *  0b111..Event. Non-sticky rising or falling edge. Match occurs on an event when either a rising or falling edge
 *         is first detected on the specified input (this is a non-sticky version of value 0x3). This bit is
 *         cleared after 1 clock cycle.
 */
#define PINT_PMCFG_CFG7(x)                       (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PINT_Register_Masks */


/* PINT - Peripheral instance base addresses */
/** Peripheral PINT base address */
#define PINT_BASE                                (0x40025000u)
/** Peripheral PINT base pointer */
#define PINT                                     ((PINT_Type *)PINT_BASE)
/** Array initializer of PINT peripheral base addresses */
#define PINT_BASE_ADDRS                          { PINT_BASE }
/** Array initializer of PINT peripheral base pointers */
#define PINT_BASE_PTRS                           { PINT }
/** Interrupt vectors for the PINT peripheral type */
#define PINT_IRQS                                { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }

/*!
 * @}
 */ /* end of group PINT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- POWERQUAD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer
 * @{
 */

/** POWERQUAD - Register Layout Typedef */
typedef struct {
  __IO uint32_t OUTBASE;                           /**< Output Base, offset: 0x0 */
  __IO uint32_t OUTFORMAT;                         /**< Output Format, offset: 0x4 */
  __IO uint32_t TMPBASE;                           /**< Temporary Base, offset: 0x8 */
  __IO uint32_t TMPFORMAT;                         /**< Temporary Format, offset: 0xC */
  __IO uint32_t INABASE;                           /**< Input A Base, offset: 0x10 */
  __IO uint32_t INAFORMAT;                         /**< Input A Format, offset: 0x14 */
  __IO uint32_t INBBASE;                           /**< Input B Base, offset: 0x18 */
  __IO uint32_t INBFORMAT;                         /**< Input B Format, offset: 0x1C */
       uint8_t RESERVED_0[224];
  __IO uint32_t CONTROL;                           /**< Control, offset: 0x100 */
  __IO uint32_t LENGTH;                            /**< Length, offset: 0x104 */
  __IO uint32_t CPPRE;                             /**< Coprocessor Pre-scale, offset: 0x108 */
  __IO uint32_t MISC;                              /**< Miscellaneous, offset: 0x10C */
  __IO uint32_t CURSORY;                           /**< Cursory, offset: 0x110 */
       uint8_t RESERVED_1[108];
  __IO uint32_t CORDIC_X;                          /**< Cordic input X, offset: 0x180 */
  __IO uint32_t CORDIC_Y;                          /**< Cordic Input Y, offset: 0x184 */
  __IO uint32_t CORDIC_Z;                          /**< Cordic Input Z, offset: 0x188 */
  __IO uint32_t ERRSTAT;                           /**< Error Status, offset: 0x18C */
  __IO uint32_t INTREN;                            /**< Interrupt Enable, offset: 0x190 */
  __IO uint32_t EVENTEN;                           /**< Event Enable, offset: 0x194 */
  __IO uint32_t INTRSTAT;                          /**< Interrupt Status, offset: 0x198 */
       uint8_t RESERVED_2[100];
  __IO uint32_t GPREG[16];                         /**< General Purpose Register Bank n, array offset: 0x200, array step: 0x4 */
  __IO uint32_t COMPREG[8];                        /**< Compute Register Bank n, array offset: 0x240, array step: 0x4 */
} POWERQUAD_Type;

/* ----------------------------------------------------------------------------
   -- POWERQUAD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks
 * @{
 */

/*! @name OUTBASE - Output Base */
/*! @{ */
#define POWERQUAD_OUTBASE_OUTBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_OUTBASE_OUTBASE_SHIFT          (0U)
/*! OUTBASE - Base address register for the output region
 */
#define POWERQUAD_OUTBASE_OUTBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)
/*! @} */

/*! @name OUTFORMAT - Output Format */
/*! @{ */
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK   (0x3U)
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT  (0U)
/*! OUT_FORMATINT - Output Internal Format
 */
#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT  (4U)
/*! OUT_FORMATEXT - Output External Format
 */
#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)
#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK      (0xFF00U)
#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT     (8U)
/*! OUT_SCALER - Output Scaler Value
 */
#define POWERQUAD_OUTFORMAT_OUT_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)
/*! @} */

/*! @name TMPBASE - Temporary Base */
/*! @{ */
#define POWERQUAD_TMPBASE_TMPBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_TMPBASE_TMPBASE_SHIFT          (0U)
/*! TMPBASE - Base address register for the temporary region
 */
#define POWERQUAD_TMPBASE_TMPBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)
/*! @} */

/*! @name TMPFORMAT - Temporary Format */
/*! @{ */
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK   (0x3U)
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT  (0U)
/*! TMP_FORMATINT - Temporary Internal Format
 */
#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT  (4U)
/*! TMP_FORMATEXT - Temporary External Format
 */
#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)
#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK      (0xFF00U)
#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT     (8U)
/*! TMP_SCALER - Temporary Scaler Value
 */
#define POWERQUAD_TMPFORMAT_TMP_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)
/*! @} */

/*! @name INABASE - Input A Base */
/*! @{ */
#define POWERQUAD_INABASE_INABASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_INABASE_INABASE_SHIFT          (0U)
/*! INABASE - Input A Base
 */
#define POWERQUAD_INABASE_INABASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)
/*! @} */

/*! @name INAFORMAT - Input A Format */
/*! @{ */
#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK   (0x3U)
#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT  (0U)
/*! INA_FORMATINT - Input A Internal Format
 */
#define POWERQUAD_INAFORMAT_INA_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)
#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT  (4U)
/*! INA_FORMATEXT - Input A External Format
 */
#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)
#define POWERQUAD_INAFORMAT_INA_SCALER_MASK      (0xFF00U)
#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT     (8U)
/*! INA_SCALER - Input A Scaler Value
 */
#define POWERQUAD_INAFORMAT_INA_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)
/*! @} */

/*! @name INBBASE - Input B Base */
/*! @{ */
#define POWERQUAD_INBBASE_INBBASE_MASK           (0xFFFFFFFFU)
#define POWERQUAD_INBBASE_INBBASE_SHIFT          (0U)
/*! INBBASE - Input B Base
 */
#define POWERQUAD_INBBASE_INBBASE(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)
/*! @} */

/*! @name INBFORMAT - Input B Format */
/*! @{ */
#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK   (0x3U)
#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT  (0U)
/*! INB_FORMATINT - Input B Internal Format
 */
#define POWERQUAD_INBFORMAT_INB_FORMATINT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)
#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK   (0x30U)
#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT  (4U)
/*! INB_FORMATEXT - Input B External Format
 */
#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x)     (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)
#define POWERQUAD_INBFORMAT_INB_SCALER_MASK      (0xFF00U)
#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT     (8U)
/*! INB_SCALER - Input B Scaler Value
 */
#define POWERQUAD_INBFORMAT_INB_SCALER(x)        (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)
/*! @} */

/*! @name CONTROL - Control */
/*! @{ */
#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK     (0xFU)
#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT    (0U)
/*! DECODE_OPCODE - Decode Opcode
 */
#define POWERQUAD_CONTROL_DECODE_OPCODE(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)
#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK    (0xF0U)
#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT   (4U)
/*! DECODE_MACHINE - Decode Machine
 */
#define POWERQUAD_CONTROL_DECODE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)
#define POWERQUAD_CONTROL_INST_BUSY_MASK         (0x80000000U)
#define POWERQUAD_CONTROL_INST_BUSY_SHIFT        (31U)
/*! INST_BUSY - Instruction Busy
 */
#define POWERQUAD_CONTROL_INST_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)
/*! @} */

/*! @name LENGTH - Length */
/*! @{ */
#define POWERQUAD_LENGTH_INST_LENGTH_MASK        (0xFFFFFFFFU)
#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT       (0U)
/*! INST_LENGTH - Instruction Length
 */
#define POWERQUAD_LENGTH_INST_LENGTH(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)
/*! @} */

/*! @name CPPRE - Coprocessor Pre-scale */
/*! @{ */
#define POWERQUAD_CPPRE_CPPRE_IN_MASK            (0xFFU)
#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT           (0U)
/*! CPPRE_IN - Input
 */
#define POWERQUAD_CPPRE_CPPRE_IN(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)
#define POWERQUAD_CPPRE_CPPRE_OUT_MASK           (0xFF00U)
#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT          (8U)
/*! CPPRE_OUT - Output
 */
#define POWERQUAD_CPPRE_CPPRE_OUT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)
#define POWERQUAD_CPPRE_CPPRE_SAT_MASK           (0x10000U)
#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT          (16U)
/*! CPPRE_SAT - Saturation
 *  0b0..No saturation
 *  0b1..Forces sub-32 bit saturation
 */
#define POWERQUAD_CPPRE_CPPRE_SAT(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)
#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK          (0x20000U)
#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT         (17U)
/*! CPPRE_SAT8 - Saturation 8
 *  0b0..8 bits
 *  0b1..16 bits
 */
#define POWERQUAD_CPPRE_CPPRE_SAT8(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)
/*! @} */

/*! @name MISC - Miscellaneous */
/*! @{ */
#define POWERQUAD_MISC_INST_MISC_MASK            (0xFFFFFFFFU)
#define POWERQUAD_MISC_INST_MISC_SHIFT           (0U)
/*! INST_MISC - For Matrix : Used for scaling factor
 */
#define POWERQUAD_MISC_INST_MISC(x)              (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)
/*! @} */

/*! @name CURSORY - Cursory */
/*! @{ */
#define POWERQUAD_CURSORY_CURSORY_MASK           (0x1U)
#define POWERQUAD_CURSORY_CURSORY_SHIFT          (0U)
/*! CURSORY - Cursory Mode
 *  0b0..Disable Cursory mode
 *  0b1..Enable Cursory Mode
 */
#define POWERQUAD_CURSORY_CURSORY(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)
/*! @} */

/*! @name CORDIC_X - Cordic input X */
/*! @{ */
#define POWERQUAD_CORDIC_X_CORDIC_X_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT        (0U)
/*! CORDIC_X - Cordic Input x
 */
#define POWERQUAD_CORDIC_X_CORDIC_X(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)
/*! @} */

/*! @name CORDIC_Y - Cordic Input Y */
/*! @{ */
#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT        (0U)
/*! CORDIC_Y - Cordic Input y
 */
#define POWERQUAD_CORDIC_Y_CORDIC_Y(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)
/*! @} */

/*! @name CORDIC_Z - Cordic Input Z */
/*! @{ */
#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK         (0xFFFFFFFFU)
#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT        (0U)
/*! CORDIC_Z - Cordic Input z
 */
#define POWERQUAD_CORDIC_Z_CORDIC_Z(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)
/*! @} */

/*! @name ERRSTAT - Error Status */
/*! @{ */
#define POWERQUAD_ERRSTAT_OVERFLOW_MASK          (0x1U)
#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT         (0U)
/*! OVERFLOW - Floating Point Overflow
 *  0b0..No Error
 *  0b1..Error on Floating Point Overflow
 */
#define POWERQUAD_ERRSTAT_OVERFLOW(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)
#define POWERQUAD_ERRSTAT_NAN_MASK               (0x2U)
#define POWERQUAD_ERRSTAT_NAN_SHIFT              (1U)
/*! NAN - Floating Point NaN
 *  0b0..No Error
 *  0b1..Error on Floating Point NaN
 */
#define POWERQUAD_ERRSTAT_NAN(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK     (0x4U)
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT    (2U)
/*! FIXEDOVERFLOW - Fixed Point Overflow
 *  0b0..No Error
 *  0b1..Error on Fixed Point Overflow
 */
#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x)       (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)
#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK         (0x8U)
#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT        (3U)
/*! UNDERFLOW - Underflow
 *  0b0..No Error
 *  0b1..Error on Underflow
 */
#define POWERQUAD_ERRSTAT_UNDERFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)
#define POWERQUAD_ERRSTAT_BUSERROR_MASK          (0x10U)
#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT         (4U)
/*! BUSERROR - Bus Error
 *  0b0..No Error
 *  0b1..Error on Bus
 */
#define POWERQUAD_ERRSTAT_BUSERROR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)
/*! @} */

/*! @name INTREN - Interrupt Enable */
/*! @{ */
#define POWERQUAD_INTREN_INTR_OFLOW_MASK         (0x1U)
#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT        (0U)
/*! INTR_OFLOW - Interrupt Floating Point Overflow
 *  0b0..Disable
 *  0b1..Enable interrupt on floating point overflow
 */
#define POWERQUAD_INTREN_INTR_OFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)
#define POWERQUAD_INTREN_INTR_NAN_MASK           (0x2U)
#define POWERQUAD_INTREN_INTR_NAN_SHIFT          (1U)
/*! INTR_NAN - Interrupt Floating Point NaN
 *  0b0..Disable
 *  0b1..Enable interrupt on floating point NaN
 */
#define POWERQUAD_INTREN_INTR_NAN(x)             (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)
#define POWERQUAD_INTREN_INTR_FIXED_MASK         (0x4U)
#define POWERQUAD_INTREN_INTR_FIXED_SHIFT        (2U)
/*! INTR_FIXED - Interrupt on Fixed Point Overflow
 *  0b0..Disable
 *  0b1..Enable interrupt on fixed point overflow
 */
#define POWERQUAD_INTREN_INTR_FIXED(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)
#define POWERQUAD_INTREN_INTR_UFLOW_MASK         (0x8U)
#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT        (3U)
/*! INTR_UFLOW - Interrupt on Subnormal Truncation
 *  0b0..Disable
 *  0b1..Enable interrupt on subnormal truncation
 */
#define POWERQUAD_INTREN_INTR_UFLOW(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)
#define POWERQUAD_INTREN_INTR_BERR_MASK          (0x10U)
#define POWERQUAD_INTREN_INTR_BERR_SHIFT         (4U)
/*! INTR_BERR - Interrupt on AHBM Bus Error
 *  0b0..Disable
 *  0b1..Enable interrupt on AHBM Bus Error
 */
#define POWERQUAD_INTREN_INTR_BERR(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)
#define POWERQUAD_INTREN_INTR_COMP_MASK          (0x80U)
#define POWERQUAD_INTREN_INTR_COMP_SHIFT         (7U)
/*! INTR_COMP - Interrupt on Instruction Completion
 *  0b0..Disable
 *  0b1..Enable interrupt on instruction completion
 */
#define POWERQUAD_INTREN_INTR_COMP(x)            (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)
/*! @} */

/*! @name EVENTEN - Event Enable */
/*! @{ */
#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK       (0x1U)
#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT      (0U)
/*! EVENT_OFLOW - Event Trigger on Floating Point Overflow
 *  0b0..Disable
 *  0b1..Enable event trigger on Floating point overflow
 */
#define POWERQUAD_EVENTEN_EVENT_OFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)
#define POWERQUAD_EVENTEN_EVENT_NAN_MASK         (0x2U)
#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT        (1U)
/*! EVENT_NAN - Event Trigger on Floating Point NaN
 *  0b0..Disable
 *  0b1..Enable event trigger on floating point NaN
 */
#define POWERQUAD_EVENTEN_EVENT_NAN(x)           (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)
#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK       (0x4U)
#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT      (2U)
/*! EVENT_FIXED - Event Trigger on Fixed Point Overflow
 *  0b0..Disable
 *  0b1..Enable event trigger on fixed point overflow
 */
#define POWERQUAD_EVENTEN_EVENT_FIXED(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)
#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK       (0x8U)
#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT      (3U)
/*! EVENT_UFLOW - Event Trigger on Subnormal Truncation
 *  0b0..Disable
 *  0b1..Enable event trigger on subnormal truncation
 */
#define POWERQUAD_EVENTEN_EVENT_UFLOW(x)         (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)
#define POWERQUAD_EVENTEN_EVENT_BERR_MASK        (0x10U)
#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT       (4U)
/*! EVENT_BERR - Event Trigger on AHBM Bus Error
 *  0b0..Disable
 *  0b1..Enable event trigger on AHBM bus error
 */
#define POWERQUAD_EVENTEN_EVENT_BERR(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)
#define POWERQUAD_EVENTEN_EVENT_COMP_MASK        (0x80U)
#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT       (7U)
/*! EVENT_COMP - Event Trigger on Instruction Completion
 *  0b0..Disable
 *  0b1..Enable event trigger on instruction completion
 */
#define POWERQUAD_EVENTEN_EVENT_COMP(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)
/*! @} */

/*! @name INTRSTAT - Interrupt Status */
/*! @{ */
#define POWERQUAD_INTRSTAT_INTR_STAT_MASK        (0x1U)
#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT       (0U)
/*! INTR_STAT - Interrupt Status
 *  0b0..No new interrupt
 *  0b1..Interrupt captured
 */
#define POWERQUAD_INTRSTAT_INTR_STAT(x)          (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)
/*! @} */

/*! @name GPREG - General Purpose Register Bank n */
/*! @{ */
#define POWERQUAD_GPREG_GPREG_MASK               (0xFFFFFFFFU)
#define POWERQUAD_GPREG_GPREG_SHIFT              (0U)
/*! GPREG - General Purpose Register Bank
 */
#define POWERQUAD_GPREG_GPREG(x)                 (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)
/*! @} */

/* The count of POWERQUAD_GPREG */
#define POWERQUAD_GPREG_COUNT                    (16U)

/*! @name COMPREGS_COMPREG - Compute Register Bank n */
/*! @{ */
#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK  (0xFFFFFFFFU)
#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)
/*! COMPREG - Compute Register Bank
 */
#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x)    (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)
/*! @} */

/* The count of POWERQUAD_COMPREGS_COMPREG */
#define POWERQUAD_COMPREGS_COMPREG_COUNT         (8U)


/*!
 * @}
 */ /* end of group POWERQUAD_Register_Masks */


/* POWERQUAD - Peripheral instance base addresses */
/** Peripheral POWERQUAD base address */
#define POWERQUAD_BASE                           (0x40200000u)
/** Peripheral POWERQUAD base pointer */
#define POWERQUAD                                ((POWERQUAD_Type *)POWERQUAD_BASE)
/** Array initializer of POWERQUAD peripheral base addresses */
#define POWERQUAD_BASE_ADDRS                     { POWERQUAD_BASE }
/** Array initializer of POWERQUAD peripheral base pointers */
#define POWERQUAD_BASE_PTRS                      { POWERQUAD }

/*!
 * @}
 */ /* end of group POWERQUAD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- PUF Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
 * @{
 */

/** PUF - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< PUF Control, offset: 0x0 */
  __IO uint32_t KEYINDEX;                          /**< PUF Key Index, offset: 0x4 */
  __IO uint32_t KEYSIZE;                           /**< PUF Key Size, offset: 0x8 */
       uint8_t RESERVED_0[20];
  __I  uint32_t STAT;                              /**< PUF Status, offset: 0x20 */
       uint8_t RESERVED_1[4];
  __I  uint32_t ALLOW;                             /**< PUF Allow, offset: 0x28 */
       uint8_t RESERVED_2[20];
  __O  uint32_t KEYINPUT;                          /**< PUF Key Input, offset: 0x40 */
  __O  uint32_t CODEINPUT;                         /**< PUF Code Input, offset: 0x44 */
  __I  uint32_t CODEOUTPUT;                        /**< PUF Code Output, offset: 0x48 */
       uint8_t RESERVED_3[20];
  __I  uint32_t KEYOUTINDEX;                       /**< PUF Key Output Index, offset: 0x60 */
  __I  uint32_t KEYOUTPUT;                         /**< PUF Key Output, offset: 0x64 */
       uint8_t RESERVED_4[116];
  __IO uint32_t IFSTAT;                            /**< PUF Interface Status and Clear, offset: 0xDC */
       uint8_t RESERVED_5[28];
  __I  uint32_t VERSION;                           /**< PUF Version, offset: 0xFC */
  __IO uint32_t INTEN;                             /**< PUF Interrupt Enable, offset: 0x100 */
  __IO uint32_t INTSTAT;                           /**< PUF Interrupt Status, offset: 0x104 */
  __IO uint32_t PWRCTRL;                           /**< PUF Power Control, offset: 0x108 */
  __IO uint32_t CFG;                               /**< PUF Configuration, offset: 0x10C */
       uint8_t RESERVED_6[240];
  __IO uint32_t KEYLOCK;                           /**< Key Lock, offset: 0x200 */
  __IO uint32_t KEYENABLE;                         /**< Key Enable, offset: 0x204 */
  __O  uint32_t KEYRESET;                          /**< Key Reset, offset: 0x208 */
  __IO uint32_t IDXBLK_L;                          /**< Index Block Low, offset: 0x20C */
  __IO uint32_t IDXBLK_H_DP;                       /**< Index Block High Duplicate, offset: 0x210 */
  __O  uint32_t KEYMASK[4];                        /**< Key Mask 0..Key Mask 3, array offset: 0x214, array step: 0x4 */
       uint8_t RESERVED_7[48];
  __IO uint32_t IDXBLK_H;                          /**< Index Block High, offset: 0x254 */
  __IO uint32_t IDXBLK_L_DP;                       /**< Index Block Low Duplicate, offset: 0x258 */
  __I  uint32_t SHIFT_STATUS;                      /**< Shift Status, offset: 0x25C */
} PUF_Type;

/* ----------------------------------------------------------------------------
   -- PUF Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup PUF_Register_Masks PUF Register Masks
 * @{
 */

/*! @name CTRL - PUF Control */
/*! @{ */
#define PUF_CTRL_ZEROIZE_MASK                    (0x1U)
#define PUF_CTRL_ZEROIZE_SHIFT                   (0U)
#define PUF_CTRL_ZEROIZE(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
#define PUF_CTRL_ENROLL_MASK                     (0x2U)
#define PUF_CTRL_ENROLL_SHIFT                    (1U)
#define PUF_CTRL_ENROLL(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
#define PUF_CTRL_START_MASK                      (0x4U)
#define PUF_CTRL_START_SHIFT                     (2U)
#define PUF_CTRL_START(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
#define PUF_CTRL_GENERATEKEY_MASK                (0x8U)
#define PUF_CTRL_GENERATEKEY_SHIFT               (3U)
#define PUF_CTRL_GENERATEKEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
#define PUF_CTRL_SETKEY_MASK                     (0x10U)
#define PUF_CTRL_SETKEY_SHIFT                    (4U)
#define PUF_CTRL_SETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
#define PUF_CTRL_GETKEY_MASK                     (0x40U)
#define PUF_CTRL_GETKEY_SHIFT                    (6U)
#define PUF_CTRL_GETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
/*! @} */

/*! @name KEYINDEX - PUF Key Index */
/*! @{ */
#define PUF_KEYINDEX_KEYIDX_MASK                 (0xFU)
#define PUF_KEYINDEX_KEYIDX_SHIFT                (0U)
#define PUF_KEYINDEX_KEYIDX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
/*! @} */

/*! @name KEYSIZE - PUF Key Size */
/*! @{ */
#define PUF_KEYSIZE_KEYSIZE_MASK                 (0x3FU)
#define PUF_KEYSIZE_KEYSIZE_SHIFT                (0U)
/*! KEYSIZE - Key Size for Set Key operations
 */
#define PUF_KEYSIZE_KEYSIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
/*! @} */

/*! @name STAT - PUF Status */
/*! @{ */
#define PUF_STAT_BUSY_MASK                       (0x1U)
#define PUF_STAT_BUSY_SHIFT                      (0U)
/*! BUSY - Busy
 */
#define PUF_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
#define PUF_STAT_SUCCESS_MASK                    (0x2U)
#define PUF_STAT_SUCCESS_SHIFT                   (1U)
/*! SUCCESS - Success
 */
#define PUF_STAT_SUCCESS(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
#define PUF_STAT_ERROR_MASK                      (0x4U)
#define PUF_STAT_ERROR_SHIFT                     (2U)
/*! ERROR - Error
 */
#define PUF_STAT_ERROR(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
#define PUF_STAT_KEYINREQ_MASK                   (0x10U)
#define PUF_STAT_KEYINREQ_SHIFT                  (4U)
/*! KEYINREQ - Key In Request
 */
#define PUF_STAT_KEYINREQ(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
#define PUF_STAT_KEYOUTAVAIL_MASK                (0x20U)
#define PUF_STAT_KEYOUTAVAIL_SHIFT               (5U)
/*! KEYOUTAVAIL - Key Out Available
 */
#define PUF_STAT_KEYOUTAVAIL(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
#define PUF_STAT_CODEINREQ_MASK                  (0x40U)
#define PUF_STAT_CODEINREQ_SHIFT                 (6U)
/*! CODEINREQ - Code In Request
 */
#define PUF_STAT_CODEINREQ(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
#define PUF_STAT_CODEOUTAVAIL_MASK               (0x80U)
#define PUF_STAT_CODEOUTAVAIL_SHIFT              (7U)
/*! CODEOUTAVAIL - Code Out Available
 */
#define PUF_STAT_CODEOUTAVAIL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
/*! @} */

/*! @name ALLOW - PUF Allow */
/*! @{ */
#define PUF_ALLOW_ALLOWENROLL_MASK               (0x1U)
#define PUF_ALLOW_ALLOWENROLL_SHIFT              (0U)
/*! ALLOWENROLL - Allow Enroll
 */
#define PUF_ALLOW_ALLOWENROLL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
#define PUF_ALLOW_ALLOWSTART_MASK                (0x2U)
#define PUF_ALLOW_ALLOWSTART_SHIFT               (1U)
/*! ALLOWSTART - Allow Start
 */
#define PUF_ALLOW_ALLOWSTART(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
#define PUF_ALLOW_ALLOWSETKEY_MASK               (0x4U)
#define PUF_ALLOW_ALLOWSETKEY_SHIFT              (2U)
/*! ALLOWSETKEY - Allow Set Key
 */
#define PUF_ALLOW_ALLOWSETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
#define PUF_ALLOW_ALLOWGETKEY_MASK               (0x8U)
#define PUF_ALLOW_ALLOWGETKEY_SHIFT              (3U)
/*! ALLOWGETKEY - Allow Get Key
 */
#define PUF_ALLOW_ALLOWGETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
/*! @} */

/*! @name KEYINPUT - PUF Key Input */
/*! @{ */
#define PUF_KEYINPUT_KEYIN_MASK                  (0xFFFFFFFFU)
#define PUF_KEYINPUT_KEYIN_SHIFT                 (0U)
/*! KEYIN - Key Input Data
 */
#define PUF_KEYINPUT_KEYIN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
/*! @} */

/*! @name CODEINPUT - PUF Code Input */
/*! @{ */
#define PUF_CODEINPUT_CODEIN_MASK                (0xFFFFFFFFU)
#define PUF_CODEINPUT_CODEIN_SHIFT               (0U)
/*! CODEIN - AC/KC Input Data
 */
#define PUF_CODEINPUT_CODEIN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
/*! @} */

/*! @name CODEOUTPUT - PUF Code Output */
/*! @{ */
#define PUF_CODEOUTPUT_CODEOUT_MASK              (0xFFFFFFFFU)
#define PUF_CODEOUTPUT_CODEOUT_SHIFT             (0U)
/*! CODEOUT - AC/KC Output Data
 */
#define PUF_CODEOUTPUT_CODEOUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
/*! @} */

/*! @name KEYOUTINDEX - PUF Key Output Index */
/*! @{ */
#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK           (0xFU)
#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT          (0U)
/*! KEYOUTIDX - Key Output Index
 */
#define PUF_KEYOUTINDEX_KEYOUTIDX(x)             (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
/*! @} */

/*! @name KEYOUTPUT - PUF Key Output */
/*! @{ */
#define PUF_KEYOUTPUT_KEYOUT_MASK                (0xFFFFFFFFU)
#define PUF_KEYOUTPUT_KEYOUT_SHIFT               (0U)
/*! KEYOUT - Key Output Data
 */
#define PUF_KEYOUTPUT_KEYOUT(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
/*! @} */

/*! @name IFSTAT - PUF Interface Status and Clear */
/*! @{ */
#define PUF_IFSTAT_ERROR_MASK                    (0x1U)
#define PUF_IFSTAT_ERROR_SHIFT                   (0U)
/*! ERROR - Error
 */
#define PUF_IFSTAT_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
/*! @} */

/*! @name VERSION - PUF Version */
/*! @{ */
#define PUF_VERSION_VERSION_MASK                 (0xFFFFFFFFU)
#define PUF_VERSION_VERSION_SHIFT                (0U)
/*! VERSION - Version
 */
#define PUF_VERSION_VERSION(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
/*! @} */

/*! @name INTEN - PUF Interrupt Enable */
/*! @{ */
#define PUF_INTEN_READYEN_MASK                   (0x1U)
#define PUF_INTEN_READYEN_SHIFT                  (0U)
/*! READYEN - Enable corresponding interrupt in STAT, which indicates that the initialization or a operation is completed.
 */
#define PUF_INTEN_READYEN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
#define PUF_INTEN_SUCCESEN_MASK                  (0x2U)
#define PUF_INTEN_SUCCESEN_SHIFT                 (1U)
/*! SUCCESEN - Enable corresponding interrupt in STAT, which indicates last operation was successful.
 */
#define PUF_INTEN_SUCCESEN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK)
#define PUF_INTEN_ERROREN_MASK                   (0x4U)
#define PUF_INTEN_ERROREN_SHIFT                  (2U)
/*! ERROREN - Enable corresponding interrupt in STAT, which indicates that PUF is in the error state
 *    and no operations can be performed.
 */
#define PUF_INTEN_ERROREN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
#define PUF_INTEN_KEYINREQEN_MASK                (0x10U)
#define PUF_INTEN_KEYINREQEN_SHIFT               (4U)
/*! KEYINREQEN - Enable corresponding interrupt in STAT, which is request for next part of key.
 */
#define PUF_INTEN_KEYINREQEN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
#define PUF_INTEN_KEYOUTAVAILEN_MASK             (0x20U)
#define PUF_INTEN_KEYOUTAVAILEN_SHIFT            (5U)
/*! KEYOUTAVAILEN - Enable corresponding interrupt in STAT, which is next part of key is available.
 */
#define PUF_INTEN_KEYOUTAVAILEN(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
#define PUF_INTEN_CODEINREQEN_MASK               (0x40U)
#define PUF_INTEN_CODEINREQEN_SHIFT              (6U)
/*! CODEINREQEN - Enable corresponding interrupt in STAT, which is request for next part of AC/KC.
 */
#define PUF_INTEN_CODEINREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
#define PUF_INTEN_CODEOUTAVAILEN_MASK            (0x80U)
#define PUF_INTEN_CODEOUTAVAILEN_SHIFT           (7U)
/*! CODEOUTAVAILEN - Enable corresponding interrupt in STAT, which is next part of AC/KC is available.
 */
#define PUF_INTEN_CODEOUTAVAILEN(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
/*! @} */

/*! @name INTSTAT - PUF Interrupt Status */
/*! @{ */
#define PUF_INTSTAT_READY_MASK                   (0x1U)
#define PUF_INTSTAT_READY_SHIFT                  (0U)
/*! READY - Ready
 */
#define PUF_INTSTAT_READY(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
#define PUF_INTSTAT_SUCCESS_MASK                 (0x2U)
#define PUF_INTSTAT_SUCCESS_SHIFT                (1U)
/*! SUCCESS - Success
 */
#define PUF_INTSTAT_SUCCESS(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
#define PUF_INTSTAT_ERROR_MASK                   (0x4U)
#define PUF_INTSTAT_ERROR_SHIFT                  (2U)
/*! ERROR - Error
 */
#define PUF_INTSTAT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
#define PUF_INTSTAT_KEYINREQ_MASK                (0x10U)
#define PUF_INTSTAT_KEYINREQ_SHIFT               (4U)
/*! KEYINREQ - Key In Request
 */
#define PUF_INTSTAT_KEYINREQ(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
#define PUF_INTSTAT_KEYOUTAVAIL_MASK             (0x20U)
#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT            (5U)
/*! KEYOUTAVAIL - Key Out Available
 */
#define PUF_INTSTAT_KEYOUTAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
#define PUF_INTSTAT_CODEINREQ_MASK               (0x40U)
#define PUF_INTSTAT_CODEINREQ_SHIFT              (6U)
/*! CODEINREQ - Code In Request
 */
#define PUF_INTSTAT_CODEINREQ(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
#define PUF_INTSTAT_CODEOUTAVAIL_MASK            (0x80U)
#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT           (7U)
/*! CODEOUTAVAIL - Code Out Available
 */
#define PUF_INTSTAT_CODEOUTAVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
/*! @} */

/*! @name PWRCTRL - PUF Power Control */
/*! @{ */
#define PUF_PWRCTRL_RAMON_MASK                   (0x1U)
#define PUF_PWRCTRL_RAMON_SHIFT                  (0U)
/*! RAMON - RAM Power On
 *  0b0..Power Off
 *  0b1..Power On
 */
#define PUF_PWRCTRL_RAMON(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK)
#define PUF_PWRCTRL_RAMSTAT_MASK                 (0x2U)
#define PUF_PWRCTRL_RAMSTAT_SHIFT                (1U)
/*! RAMSTAT - RAM Status
 *  0b0..Cleared when RAMON = 0.
 *  0b1..RAMSTAT is set to 1 when PUF RAM completes initialization after RAMON bit is set to 1.
 */
#define PUF_PWRCTRL_RAMSTAT(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK)
/*! @} */

/*! @name CFG - PUF Configuration */
/*! @{ */
#define PUF_CFG_BLOCKENROLL_SETKEY_MASK          (0x1U)
#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT         (0U)
/*! BLOCKENROLL_SETKEY - Block Enroll and Set Key Operation
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define PUF_CFG_BLOCKENROLL_SETKEY(x)            (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK)
#define PUF_CFG_BLOCKKEYOUTPUT_MASK              (0x2U)
#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT             (1U)
/*! BLOCKKEYOUTPUT - Block Key Output Data
 *  0b0..Disabled. BLOCKKEYOUTPUT is cleared on reset.
 *  0b1..Enabled.
 */
#define PUF_CFG_BLOCKKEYOUTPUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK)
/*! @} */

/*! @name KEYLOCK - Key Lock */
/*! @{ */
#define PUF_KEYLOCK_KEY0_MASK                    (0x3U)
#define PUF_KEYLOCK_KEY0_SHIFT                   (0U)
/*! KEY0 - Key 0
 *  0b00, 0b01, 0b11..Write access to KEY0MASK, KEYENABLE[KEY0] and KEYRESET[KEY0] is NOT allowed.
 *  0b10..Write access to KEY0MASK, KEYENABLE[KEY0] and KEYRESET[KEY0] is allowed.
 */
#define PUF_KEYLOCK_KEY0(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK)
#define PUF_KEYLOCK_KEY1_MASK                    (0xCU)
#define PUF_KEYLOCK_KEY1_SHIFT                   (2U)
/*! KEY1 - Key 1
 *  0b00, 0b01, 0b11..Write access to KEY1MASK, KEYENABLE[KEY1] and KEYRESET[KEY1] is NOT allowed.
 *  0b10..Write access to KEY1MASK, KEYENABLE[KEY1] and KEYRESET[KEY1] is allowed.
 */
#define PUF_KEYLOCK_KEY1(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK)
#define PUF_KEYLOCK_KEY2_MASK                    (0x30U)
#define PUF_KEYLOCK_KEY2_SHIFT                   (4U)
/*! KEY2 - Key 2
 *  0b00, 0b01, 0b11..Write access to KEY2MASK, KEYENABLE[KEY2] and KEYRESET[KEY2] is NOT allowed.
 *  0b10..Write access to KEY2MASK, KEYENABLE[KEY2] and KEYRESET[KEY2] is allowed.
 */
#define PUF_KEYLOCK_KEY2(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK)
#define PUF_KEYLOCK_KEY3_MASK                    (0xC0U)
#define PUF_KEYLOCK_KEY3_SHIFT                   (6U)
/*! KEY3 - Key 3
 *  0b00, 0b01, 0b11..Write access to KEY3MASK, KEYENABLE[KEY3] and KEYRESET[KEY3] is NOT allowed.
 *  0b10..Write access to KEY3MASK, KEYENABLE[KEY3] and KEYRESET[KEY3] is allowed.
 */
#define PUF_KEYLOCK_KEY3(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK)
/*! @} */

/*! @name KEYENABLE - Key Enable */
/*! @{ */
#define PUF_KEYENABLE_KEY0_MASK                  (0x3U)
#define PUF_KEYENABLE_KEY0_SHIFT                 (0U)
/*! KEY0 - Key 0
 *  0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY0 register.
 *  0b10..Data coming from the PUF Index 0 interface are shifted in the KEY0 register.
 */
#define PUF_KEYENABLE_KEY0(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK)
#define PUF_KEYENABLE_KEY1_MASK                  (0xCU)
#define PUF_KEYENABLE_KEY1_SHIFT                 (2U)
/*! KEY1 - Key 1
 *  0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY1 register.
 *  0b10..Data coming from the PUF Index 0 interface are shifted in the KEY1 register.
 */
#define PUF_KEYENABLE_KEY1(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK)
#define PUF_KEYENABLE_KEY2_MASK                  (0x30U)
#define PUF_KEYENABLE_KEY2_SHIFT                 (4U)
/*! KEY2 - Key 2
 *  0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY2 register.
 *  0b10..Data coming from the PUF Index 0 interface are shifted in the KEY2 register.
 */
#define PUF_KEYENABLE_KEY2(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK)
#define PUF_KEYENABLE_KEY3_MASK                  (0xC0U)
#define PUF_KEYENABLE_KEY3_SHIFT                 (6U)
/*! KEY3 - Key 3
 *  0b00, 0b01, 0b11..Data coming from the PUF Index 0 interface are NOT shifted in the KEY3 register.
 *  0b10..Data coming from the PUF Index 0 interface are shifted in the KEY3 register.
 */
#define PUF_KEYENABLE_KEY3(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK)
/*! @} */

/*! @name KEYRESET - Key Reset */
/*! @{ */
#define PUF_KEYRESET_KEY0_MASK                   (0x3U)
#define PUF_KEYRESET_KEY0_SHIFT                  (0U)
/*! KEY0 - Key 0
 *  0b10..Reset KEY0 Hold register and SHIFT_STATUS[KEY0].
 */
#define PUF_KEYRESET_KEY0(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK)
#define PUF_KEYRESET_KEY1_MASK                   (0xCU)
#define PUF_KEYRESET_KEY1_SHIFT                  (2U)
/*! KEY1 - Key 1
 *  0b10..Reset KEY1 Hold register and SHIFT_STATUS[KEY1].
 */
#define PUF_KEYRESET_KEY1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK)
#define PUF_KEYRESET_KEY2_MASK                   (0x30U)
#define PUF_KEYRESET_KEY2_SHIFT                  (4U)
/*! KEY2 - Key 2
 *  0b10..Reset KEY2 Hold register and SHIFT_STATUS[KEY2].
 */
#define PUF_KEYRESET_KEY2(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK)
#define PUF_KEYRESET_KEY3_MASK                   (0xC0U)
#define PUF_KEYRESET_KEY3_SHIFT                  (6U)
/*! KEY3 - Key 3
 *  0b10..Reset KEY3 Hold register and SHIFT_STATUS[KEY3].
 */
#define PUF_KEYRESET_KEY3(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK)
/*! @} */

/*! @name IDXBLK_L - Index Block Low */
/*! @{ */
#define PUF_IDXBLK_L_IDX1_MASK                   (0xCU)
#define PUF_IDXBLK_L_IDX1_SHIFT                  (2U)
/*! IDX1 - Index 1
 */
#define PUF_IDXBLK_L_IDX1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK)
#define PUF_IDXBLK_L_IDX2_MASK                   (0x30U)
#define PUF_IDXBLK_L_IDX2_SHIFT                  (4U)
/*! IDX2 - Index 2
 */
#define PUF_IDXBLK_L_IDX2(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK)
#define PUF_IDXBLK_L_IDX3_MASK                   (0xC0U)
#define PUF_IDXBLK_L_IDX3_SHIFT                  (6U)
/*! IDX3 - Index 3
 */
#define PUF_IDXBLK_L_IDX3(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK)
#define PUF_IDXBLK_L_IDX4_MASK                   (0x300U)
#define PUF_IDXBLK_L_IDX4_SHIFT                  (8U)
/*! IDX4 - Index 4
 */
#define PUF_IDXBLK_L_IDX4(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK)
#define PUF_IDXBLK_L_IDX5_MASK                   (0xC00U)
#define PUF_IDXBLK_L_IDX5_SHIFT                  (10U)
/*! IDX5 - Index 5
 */
#define PUF_IDXBLK_L_IDX5(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK)
#define PUF_IDXBLK_L_IDX6_MASK                   (0x3000U)
#define PUF_IDXBLK_L_IDX6_SHIFT                  (12U)
/*! IDX6 - Index 6
 */
#define PUF_IDXBLK_L_IDX6(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK)
#define PUF_IDXBLK_L_IDX7_MASK                   (0xC000U)
#define PUF_IDXBLK_L_IDX7_SHIFT                  (14U)
/*! IDX7 - Index 7
 */
#define PUF_IDXBLK_L_IDX7(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK)
#define PUF_IDXBLK_L_LOCK_IDX_MASK               (0xC0000000U)
#define PUF_IDXBLK_L_LOCK_IDX_SHIFT              (30U)
/*! LOCK_IDX - Lock Index
 */
#define PUF_IDXBLK_L_LOCK_IDX(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK)
/*! @} */

/*! @name IDXBLK_H_DP - Index Block High Duplicate */
/*! @{ */
#define PUF_IDXBLK_H_DP_IDX8_MASK                (0x3U)
#define PUF_IDXBLK_H_DP_IDX8_SHIFT               (0U)
/*! IDX8 - Index 8
 */
#define PUF_IDXBLK_H_DP_IDX8(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK)
#define PUF_IDXBLK_H_DP_IDX9_MASK                (0xCU)
#define PUF_IDXBLK_H_DP_IDX9_SHIFT               (2U)
/*! IDX9 - Index 9
 */
#define PUF_IDXBLK_H_DP_IDX9(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
#define PUF_IDXBLK_H_DP_IDX10_MASK               (0x30U)
#define PUF_IDXBLK_H_DP_IDX10_SHIFT              (4U)
/*! IDX10 - Index 10
 */
#define PUF_IDXBLK_H_DP_IDX10(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK)
#define PUF_IDXBLK_H_DP_IDX11_MASK               (0xC0U)
#define PUF_IDXBLK_H_DP_IDX11_SHIFT              (6U)
/*! IDX11 - Index 11
 */
#define PUF_IDXBLK_H_DP_IDX11(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK)
#define PUF_IDXBLK_H_DP_IDX12_MASK               (0x300U)
#define PUF_IDXBLK_H_DP_IDX12_SHIFT              (8U)
/*! IDX12 - Index 12
 */
#define PUF_IDXBLK_H_DP_IDX12(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK)
#define PUF_IDXBLK_H_DP_IDX13_MASK               (0xC00U)
#define PUF_IDXBLK_H_DP_IDX13_SHIFT              (10U)
/*! IDX13 - Index 13
 */
#define PUF_IDXBLK_H_DP_IDX13(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK)
#define PUF_IDXBLK_H_DP_IDX14_MASK               (0x3000U)
#define PUF_IDXBLK_H_DP_IDX14_SHIFT              (12U)
/*! IDX14 - Index 14
 */
#define PUF_IDXBLK_H_DP_IDX14(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK)
#define PUF_IDXBLK_H_DP_IDX15_MASK               (0xC000U)
#define PUF_IDXBLK_H_DP_IDX15_SHIFT              (14U)
/*! IDX15 - Index 15
 */
#define PUF_IDXBLK_H_DP_IDX15(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK)
/*! @} */

/*! @name KEYMASK - Key Mask 0..Key Mask 3 */
/*! @{ */
#define PUF_KEYMASK_KEYMASK_MASK                 (0xFFFFFFFFU)
#define PUF_KEYMASK_KEYMASK_SHIFT                (0U)
/*! KEYMASK - Key a Mask
 */
#define PUF_KEYMASK_KEYMASK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
/*! @} */

/* The count of PUF_KEYMASK */
#define PUF_KEYMASK_COUNT                        (4U)

/*! @name IDXBLK_H - Index Block High */
/*! @{ */
#define PUF_IDXBLK_H_IDX8_MASK                   (0x3U)
#define PUF_IDXBLK_H_IDX8_SHIFT                  (0U)
/*! IDX8 - Index 8
 */
#define PUF_IDXBLK_H_IDX8(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK)
#define PUF_IDXBLK_H_IDX9_MASK                   (0xCU)
#define PUF_IDXBLK_H_IDX9_SHIFT                  (2U)
/*! IDX9 - Index 9
 */
#define PUF_IDXBLK_H_IDX9(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK)
#define PUF_IDXBLK_H_IDX10_MASK                  (0x30U)
#define PUF_IDXBLK_H_IDX10_SHIFT                 (4U)
/*! IDX10 - Index 10
 */
#define PUF_IDXBLK_H_IDX10(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK)
#define PUF_IDXBLK_H_IDX11_MASK                  (0xC0U)
#define PUF_IDXBLK_H_IDX11_SHIFT                 (6U)
/*! IDX11 - Index 11
 */
#define PUF_IDXBLK_H_IDX11(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK)
#define PUF_IDXBLK_H_IDX12_MASK                  (0x300U)
#define PUF_IDXBLK_H_IDX12_SHIFT                 (8U)
/*! IDX12 - Index 12
 */
#define PUF_IDXBLK_H_IDX12(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK)
#define PUF_IDXBLK_H_IDX13_MASK                  (0xC00U)
#define PUF_IDXBLK_H_IDX13_SHIFT                 (10U)
/*! IDX13 - Index 13
 */
#define PUF_IDXBLK_H_IDX13(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK)
#define PUF_IDXBLK_H_IDX14_MASK                  (0x3000U)
#define PUF_IDXBLK_H_IDX14_SHIFT                 (12U)
/*! IDX14 - Index 14
 */
#define PUF_IDXBLK_H_IDX14(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK)
#define PUF_IDXBLK_H_IDX15_MASK                  (0xC000U)
#define PUF_IDXBLK_H_IDX15_SHIFT                 (14U)
/*! IDX15 - Index 15
 */
#define PUF_IDXBLK_H_IDX15(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK)
#define PUF_IDXBLK_H_LOCK_IDX_MASK               (0xC0000000U)
#define PUF_IDXBLK_H_LOCK_IDX_SHIFT              (30U)
/*! LOCK_IDX - Lock Index
 */
#define PUF_IDXBLK_H_LOCK_IDX(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK)
/*! @} */

/*! @name IDXBLK_L_DP - Index Block Low Duplicate */
/*! @{ */
#define PUF_IDXBLK_L_DP_IDX0_MASK                (0x3U)
#define PUF_IDXBLK_L_DP_IDX0_SHIFT               (0U)
/*! IDX0 - Index 0
 */
#define PUF_IDXBLK_L_DP_IDX0(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK)
#define PUF_IDXBLK_L_DP_IDX1_MASK                (0xCU)
#define PUF_IDXBLK_L_DP_IDX1_SHIFT               (2U)
/*! IDX1 - Index 1
 */
#define PUF_IDXBLK_L_DP_IDX1(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK)
#define PUF_IDXBLK_L_DP_IDX2_MASK                (0x30U)
#define PUF_IDXBLK_L_DP_IDX2_SHIFT               (4U)
/*! IDX2 - Index 2
 */
#define PUF_IDXBLK_L_DP_IDX2(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK)
#define PUF_IDXBLK_L_DP_IDX3_MASK                (0xC0U)
#define PUF_IDXBLK_L_DP_IDX3_SHIFT               (6U)
/*! IDX3 - Index 3
 */
#define PUF_IDXBLK_L_DP_IDX3(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK)
#define PUF_IDXBLK_L_DP_IDX4_MASK                (0x300U)
#define PUF_IDXBLK_L_DP_IDX4_SHIFT               (8U)
/*! IDX4 - Index 4
 */
#define PUF_IDXBLK_L_DP_IDX4(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK)
#define PUF_IDXBLK_L_DP_IDX5_MASK                (0xC00U)
#define PUF_IDXBLK_L_DP_IDX5_SHIFT               (10U)
/*! IDX5 - Index 5
 */
#define PUF_IDXBLK_L_DP_IDX5(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
#define PUF_IDXBLK_L_DP_IDX6_MASK                (0x3000U)
#define PUF_IDXBLK_L_DP_IDX6_SHIFT               (12U)
/*! IDX6 - Index 6
 */
#define PUF_IDXBLK_L_DP_IDX6(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK)
#define PUF_IDXBLK_L_DP_IDX7_MASK                (0xC000U)
#define PUF_IDXBLK_L_DP_IDX7_SHIFT               (14U)
/*! IDX7 - Index 7
 */
#define PUF_IDXBLK_L_DP_IDX7(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK)
/*! @} */

/*! @name SHIFT_STATUS - Shift Status */
/*! @{ */
#define PUF_SHIFT_STATUS_KEY0_MASK               (0xFU)
#define PUF_SHIFT_STATUS_KEY0_SHIFT              (0U)
/*! KEY0 - Key 0
 */
#define PUF_SHIFT_STATUS_KEY0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK)
#define PUF_SHIFT_STATUS_KEY1_MASK               (0xF0U)
#define PUF_SHIFT_STATUS_KEY1_SHIFT              (4U)
/*! KEY1 - Key 1
 */
#define PUF_SHIFT_STATUS_KEY1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK)
#define PUF_SHIFT_STATUS_KEY2_MASK               (0xF00U)
#define PUF_SHIFT_STATUS_KEY2_SHIFT              (8U)
/*! KEY2 - Key 2
 */
#define PUF_SHIFT_STATUS_KEY2(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK)
#define PUF_SHIFT_STATUS_KEY3_MASK               (0xF000U)
#define PUF_SHIFT_STATUS_KEY3_SHIFT              (12U)
/*! KEY3 - Key 3
 */
#define PUF_SHIFT_STATUS_KEY3(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group PUF_Register_Masks */


/* PUF - Peripheral instance base addresses */
/** Peripheral PUF base address */
#define PUF_BASE                                 (0x40006000u)
/** Peripheral PUF base pointer */
#define PUF                                      ((PUF_Type *)PUF_BASE)
/** Array initializer of PUF peripheral base addresses */
#define PUF_BASE_ADDRS                           { PUF_BASE }
/** Array initializer of PUF peripheral base pointers */
#define PUF_BASE_PTRS                            { PUF }

/*!
 * @}
 */ /* end of group PUF_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- ROMCP Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ROMCP_Peripheral_Access_Layer ROMCP Peripheral Access Layer
 * @{
 */

/** ROMCP - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[212];
  __IO uint32_t ROMPATCHD[8];                      /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
  __IO uint32_t ROMPATCHCNTL;                      /**< ROMC Control Register, offset: 0xF4 */
       uint32_t ROMPATCHENH;                       /**< ROMC Enable Register High, offset: 0xF8 */
  __IO uint32_t ROMPATCHENL;                       /**< ROMC Enable Register Low, offset: 0xFC */
  __IO uint32_t ROMPATCHA[16];                     /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
       uint8_t RESERVED_1[200];
  __IO uint32_t ROMPATCHSR;                        /**< ROMC Status Register, offset: 0x208 */
} ROMCP_Type;

/* ----------------------------------------------------------------------------
   -- ROMCP Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup ROMCP_Register_Masks ROMCP Register Masks
 * @{
 */

/*! @name ROMPATCHD - ROMC Data Registers */
/*! @{ */
#define ROMCP_ROMPATCHD_DATAX_MASK               (0xFFFFFFFFU)
#define ROMCP_ROMPATCHD_DATAX_SHIFT              (0U)
/*! DATAX - Data Fix Registers
 */
#define ROMCP_ROMPATCHD_DATAX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHD_DATAX_SHIFT)) & ROMCP_ROMPATCHD_DATAX_MASK)
/*! @} */

/* The count of ROMCP_ROMPATCHD */
#define ROMCP_ROMPATCHD_COUNT                    (8U)

/*! @name ROMPATCHCNTL - ROMC Control Register */
/*! @{ */
#define ROMCP_ROMPATCHCNTL_DATAFIX0_MASK         (0x1U)
#define ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT        (0U)
/*! DATAFIX0 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX0(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX0_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX1_MASK         (0x2U)
#define ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT        (1U)
/*! DATAFIX1 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX1(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX1_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX2_MASK         (0x4U)
#define ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT        (2U)
/*! DATAFIX2 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX2(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX2_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX3_MASK         (0x8U)
#define ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT        (3U)
/*! DATAFIX3 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX3(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX3_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX4_MASK         (0x10U)
#define ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT        (4U)
/*! DATAFIX4 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX4(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX4_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX5_MASK         (0x20U)
#define ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT        (5U)
/*! DATAFIX5 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX5(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX5_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX6_MASK         (0x40U)
#define ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT        (6U)
/*! DATAFIX6 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX6(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX6_MASK)
#define ROMCP_ROMPATCHCNTL_DATAFIX7_MASK         (0x80U)
#define ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT        (7U)
/*! DATAFIX7 - Data Fix Enable
 *  0b0..Trigger an opcode patch for ROMPATCHnA
 *  0b1..Trigger a data fix for ROMPATCHnA
 */
#define ROMCP_ROMPATCHCNTL_DATAFIX7(x)           (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT)) & ROMCP_ROMPATCHCNTL_DATAFIX7_MASK)
#define ROMCP_ROMPATCHCNTL_DIS_MASK              (0x20000000U)
#define ROMCP_ROMPATCHCNTL_DIS_SHIFT             (29U)
/*! DIS - ROMC Disable
 *  0b0..Does not affect any ROMC functions (default)
 *  0b1..Disables all ROMC functions: data fixing and opcode patching
 */
#define ROMCP_ROMPATCHCNTL_DIS(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & ROMCP_ROMPATCHCNTL_DIS_MASK)
/*! @} */

/*! @name ROMPATCHENL - ROMC Enable Register Low */
/*! @{ */
#define ROMCP_ROMPATCHENL_ENABLE0_MASK           (0x1U)
#define ROMCP_ROMPATCHENL_ENABLE0_SHIFT          (0U)
/*! ENABLE0 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE0(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE0_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE0_MASK)
#define ROMCP_ROMPATCHENL_ENABLE1_MASK           (0x2U)
#define ROMCP_ROMPATCHENL_ENABLE1_SHIFT          (1U)
/*! ENABLE1 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE1(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE1_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE1_MASK)
#define ROMCP_ROMPATCHENL_ENABLE2_MASK           (0x4U)
#define ROMCP_ROMPATCHENL_ENABLE2_SHIFT          (2U)
/*! ENABLE2 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE2(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE2_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE2_MASK)
#define ROMCP_ROMPATCHENL_ENABLE3_MASK           (0x8U)
#define ROMCP_ROMPATCHENL_ENABLE3_SHIFT          (3U)
/*! ENABLE3 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE3(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE3_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE3_MASK)
#define ROMCP_ROMPATCHENL_ENABLE4_MASK           (0x10U)
#define ROMCP_ROMPATCHENL_ENABLE4_SHIFT          (4U)
/*! ENABLE4 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE4(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE4_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE4_MASK)
#define ROMCP_ROMPATCHENL_ENABLE5_MASK           (0x20U)
#define ROMCP_ROMPATCHENL_ENABLE5_SHIFT          (5U)
/*! ENABLE5 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE5(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE5_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE5_MASK)
#define ROMCP_ROMPATCHENL_ENABLE6_MASK           (0x40U)
#define ROMCP_ROMPATCHENL_ENABLE6_SHIFT          (6U)
/*! ENABLE6 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE6(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE6_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE6_MASK)
#define ROMCP_ROMPATCHENL_ENABLE7_MASK           (0x80U)
#define ROMCP_ROMPATCHENL_ENABLE7_SHIFT          (7U)
/*! ENABLE7 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE7(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE7_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE7_MASK)
#define ROMCP_ROMPATCHENL_ENABLE8_MASK           (0x100U)
#define ROMCP_ROMPATCHENL_ENABLE8_SHIFT          (8U)
/*! ENABLE8 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE8(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE8_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE8_MASK)
#define ROMCP_ROMPATCHENL_ENABLE9_MASK           (0x200U)
#define ROMCP_ROMPATCHENL_ENABLE9_SHIFT          (9U)
/*! ENABLE9 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE9(x)             (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE9_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE9_MASK)
#define ROMCP_ROMPATCHENL_ENABLE10_MASK          (0x400U)
#define ROMCP_ROMPATCHENL_ENABLE10_SHIFT         (10U)
/*! ENABLE10 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE10(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE10_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE10_MASK)
#define ROMCP_ROMPATCHENL_ENABLE11_MASK          (0x800U)
#define ROMCP_ROMPATCHENL_ENABLE11_SHIFT         (11U)
/*! ENABLE11 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE11(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE11_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE11_MASK)
#define ROMCP_ROMPATCHENL_ENABLE12_MASK          (0x1000U)
#define ROMCP_ROMPATCHENL_ENABLE12_SHIFT         (12U)
/*! ENABLE12 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE12(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE12_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE12_MASK)
#define ROMCP_ROMPATCHENL_ENABLE13_MASK          (0x2000U)
#define ROMCP_ROMPATCHENL_ENABLE13_SHIFT         (13U)
/*! ENABLE13 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE13(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE13_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE13_MASK)
#define ROMCP_ROMPATCHENL_ENABLE14_MASK          (0x4000U)
#define ROMCP_ROMPATCHENL_ENABLE14_SHIFT         (14U)
/*! ENABLE14 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE14(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE14_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE14_MASK)
#define ROMCP_ROMPATCHENL_ENABLE15_MASK          (0x8000U)
#define ROMCP_ROMPATCHENL_ENABLE15_SHIFT         (15U)
/*! ENABLE15 - Enable Address Comparator n
 *  0b0..Address comparator n is disabled
 *  0b1..Address comparator n is enabled
 */
#define ROMCP_ROMPATCHENL_ENABLE15(x)            (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHENL_ENABLE15_SHIFT)) & ROMCP_ROMPATCHENL_ENABLE15_MASK)
/*! @} */

/*! @name ROMPATCHA - ROMC Address Registers */
/*! @{ */
#define ROMCP_ROMPATCHA_THUMBX_MASK              (0x1U)
#define ROMCP_ROMPATCHA_THUMBX_SHIFT             (0U)
/*! THUMBX - THUMB Comparator Select
 *  0b0..ARM patch
 *  0b1..THUMB patch (ignore if a data fix)
 */
#define ROMCP_ROMPATCHA_THUMBX(x)                (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_THUMBX_SHIFT)) & ROMCP_ROMPATCHA_THUMBX_MASK)
#define ROMCP_ROMPATCHA_ADDRX_MASK               (0x7FFFFEU)
#define ROMCP_ROMPATCHA_ADDRX_SHIFT              (1U)
/*! ADDRX - Address Comparator Registers
 */
#define ROMCP_ROMPATCHA_ADDRX(x)                 (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHA_ADDRX_SHIFT)) & ROMCP_ROMPATCHA_ADDRX_MASK)
/*! @} */

/* The count of ROMCP_ROMPATCHA */
#define ROMCP_ROMPATCHA_COUNT                    (16U)

/*! @name ROMPATCHSR - ROMC Status Register */
/*! @{ */
#define ROMCP_ROMPATCHSR_SOURCE_MASK             (0x3FU)
#define ROMCP_ROMPATCHSR_SOURCE_SHIFT            (0U)
/*! SOURCE - ROMC Source Number
 *  0b000000..Address Comparator 0 matched
 *  0b000001..Address Comparator 1 matched
 *  0b001111..Address Comparator 15 matched
 */
#define ROMCP_ROMPATCHSR_SOURCE(x)               (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & ROMCP_ROMPATCHSR_SOURCE_MASK)
#define ROMCP_ROMPATCHSR_SW_MASK                 (0x20000U)
#define ROMCP_ROMPATCHSR_SW_SHIFT                (17U)
/*! SW - ROMC AHB Multiple Address Comparator Match Indicator
 *  0b0..No event or comparator collisions have occurred
 *  0b1..A collision has occurred
 */
#define ROMCP_ROMPATCHSR_SW(x)                   (((uint32_t)(((uint32_t)(x)) << ROMCP_ROMPATCHSR_SW_SHIFT)) & ROMCP_ROMPATCHSR_SW_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group ROMCP_Register_Masks */


/* ROMCP - Peripheral instance base addresses */
/** Peripheral ROMCP0 base address */
#define ROMCP0_BASE                              (0x40115000u)
/** Peripheral ROMCP0 base pointer */
#define ROMCP0                                   ((ROMCP_Type *)ROMCP0_BASE)
/** Array initializer of ROMCP peripheral base addresses */
#define ROMCP_BASE_ADDRS                         { ROMCP0_BASE }
/** Array initializer of ROMCP peripheral base pointers */
#define ROMCP_BASE_PTRS                          { ROMCP0 }

/*!
 * @}
 */ /* end of group ROMCP_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RSTCTL0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL0_Peripheral_Access_Layer RSTCTL0 Peripheral Access Layer
 * @{
 */

/** RSTCTL0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t SYSRSTSTAT;                        /**< System Reset Status Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t PRSTCTL0;                          /**< Peripheral Reset Control Register 0, offset: 0x10 */
  __IO uint32_t PRSTCTL1;                          /**< Peripheral Reset Control Register 1, offset: 0x14 */
  __IO uint32_t PRSTCTL2;                          /**< Peripheral Reset Control Register 2, offset: 0x18 */
       uint8_t RESERVED_1[36];
  __O  uint32_t PRSTCTL0_SET;                      /**< Peripheral Reset Control Register 0 SET, offset: 0x40 */
  __O  uint32_t PRSTCTL1_SET;                      /**< Peripheral Reset Control Register 1 SET, offset: 0x44 */
  __O  uint32_t PRSTCTL2_SET;                      /**< Peripheral Reset Control Register 2 SET, offset: 0x48 */
       uint8_t RESERVED_2[36];
  __O  uint32_t PRSTCTL0_CLR;                      /**< Peripheral Reset Control Register 0 CLR, offset: 0x70 */
  __O  uint32_t PRSTCTL1_CLR;                      /**< Peripheral Reset Control Register 1 CLR, offset: 0x74 */
  __O  uint32_t PRSTCTL2_CLR;                      /**< Peripheral Reset Control Register 2 CLR, offset: 0x78 */
} RSTCTL0_Type;

/* ----------------------------------------------------------------------------
   -- RSTCTL0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL0_Register_Masks RSTCTL0 Register Masks
 * @{
 */

/*! @name SYSRSTSTAT - System Reset Status Register */
/*! @{ */
#define RSTCTL0_SYSRSTSTAT_VDD_POR_MASK          (0x1U)
#define RSTCTL0_SYSRSTSTAT_VDD_POR_SHIFT         (0U)
/*! VDD_POR - VDD Power-On Reset (POR) was detected
 *  0b0..No VDD POR event is detected
 *  0b1..VDD POR event was detected
 */
#define RSTCTL0_SYSRSTSTAT_VDD_POR(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_VDD_POR_SHIFT)) & RSTCTL0_SYSRSTSTAT_VDD_POR_MASK)
#define RSTCTL0_SYSRSTSTAT_PAD_RESET_MASK        (0x10U)
#define RSTCTL0_SYSRSTSTAT_PAD_RESET_SHIFT       (4U)
/*! PAD_RESET - PAD reset was detected
 *  0b0..No PAD event is detected
 *  0b1..PAD event was detected. Write '1' to clear this bit
 */
#define RSTCTL0_SYSRSTSTAT_PAD_RESET(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_PAD_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_PAD_RESET_MASK)
#define RSTCTL0_SYSRSTSTAT_ARM_RESET_MASK        (0x20U)
#define RSTCTL0_SYSRSTSTAT_ARM_RESET_SHIFT       (5U)
/*! ARM_RESET - ARM reset was detected
 *  0b0..No ARM reset event is detected
 *  0b1..ARM reset was detected. Write '1' to clear this bit
 */
#define RSTCTL0_SYSRSTSTAT_ARM_RESET(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_ARM_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_ARM_RESET_MASK)
#define RSTCTL0_SYSRSTSTAT_WDT0_RESET_MASK       (0x40U)
#define RSTCTL0_SYSRSTSTAT_WDT0_RESET_SHIFT      (6U)
/*! WDT0_RESET - WatchDog Timer 0 reset was detected
 *  0b0..No WDT0 reset event detected
 *  0b1..WDT0 reset event detected. Write '1' to clear this bit
 */
#define RSTCTL0_SYSRSTSTAT_WDT0_RESET(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_WDT0_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_WDT0_RESET_MASK)
#define RSTCTL0_SYSRSTSTAT_WDT1_RESET_MASK       (0x80U)
#define RSTCTL0_SYSRSTSTAT_WDT1_RESET_SHIFT      (7U)
/*! WDT1_RESET - WatchDog Timer 1 reset was detected
 *  0b0..No WDT1 reset event detected
 *  0b1..WDT1 reset event detected. Write '1' to clear this bit
 */
#define RSTCTL0_SYSRSTSTAT_WDT1_RESET(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_SYSRSTSTAT_WDT1_RESET_SHIFT)) & RSTCTL0_SYSRSTSTAT_WDT1_RESET_MASK)
/*! @} */

/*! @name PRSTCTL0 - Peripheral Reset Control Register 0 */
/*! @{ */
#define RSTCTL0_PRSTCTL0_DSP_MASK                (0x2U)
#define RSTCTL0_PRSTCTL0_DSP_SHIFT               (1U)
/*! DSP - Fusion F1 DSP reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL0_DSP(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_DSP_SHIFT)) & RSTCTL0_PRSTCTL0_DSP_MASK)
#define RSTCTL0_PRSTCTL0_AXI_SWITCH_MASK         (0x8U)
#define RSTCTL0_PRSTCTL0_AXI_SWITCH_SHIFT        (3U)
/*! AXI_SWITCH - AXI Switch reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_AXI_SWITCH(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_AXI_SWITCH_SHIFT)) & RSTCTL0_PRSTCTL0_AXI_SWITCH_MASK)
#define RSTCTL0_PRSTCTL0_POWERQUAD_MASK          (0x100U)
#define RSTCTL0_PRSTCTL0_POWERQUAD_SHIFT         (8U)
/*! POWERQUAD - POWERQUAD reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_POWERQUAD(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_POWERQUAD_SHIFT)) & RSTCTL0_PRSTCTL0_POWERQUAD_MASK)
#define RSTCTL0_PRSTCTL0_CASPER_MASK             (0x200U)
#define RSTCTL0_PRSTCTL0_CASPER_SHIFT            (9U)
/*! CASPER - CASPER reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_CASPER(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CASPER_SHIFT)) & RSTCTL0_PRSTCTL0_CASPER_MASK)
#define RSTCTL0_PRSTCTL0_HASHCRYPT_MASK          (0x400U)
#define RSTCTL0_PRSTCTL0_HASHCRYPT_SHIFT         (10U)
/*! HASHCRYPT - Hash-Crypt reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_HASHCRYPT(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_HASHCRYPT_SHIFT)) & RSTCTL0_PRSTCTL0_HASHCRYPT_MASK)
#define RSTCTL0_PRSTCTL0_PUF_MASK                (0x800U)
#define RSTCTL0_PRSTCTL0_PUF_SHIFT               (11U)
/*! PUF - PUF reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_PUF(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_PUF_MASK)
#define RSTCTL0_PRSTCTL0_RNG_MASK                (0x1000U)
#define RSTCTL0_PRSTCTL0_RNG_SHIFT               (12U)
/*! RNG - RNG reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_RNG(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_RNG_SHIFT)) & RSTCTL0_PRSTCTL0_RNG_MASK)
#define RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_MASK     (0x10000U)
#define RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_SHIFT    (16U)
/*! FLEXSPI0_OTFAD - FLEXSPI0 and OTFAD reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_SHIFT)) & RSTCTL0_PRSTCTL0_FLEXSPI0_OTFAD_MASK)
#define RSTCTL0_PRSTCTL0_FLEXSPI1_MASK           (0x40000U)
#define RSTCTL0_PRSTCTL0_FLEXSPI1_SHIFT          (18U)
/*! FLEXSPI1 - FLEXSPI1 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_FLEXSPI1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_FLEXSPI1_SHIFT)) & RSTCTL0_PRSTCTL0_FLEXSPI1_MASK)
#define RSTCTL0_PRSTCTL0_USBHS_PHY_MASK          (0x100000U)
#define RSTCTL0_PRSTCTL0_USBHS_PHY_SHIFT         (20U)
/*! USBHS_PHY - USB PHY reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_USBHS_PHY(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_PHY_MASK)
#define RSTCTL0_PRSTCTL0_USBHS_DEVICE_MASK       (0x200000U)
#define RSTCTL0_PRSTCTL0_USBHS_DEVICE_SHIFT      (21U)
/*! USBHS_DEVICE - USB HS Device reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_USBHS_DEVICE(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_DEVICE_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_DEVICE_MASK)
#define RSTCTL0_PRSTCTL0_USBHS_HOST_MASK         (0x400000U)
#define RSTCTL0_PRSTCTL0_USBHS_HOST_SHIFT        (22U)
/*! USBHS_HOST - USB HOST reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_USBHS_HOST(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_HOST_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_HOST_MASK)
#define RSTCTL0_PRSTCTL0_USBHS_SRAM_MASK         (0x800000U)
#define RSTCTL0_PRSTCTL0_USBHS_SRAM_SHIFT        (23U)
/*! USBHS_SRAM - USB RAM reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_USBHS_SRAM(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_USBHS_SRAM_SHIFT)) & RSTCTL0_PRSTCTL0_USBHS_SRAM_MASK)
#define RSTCTL0_PRSTCTL0_SCT_MASK                (0x1000000U)
#define RSTCTL0_PRSTCTL0_SCT_SHIFT               (24U)
/*! SCT - SC Timer reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_SCT(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_SCT_MASK)
#define RSTCTL0_PRSTCTL0_GPU_MASK                (0x4000000U)
#define RSTCTL0_PRSTCTL0_GPU_SHIFT               (26U)
/*! GPU - GPU reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_GPU(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_GPU_SHIFT)) & RSTCTL0_PRSTCTL0_GPU_MASK)
#define RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_MASK (0x8000000U)
#define RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_SHIFT (27U)
/*! DISPLAY_CONTROLLER - Display Controller reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_DISPLAY_CONTROLLER_MASK)
#define RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
#define RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_SHIFT (28U)
/*! MIPI_DSI_CONTROLLER - MIPI Digital serial Interface controller reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER(x)  (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_MIPI_DSI_CONTROLLER_MASK)
#define RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_MASK       (0x20000000U)
#define RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_SHIFT      (29U)
/*! MIPI_DSI_PHY - MIPI DSI PHY reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_MIPI_DSI_PHY(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_MIPI_DSI_PHY_MASK)
#define RSTCTL0_PRSTCTL0_SMARTDMA_MASK           (0x40000000U)
#define RSTCTL0_PRSTCTL0_SMARTDMA_SHIFT          (30U)
/*! SMARTDMA - SMARTDMA Event/Algorithm handler reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL0_PRSTCTL0_SMARTDMA(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SMARTDMA_SHIFT)) & RSTCTL0_PRSTCTL0_SMARTDMA_MASK)
/*! @} */

/*! @name PRSTCTL1 - Peripheral Reset Control Register 1 */
/*! @{ */
#define RSTCTL0_PRSTCTL1_SDIO0_MASK              (0x4U)
#define RSTCTL0_PRSTCTL1_SDIO0_SHIFT             (2U)
/*! SDIO0 - SDIO0 reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL1_SDIO0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SDIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SDIO0_MASK)
#define RSTCTL0_PRSTCTL1_SDIO1_MASK              (0x8U)
#define RSTCTL0_PRSTCTL1_SDIO1_SHIFT             (3U)
/*! SDIO1 - SDIO1 reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL1_SDIO1(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SDIO1_SHIFT)) & RSTCTL0_PRSTCTL1_SDIO1_MASK)
#define RSTCTL0_PRSTCTL1_ACMP0_MASK              (0x8000U)
#define RSTCTL0_PRSTCTL1_ACMP0_SHIFT             (15U)
/*! ACMP0
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL1_ACMP0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ACMP0_SHIFT)) & RSTCTL0_PRSTCTL1_ACMP0_MASK)
#define RSTCTL0_PRSTCTL1_ADC0_MASK               (0x10000U)
#define RSTCTL0_PRSTCTL1_ADC0_SHIFT              (16U)
/*! ADC0
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL1_ADC0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_ADC0_MASK)
#define RSTCTL0_PRSTCTL1_SHSGPIO0_MASK           (0x1000000U)
#define RSTCTL0_PRSTCTL1_SHSGPIO0_SHIFT          (24U)
/*! SHSGPIO0 - Secure GPIO 0 reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL1_SHSGPIO0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SHSGPIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SHSGPIO0_MASK)
/*! @} */

/*! @name PRSTCTL2 - Peripheral Reset Control Register 2 */
/*! @{ */
#define RSTCTL0_PRSTCTL2_UTICK0_MASK             (0x1U)
#define RSTCTL0_PRSTCTL2_UTICK0_SHIFT            (0U)
/*! UTICK0 - Micro-tick timer reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL2_UTICK0(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL2_UTICK0_MASK)
#define RSTCTL0_PRSTCTL2_WWDT0_MASK              (0x2U)
#define RSTCTL0_PRSTCTL2_WWDT0_SHIFT             (1U)
/*! WWDT0 - Watchdog timer reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL2_WWDT0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_WWDT0_MASK)
#define RSTCTL0_PRSTCTL2_FREEMRT_TEST_MASK       (0x4000000U)
#define RSTCTL0_PRSTCTL2_FREEMRT_TEST_SHIFT      (26U)
/*! FREEMRT_TEST - FREEMRT reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL2_FREEMRT_TEST(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_FREEMRT_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_FREEMRT_TEST_MASK)
#define RSTCTL0_PRSTCTL2_PVTCTL_TEST_MASK        (0x8000000U)
#define RSTCTL0_PRSTCTL2_PVTCTL_TEST_SHIFT       (27U)
/*! PVTCTL_TEST - PVTCTL reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL2_PVTCTL_TEST(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_PVTCTL_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_PVTCTL_TEST_MASK)
#define RSTCTL0_PRSTCTL2_DPM_TEST_MASK           (0x10000000U)
#define RSTCTL0_PRSTCTL2_DPM_TEST_SHIFT          (28U)
/*! DPM_TEST - DPM reset control
 *  0b0..Clear Reset
 *  0b1..Set Reset
 */
#define RSTCTL0_PRSTCTL2_DPM_TEST(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_DPM_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_DPM_TEST_MASK)
/*! @} */

/*! @name PRSTCTL0_SET - Peripheral Reset Control Register 0 SET */
/*! @{ */
#define RSTCTL0_PRSTCTL0_SET_DSP_MASK            (0x2U)
#define RSTCTL0_PRSTCTL0_SET_DSP_SHIFT           (1U)
/*! DSP - Fusion_ DSP reset set
 *  0b0..No Effect
 *  0b1..Sets the PRSTCTL0 Bit
 */
#define RSTCTL0_PRSTCTL0_SET_DSP(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_DSP_SHIFT)) & RSTCTL0_PRSTCTL0_SET_DSP_MASK)
#define RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_MASK     (0x8U)
#define RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_SHIFT    (3U)
/*! AXI_SWITCH - AXI SWITCH reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_AXI_SWITCH(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_SHIFT)) & RSTCTL0_PRSTCTL0_SET_AXI_SWITCH_MASK)
#define RSTCTL0_PRSTCTL0_SET_POWERQUAD_MASK      (0x100U)
#define RSTCTL0_PRSTCTL0_SET_POWERQUAD_SHIFT     (8U)
/*! POWERQUAD - POWERQUAD reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_POWERQUAD(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_POWERQUAD_SHIFT)) & RSTCTL0_PRSTCTL0_SET_POWERQUAD_MASK)
#define RSTCTL0_PRSTCTL0_SET_CASPER_MASK         (0x200U)
#define RSTCTL0_PRSTCTL0_SET_CASPER_SHIFT        (9U)
/*! CASPER - CASPER reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_CASPER(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_CASPER_SHIFT)) & RSTCTL0_PRSTCTL0_SET_CASPER_MASK)
#define RSTCTL0_PRSTCTL0_SET_HASHCRYPT_MASK      (0x400U)
#define RSTCTL0_PRSTCTL0_SET_HASHCRYPT_SHIFT     (10U)
/*! HASHCRYPT - HASHCRYPT reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_HASHCRYPT(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_HASHCRYPT_SHIFT)) & RSTCTL0_PRSTCTL0_SET_HASHCRYPT_MASK)
#define RSTCTL0_PRSTCTL0_SET_PUF_MASK            (0x800U)
#define RSTCTL0_PRSTCTL0_SET_PUF_SHIFT           (11U)
/*! PUF - PUF reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_PUF(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_SET_PUF_MASK)
#define RSTCTL0_PRSTCTL0_SET_RNG_MASK            (0x1000U)
#define RSTCTL0_PRSTCTL0_SET_RNG_SHIFT           (12U)
/*! RNG - RNG reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_RNG(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_RNG_SHIFT)) & RSTCTL0_PRSTCTL0_SET_RNG_MASK)
#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_MASK (0x10000U)
#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_SHIFT (16U)
/*! FLEXSPI0_OTFAD - FLEXSPI0 and OTFAD reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_SHIFT)) & RSTCTL0_PRSTCTL0_SET_FLEXSPI0_OTFAD_MASK)
#define RSTCTL0_PRSTCTL0_SET_FLEXSPI1_MASK       (0x40000U)
#define RSTCTL0_PRSTCTL0_SET_FLEXSPI1_SHIFT      (18U)
/*! FLEXSPI1 - FLEXSPI1 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_FLEXSPI1(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_FLEXSPI1_SHIFT)) & RSTCTL0_PRSTCTL0_SET_FLEXSPI1_MASK)
#define RSTCTL0_PRSTCTL0_SET_USBHS_PHY_MASK      (0x100000U)
#define RSTCTL0_PRSTCTL0_SET_USBHS_PHY_SHIFT     (20U)
/*! USBHS_PHY - USB PHY reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_USBHS_PHY(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_PHY_MASK)
#define RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_MASK   (0x200000U)
#define RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_SHIFT  (21U)
/*! USBHS_DEVICE - USB Device reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_DEVICE_MASK)
#define RSTCTL0_PRSTCTL0_SET_USBHS_HOST_MASK     (0x400000U)
#define RSTCTL0_PRSTCTL0_SET_USBHS_HOST_SHIFT    (22U)
/*! USBHS_HOST - USB HOST reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_USBHS_HOST(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_HOST_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_HOST_MASK)
#define RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_MASK     (0x800000U)
#define RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_SHIFT    (23U)
/*! USBHS_SRAM - USBHS SRAM reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_USBHS_SRAM(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_SHIFT)) & RSTCTL0_PRSTCTL0_SET_USBHS_SRAM_MASK)
#define RSTCTL0_PRSTCTL0_SET_SCT_MASK            (0x1000000U)
#define RSTCTL0_PRSTCTL0_SET_SCT_SHIFT           (24U)
/*! SCT - SC Timer reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_SCT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_SET_SCT_MASK)
#define RSTCTL0_PRSTCTL0_SET_GPU_MASK            (0x4000000U)
#define RSTCTL0_PRSTCTL0_SET_GPU_SHIFT           (26U)
/*! GPU - GPU reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_GPU(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_GPU_SHIFT)) & RSTCTL0_PRSTCTL0_SET_GPU_MASK)
#define RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_MASK (0x8000000U)
#define RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_SHIFT (27U)
/*! DISPLAY_CONTROLLER - DISPLAY CONTROLLER reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_SET_DISPLAY_CONTROLLER_MASK)
#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_SHIFT (28U)
/*! MIPI_DSI_CONTROLLER - MIPI DSI controller reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_SET_MIPI_DSI_CONTROLLER_MASK)
#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_MASK   (0x20000000U)
#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_SHIFT  (29U)
/*! MIPI_DSI_PHY - MIPI DSI PHY reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_SET_MIPI_DSI_PHY_MASK)
#define RSTCTL0_PRSTCTL0_SET_SMARTDMA_MASK       (0x40000000U)
#define RSTCTL0_PRSTCTL0_SET_SMARTDMA_SHIFT      (30U)
/*! SMARTDMA - SMARTDMA Event/Algorithm handler reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL0_PRSTCTL0_SET_SMARTDMA(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_SET_SMARTDMA_SHIFT)) & RSTCTL0_PRSTCTL0_SET_SMARTDMA_MASK)
/*! @} */

/*! @name PRSTCTL1_SET - Peripheral Reset Control Register 1 SET */
/*! @{ */
#define RSTCTL0_PRSTCTL1_SET_SDIO0_MASK          (0x4U)
#define RSTCTL0_PRSTCTL1_SET_SDIO0_SHIFT         (2U)
/*! SDIO0 - SDIO0 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_SET_SDIO0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SDIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SDIO0_MASK)
#define RSTCTL0_PRSTCTL1_SET_SDIO1_MASK          (0x8U)
#define RSTCTL0_PRSTCTL1_SET_SDIO1_SHIFT         (3U)
/*! SDIO1 - SDIO1 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_SET_SDIO1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SDIO1_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SDIO1_MASK)
#define RSTCTL0_PRSTCTL1_SET_ACMP0_MASK          (0x8000U)
#define RSTCTL0_PRSTCTL1_SET_ACMP0_SHIFT         (15U)
/*! ACMP0 - ACMP0 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_SET_ACMP0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ACMP0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ACMP0_MASK)
#define RSTCTL0_PRSTCTL1_SET_ADC0_MASK           (0x10000U)
#define RSTCTL0_PRSTCTL1_SET_ADC0_SHIFT          (16U)
/*! ADC0 - ADC0 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_SET_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_ADC0_MASK)
#define RSTCTL0_PRSTCTL1_SET_SHSGPIO0_MASK       (0x1000000U)
#define RSTCTL0_PRSTCTL1_SET_SHSGPIO0_SHIFT      (24U)
/*! SHSGPIO0 - SHSGPIO0 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_SET_SHSGPIO0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_SET_SHSGPIO0_SHIFT)) & RSTCTL0_PRSTCTL1_SET_SHSGPIO0_MASK)
/*! @} */

/*! @name PRSTCTL2_SET - Peripheral Reset Control Register 2 SET */
/*! @{ */
#define RSTCTL0_PRSTCTL2_SET_UTICK0_MASK         (0x1U)
#define RSTCTL0_PRSTCTL2_SET_UTICK0_SHIFT        (0U)
/*! UTICK0 - Micro-tick timer 0 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_SET_UTICK0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_UTICK0_MASK)
#define RSTCTL0_PRSTCTL2_SET_WWDT0_MASK          (0x2U)
#define RSTCTL0_PRSTCTL2_SET_WWDT0_SHIFT         (1U)
/*! WWDT0 - WWDT0 reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_SET_WWDT0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_SET_WWDT0_MASK)
#define RSTCTL0_PRSTCTL2_SET_FREEMRT_TEST_MASK   (0x4000000U)
#define RSTCTL0_PRSTCTL2_SET_FREEMRT_TEST_SHIFT  (26U)
/*! FREEMRT_TEST - FREEMRT reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_SET_FREEMRT_TEST(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_FREEMRT_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_SET_FREEMRT_TEST_MASK)
#define RSTCTL0_PRSTCTL2_SET_PVTCTL_TEST_MASK    (0x8000000U)
#define RSTCTL0_PRSTCTL2_SET_PVTCTL_TEST_SHIFT   (27U)
/*! PVTCTL_TEST - PVTCTL reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_SET_PVTCTL_TEST(x)      (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_PVTCTL_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_SET_PVTCTL_TEST_MASK)
#define RSTCTL0_PRSTCTL2_SET_DPM_TEST_MASK       (0x10000000U)
#define RSTCTL0_PRSTCTL2_SET_DPM_TEST_SHIFT      (28U)
/*! DPM_TEST - DPM reset set
 *  0b0..No effect
 *  0b1..Sets the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_SET_DPM_TEST(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_SET_DPM_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_SET_DPM_TEST_MASK)
/*! @} */

/*! @name PRSTCTL0_CLR - Peripheral Reset Control Register 0 CLR */
/*! @{ */
#define RSTCTL0_PRSTCTL0_CLR_DSP_MASK            (0x2U)
#define RSTCTL0_PRSTCTL0_CLR_DSP_SHIFT           (1U)
/*! DSP
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL0 Bit
 */
#define RSTCTL0_PRSTCTL0_CLR_DSP(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_DSP_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_DSP_MASK)
#define RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_MASK     (0x8U)
#define RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_SHIFT    (3U)
/*! AXI_SWITCH - AXI SWITCH reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_AXI_SWITCH_MASK)
#define RSTCTL0_PRSTCTL0_CLR_POWERQUAD_MASK      (0x100U)
#define RSTCTL0_PRSTCTL0_CLR_POWERQUAD_SHIFT     (8U)
/*! POWERQUAD - POWERQUAD reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_POWERQUAD(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_POWERQUAD_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_POWERQUAD_MASK)
#define RSTCTL0_PRSTCTL0_CLR_CASPER_MASK         (0x200U)
#define RSTCTL0_PRSTCTL0_CLR_CASPER_SHIFT        (9U)
/*! CASPER - CASPER reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_CASPER(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_CASPER_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_CASPER_MASK)
#define RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_MASK      (0x400U)
#define RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_SHIFT     (10U)
/*! HASHCRYPT - HASHCRYPT reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_HASHCRYPT(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_HASHCRYPT_MASK)
#define RSTCTL0_PRSTCTL0_CLR_PUF_MASK            (0x800U)
#define RSTCTL0_PRSTCTL0_CLR_PUF_SHIFT           (11U)
/*! PUF - PUF reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_PUF(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_PUF_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_PUF_MASK)
#define RSTCTL0_PRSTCTL0_CLR_RNG_MASK            (0x1000U)
#define RSTCTL0_PRSTCTL0_CLR_RNG_SHIFT           (12U)
/*! RNG - RNG reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_RNG(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_RNG_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_RNG_MASK)
#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_MASK (0x10000U)
#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_SHIFT (16U)
/*! FLEXSPI0_OTFAD - FLEXSPI0 and OTFAD reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_FLEXSPI0_OTFAD_MASK)
#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_MASK       (0x40000U)
#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_SHIFT      (18U)
/*! FLEXSPI1 - FLEXSPI1 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_FLEXSPI1(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_FLEXSPI1_MASK)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_MASK      (0x100000U)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_SHIFT     (20U)
/*! USBHS_PHY - USB PHY reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_USBHS_PHY(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_PHY_MASK)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_MASK   (0x200000U)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_SHIFT  (21U)
/*! USBHS_DEVICE - USB DEVICE reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_DEVICE_MASK)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_MASK     (0x400000U)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_SHIFT    (22U)
/*! USBHS_HOST - USB HOST reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_USBHS_HOST(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_HOST_MASK)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_MASK     (0x800000U)
#define RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_SHIFT    (23U)
/*! USBHS_SRAM - USBHS SRAM reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_USBHS_SRAM_MASK)
#define RSTCTL0_PRSTCTL0_CLR_SCT_MASK            (0x1000000U)
#define RSTCTL0_PRSTCTL0_CLR_SCT_SHIFT           (24U)
/*! SCT - SCT reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_SCT(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_SCT_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_SCT_MASK)
#define RSTCTL0_PRSTCTL0_CLR_GPU_MASK            (0x4000000U)
#define RSTCTL0_PRSTCTL0_CLR_GPU_SHIFT           (26U)
/*! GPU - GPU reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_GPU(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_GPU_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_GPU_MASK)
#define RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_MASK (0x8000000U)
#define RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_SHIFT (27U)
/*! DISPLAY_CONTROLLER - DISPLAY CONTROLLER reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_DISPLAY_CONTROLLER_MASK)
#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_SHIFT (28U)
/*! MIPI_DSI_CONTROLLER - MIPI DSI controller reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_CONTROLLER_MASK)
#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_MASK   (0x20000000U)
#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_SHIFT  (29U)
/*! MIPI_DSI_PHY - MIPI DSI PHY reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_MIPI_DSI_PHY_MASK)
#define RSTCTL0_PRSTCTL0_CLR_SMARTDMA_MASK       (0x40000000U)
#define RSTCTL0_PRSTCTL0_CLR_SMARTDMA_SHIFT      (30U)
/*! SMARTDMA - SMARTDMA Event/Algorithm handler reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL0_PRSTCTL0_CLR_SMARTDMA(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL0_CLR_SMARTDMA_SHIFT)) & RSTCTL0_PRSTCTL0_CLR_SMARTDMA_MASK)
/*! @} */

/*! @name PRSTCTL1_CLR - Peripheral Reset Control Register 1 CLR */
/*! @{ */
#define RSTCTL0_PRSTCTL1_CLR_SDIO0_MASK          (0x4U)
#define RSTCTL0_PRSTCTL1_CLR_SDIO0_SHIFT         (2U)
/*! SDIO0 - SDIO0 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_CLR_SDIO0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SDIO0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SDIO0_MASK)
#define RSTCTL0_PRSTCTL1_CLR_SDIO1_MASK          (0x8U)
#define RSTCTL0_PRSTCTL1_CLR_SDIO1_SHIFT         (3U)
/*! SDIO1 - SDIO1 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_CLR_SDIO1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SDIO1_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SDIO1_MASK)
#define RSTCTL0_PRSTCTL1_CLR_ACMP0_MASK          (0x8000U)
#define RSTCTL0_PRSTCTL1_CLR_ACMP0_SHIFT         (15U)
/*! ACMP0 - ACMP0 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_CLR_ACMP0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ACMP0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ACMP0_MASK)
#define RSTCTL0_PRSTCTL1_CLR_ADC0_MASK           (0x10000U)
#define RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT          (16U)
/*! ADC0 - ADC0 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_CLR_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_ADC0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_ADC0_MASK)
#define RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_MASK       (0x1000000U)
#define RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_SHIFT      (24U)
/*! SHSGPIO0 - Secure HSGPIO0 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL1 Bit
 */
#define RSTCTL0_PRSTCTL1_CLR_SHSGPIO0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_SHIFT)) & RSTCTL0_PRSTCTL1_CLR_SHSGPIO0_MASK)
/*! @} */

/*! @name PRSTCTL2_CLR - Peripheral Reset Control Register 2 CLR */
/*! @{ */
#define RSTCTL0_PRSTCTL2_CLR_UTICK0_MASK         (0x1U)
#define RSTCTL0_PRSTCTL2_CLR_UTICK0_SHIFT        (0U)
/*! UTICK0 - Micro-tick timer 0 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_CLR_UTICK0(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_UTICK0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_UTICK0_MASK)
#define RSTCTL0_PRSTCTL2_CLR_WWDT0_MASK          (0x2U)
#define RSTCTL0_PRSTCTL2_CLR_WWDT0_SHIFT         (1U)
/*! WWDT0 - WWDT0 reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_CLR_WWDT0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_WWDT0_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_WWDT0_MASK)
#define RSTCTL0_PRSTCTL2_CLR_FREEMRT_TEST_MASK   (0x4000000U)
#define RSTCTL0_PRSTCTL2_CLR_FREEMRT_TEST_SHIFT  (26U)
/*! FREEMRT_TEST - FREEMRT reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_CLR_FREEMRT_TEST(x)     (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_FREEMRT_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_FREEMRT_TEST_MASK)
#define RSTCTL0_PRSTCTL2_CLR_PVTCTL_TEST_MASK    (0x8000000U)
#define RSTCTL0_PRSTCTL2_CLR_PVTCTL_TEST_SHIFT   (27U)
/*! PVTCTL_TEST - PVTCTL reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_CLR_PVTCTL_TEST(x)      (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_PVTCTL_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_PVTCTL_TEST_MASK)
#define RSTCTL0_PRSTCTL2_CLR_DPM_TEST_MASK       (0x10000000U)
#define RSTCTL0_PRSTCTL2_CLR_DPM_TEST_SHIFT      (28U)
/*! DPM_TEST - DPM reset clear
 *  0b0..No effect
 *  0b1..Clears the PRSTCTL2 Bit
 */
#define RSTCTL0_PRSTCTL2_CLR_DPM_TEST(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL0_PRSTCTL2_CLR_DPM_TEST_SHIFT)) & RSTCTL0_PRSTCTL2_CLR_DPM_TEST_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RSTCTL0_Register_Masks */


/* RSTCTL0 - Peripheral instance base addresses */
/** Peripheral RSTCTL0 base address */
#define RSTCTL0_BASE                             (0x40000000u)
/** Peripheral RSTCTL0 base pointer */
#define RSTCTL0                                  ((RSTCTL0_Type *)RSTCTL0_BASE)
/** Array initializer of RSTCTL0 peripheral base addresses */
#define RSTCTL0_BASE_ADDRS                       { RSTCTL0_BASE }
/** Array initializer of RSTCTL0 peripheral base pointers */
#define RSTCTL0_BASE_PTRS                        { RSTCTL0 }

/*!
 * @}
 */ /* end of group RSTCTL0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RSTCTL1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL1_Peripheral_Access_Layer RSTCTL1 Peripheral Access Layer
 * @{
 */

/** RSTCTL1 - Register Layout Typedef */
typedef struct {
  __I  uint32_t SYSRSTSTAT;                        /**< System Reset Status Register, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t PRSTCTL0;                          /**< Peripheral Reset Control Register 0, offset: 0x10 */
  __IO uint32_t PRSTCTL1;                          /**< Peripheral Reset Control Register 1, offset: 0x14 */
  __IO uint32_t PRSTCTL2;                          /**< Peripheral Reset Control Register 2, offset: 0x18 */
       uint8_t RESERVED_1[36];
  __O  uint32_t PRSTCTL0_SET;                      /**< Peripheral Reset Control Register 0 SET, offset: 0x40 */
  __O  uint32_t PRSTCTL1_SET;                      /**< Peripheral Reset Control Register 1 SET, offset: 0x44 */
  __O  uint32_t PRSTCTL2_SET;                      /**< Peripheral Reset Control Register 2 SET, offset: 0x48 */
       uint8_t RESERVED_2[36];
  __O  uint32_t PRSTCTL0_CLR;                      /**< Peripheral Reset Control Register 0 CLR, offset: 0x70 */
  __O  uint32_t PRSTCTL1_CLR;                      /**< Peripheral Reset Control Register 1 CLR, offset: 0x74 */
  __O  uint32_t PRSTCTL2_CLR;                      /**< Peripheral Reset Control Register 2 CLR, offset: 0x78 */
} RSTCTL1_Type;

/* ----------------------------------------------------------------------------
   -- RSTCTL1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RSTCTL1_Register_Masks RSTCTL1 Register Masks
 * @{
 */

/*! @name SYSRSTSTAT - System Reset Status Register */
/*! @{ */
#define RSTCTL1_SYSRSTSTAT_VDD_POR_MASK          (0x1U)
#define RSTCTL1_SYSRSTSTAT_VDD_POR_SHIFT         (0U)
/*! VDD_POR - VDD Power-On Reset (POR) was detected
 *  0b0..No VDD POR event is detected
 *  0b1..VDD POR event was detected
 */
#define RSTCTL1_SYSRSTSTAT_VDD_POR(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_VDD_POR_SHIFT)) & RSTCTL1_SYSRSTSTAT_VDD_POR_MASK)
#define RSTCTL1_SYSRSTSTAT_PAD_RESET_MASK        (0x10U)
#define RSTCTL1_SYSRSTSTAT_PAD_RESET_SHIFT       (4U)
/*! PAD_RESET - PAD reset was detected
 *  0b0..No PAD event is detected
 *  0b1..PAD reset event was detected
 */
#define RSTCTL1_SYSRSTSTAT_PAD_RESET(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_PAD_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_PAD_RESET_MASK)
#define RSTCTL1_SYSRSTSTAT_ARM_RESET_MASK        (0x20U)
#define RSTCTL1_SYSRSTSTAT_ARM_RESET_SHIFT       (5U)
/*! ARM_RESET - ARM reset was detected
 *  0b0..No ARM reset event is detected
 *  0b1..ARM reset was detected
 */
#define RSTCTL1_SYSRSTSTAT_ARM_RESET(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_ARM_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_ARM_RESET_MASK)
#define RSTCTL1_SYSRSTSTAT_WDT0_RESET_MASK       (0x40U)
#define RSTCTL1_SYSRSTSTAT_WDT0_RESET_SHIFT      (6U)
/*! WDT0_RESET - WDT0 reset was detected
 *  0b0..No WDT0 reset event is detected
 *  0b1..WDT0 reset was detected
 */
#define RSTCTL1_SYSRSTSTAT_WDT0_RESET(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_WDT0_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_WDT0_RESET_MASK)
#define RSTCTL1_SYSRSTSTAT_WDT1_RESET_MASK       (0x80U)
#define RSTCTL1_SYSRSTSTAT_WDT1_RESET_SHIFT      (7U)
/*! WDT1_RESET - WDT1 reset was detected
 *  0b0..No WDT1 reset event is detected
 *  0b1..WDT1 reset was detected
 */
#define RSTCTL1_SYSRSTSTAT_WDT1_RESET(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_SYSRSTSTAT_WDT1_RESET_SHIFT)) & RSTCTL1_SYSRSTSTAT_WDT1_RESET_MASK)
/*! @} */

/*! @name PRSTCTL0 - Peripheral Reset Control Register 0 */
/*! @{ */
#define RSTCTL1_PRSTCTL0_FLEXCOMM0_MASK          (0x100U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM0_SHIFT         (8U)
/*! FLEXCOMM0 - Flexcomm0 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM0_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM0_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM1_MASK          (0x200U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM1_SHIFT         (9U)
/*! FLEXCOMM1 - Flexcomm1 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM1_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM1_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM2_MASK          (0x400U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM2_SHIFT         (10U)
/*! FLEXCOMM2 - Flexcomm2 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM2(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM2_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM2_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM3_MASK          (0x800U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM3_SHIFT         (11U)
/*! FLEXCOMM3 - Flexcomm3 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM3(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM3_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM3_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM4_MASK          (0x1000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM4_SHIFT         (12U)
/*! FLEXCOMM4 - Flexcomm4 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM4(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM4_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM4_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM5_MASK          (0x2000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM5_SHIFT         (13U)
/*! FLEXCOMM5 - Flexcomm5 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM5(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM5_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM5_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM6_MASK          (0x4000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM6_SHIFT         (14U)
/*! FLEXCOMM6 - Flexcomm6 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM6(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM6_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM6_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM7_MASK          (0x8000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM7_SHIFT         (15U)
/*! FLEXCOMM7 - Flexcomm7 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM7(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM7_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM7_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM8_MASK          (0x10000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM8_SHIFT         (16U)
/*! FLEXCOMM8 - Flexcomm8 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM8(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM8_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM8_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM9_MASK          (0x20000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM9_SHIFT         (17U)
/*! FLEXCOMM9 - Flexcomm9 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM9(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM9_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM9_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM10_MASK         (0x40000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM10_SHIFT        (18U)
/*! FLEXCOMM10 - Flexcomm10 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM10(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM10_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM10_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM11_MASK         (0x80000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM11_SHIFT        (19U)
/*! FLEXCOMM11 - Flexcomm11 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM11(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM11_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM11_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM12_MASK         (0x100000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM12_SHIFT        (20U)
/*! FLEXCOMM12 - Flexcomm12 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM12(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM12_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM12_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM13_MASK         (0x200000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM13_SHIFT        (21U)
/*! FLEXCOMM13 - Flexcomm13 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM13(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM13_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM13_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM14_MASK         (0x400000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM14_SHIFT        (22U)
/*! FLEXCOMM14 - Flexcomm14 SPI0 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM14(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM14_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM14_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_MASK     (0x800000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_SHIFT    (23U)
/*! FLEXCOMM15_I2C - Flexcomm15 I2C reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM15_I2C_MASK)
#define RSTCTL1_PRSTCTL0_DMIC0_MASK              (0x1000000U)
#define RSTCTL1_PRSTCTL0_DMIC0_SHIFT             (24U)
/*! DMIC0 - DMIC0 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_DMIC0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_DMIC0_MASK)
#define RSTCTL1_PRSTCTL0_FLEXCOMM16_MASK         (0x2000000U)
#define RSTCTL1_PRSTCTL0_FLEXCOMM16_SHIFT        (25U)
/*! FLEXCOMM16 - Flexcomm SPI reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXCOMM16(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXCOMM16_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXCOMM16_MASK)
#define RSTCTL1_PRSTCTL0_OSEVENT_TIMER_MASK      (0x8000000U)
#define RSTCTL1_PRSTCTL0_OSEVENT_TIMER_SHIFT     (27U)
/*! OSEVENT_TIMER - OSEVENT Timer reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_OSEVENT_TIMER(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_OSEVENT_TIMER_SHIFT)) & RSTCTL1_PRSTCTL0_OSEVENT_TIMER_MASK)
#define RSTCTL1_PRSTCTL0_FLEXIO_MASK             (0x20000000U)
#define RSTCTL1_PRSTCTL0_FLEXIO_SHIFT            (29U)
/*! FLEXIO - FLEXIO reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL0_FLEXIO(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_FLEXIO_SHIFT)) & RSTCTL1_PRSTCTL0_FLEXIO_MASK)
/*! @} */

/*! @name PRSTCTL1 - Peripheral Reset Control Register 1 */
/*! @{ */
#define RSTCTL1_PRSTCTL1_HSGPIO0_MASK            (0x1U)
#define RSTCTL1_PRSTCTL1_HSGPIO0_SHIFT           (0U)
/*! HSGPIO0 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO0(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO0_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO1_MASK            (0x2U)
#define RSTCTL1_PRSTCTL1_HSGPIO1_SHIFT           (1U)
/*! HSGPIO1 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO1(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO1_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO2_MASK            (0x4U)
#define RSTCTL1_PRSTCTL1_HSGPIO2_SHIFT           (2U)
/*! HSGPIO2 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO2(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO2_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO2_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO3_MASK            (0x8U)
#define RSTCTL1_PRSTCTL1_HSGPIO3_SHIFT           (3U)
/*! HSGPIO3 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO3(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO3_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO3_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO4_MASK            (0x10U)
#define RSTCTL1_PRSTCTL1_HSGPIO4_SHIFT           (4U)
/*! HSGPIO4 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO4(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO4_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO4_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO5_MASK            (0x20U)
#define RSTCTL1_PRSTCTL1_HSGPIO5_SHIFT           (5U)
/*! HSGPIO5 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO5(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO5_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO5_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO6_MASK            (0x40U)
#define RSTCTL1_PRSTCTL1_HSGPIO6_SHIFT           (6U)
/*! HSGPIO6 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO6(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO6_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO6_MASK)
#define RSTCTL1_PRSTCTL1_HSGPIO7_MASK            (0x80U)
#define RSTCTL1_PRSTCTL1_HSGPIO7_SHIFT           (7U)
/*! HSGPIO7 - HSGPIO[7:0] reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_HSGPIO7(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_HSGPIO7_SHIFT)) & RSTCTL1_PRSTCTL1_HSGPIO7_MASK)
#define RSTCTL1_PRSTCTL1_CRC_MASK                (0x10000U)
#define RSTCTL1_PRSTCTL1_CRC_SHIFT               (16U)
/*! CRC - CRC reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_CRC(x)                  (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_CRC_MASK)
#define RSTCTL1_PRSTCTL1_DMAC0_MASK              (0x800000U)
#define RSTCTL1_PRSTCTL1_DMAC0_SHIFT             (23U)
/*! DMAC0 - DMAC reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_DMAC0(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_DMAC0_SHIFT)) & RSTCTL1_PRSTCTL1_DMAC0_MASK)
#define RSTCTL1_PRSTCTL1_DMAC1_MASK              (0x1000000U)
#define RSTCTL1_PRSTCTL1_DMAC1_SHIFT             (24U)
/*! DMAC1 - DMAC reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_DMAC1(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_DMAC1_SHIFT)) & RSTCTL1_PRSTCTL1_DMAC1_MASK)
#define RSTCTL1_PRSTCTL1_MU_MASK                 (0x10000000U)
#define RSTCTL1_PRSTCTL1_MU_SHIFT                (28U)
/*! MU - MU reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_MU(x)                   (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_MU_SHIFT)) & RSTCTL1_PRSTCTL1_MU_MASK)
#define RSTCTL1_PRSTCTL1_SEMA_MASK               (0x20000000U)
#define RSTCTL1_PRSTCTL1_SEMA_SHIFT              (29U)
/*! SEMA - SEMA reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_SEMA(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SEMA_SHIFT)) & RSTCTL1_PRSTCTL1_SEMA_MASK)
#define RSTCTL1_PRSTCTL1_FREQME_MASK             (0x80000000U)
#define RSTCTL1_PRSTCTL1_FREQME_SHIFT            (31U)
/*! FREQME - FREQME reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL1_FREQME(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_FREQME_MASK)
/*! @} */

/*! @name PRSTCTL2 - Peripheral Reset Control Register 2 */
/*! @{ */
#define RSTCTL1_PRSTCTL2_CT32BIT0_MASK           (0x1U)
#define RSTCTL1_PRSTCTL2_CT32BIT0_SHIFT          (0U)
/*! CT32BIT0
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_CT32BIT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT0_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT0_MASK)
#define RSTCTL1_PRSTCTL2_CT32BIT1_MASK           (0x2U)
#define RSTCTL1_PRSTCTL2_CT32BIT1_SHIFT          (1U)
/*! CT32BIT1
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_CT32BIT1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT1_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT1_MASK)
#define RSTCTL1_PRSTCTL2_CT32BIT2_MASK           (0x4U)
#define RSTCTL1_PRSTCTL2_CT32BIT2_SHIFT          (2U)
/*! CT32BIT2
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_CT32BIT2(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT2_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT2_MASK)
#define RSTCTL1_PRSTCTL2_CT32BIT3_MASK           (0x8U)
#define RSTCTL1_PRSTCTL2_CT32BIT3_SHIFT          (3U)
/*! CT32BIT3
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_CT32BIT3(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT3_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT3_MASK)
#define RSTCTL1_PRSTCTL2_CT32BIT4_MASK           (0x10U)
#define RSTCTL1_PRSTCTL2_CT32BIT4_SHIFT          (4U)
/*! CT32BIT4
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_CT32BIT4(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CT32BIT4_SHIFT)) & RSTCTL1_PRSTCTL2_CT32BIT4_MASK)
#define RSTCTL1_PRSTCTL2_MRT0_MASK               (0x100U)
#define RSTCTL1_PRSTCTL2_MRT0_SHIFT              (8U)
/*! MRT0 - MRT0 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_MRT0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_MRT0_SHIFT)) & RSTCTL1_PRSTCTL2_MRT0_MASK)
#define RSTCTL1_PRSTCTL2_WWDT1_MASK              (0x400U)
#define RSTCTL1_PRSTCTL2_WWDT1_SHIFT             (10U)
/*! WWDT1 - WWDT1 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_WWDT1(x)                (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_WWDT1_SHIFT)) & RSTCTL1_PRSTCTL2_WWDT1_MASK)
#define RSTCTL1_PRSTCTL2_I3C0_MASK               (0x10000U)
#define RSTCTL1_PRSTCTL2_I3C0_SHIFT              (16U)
/*! I3C0 - I3C0 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_I3C0(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_I3C0_SHIFT)) & RSTCTL1_PRSTCTL2_I3C0_MASK)
#define RSTCTL1_PRSTCTL2_I3C1_MASK               (0x20000U)
#define RSTCTL1_PRSTCTL2_I3C1_SHIFT              (17U)
/*! I3C1 - I3C1 reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_I3C1(x)                 (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_I3C1_SHIFT)) & RSTCTL1_PRSTCTL2_I3C1_MASK)
#define RSTCTL1_PRSTCTL2_GPIOINTCTL_MASK         (0x40000000U)
#define RSTCTL1_PRSTCTL2_GPIOINTCTL_SHIFT        (30U)
/*! GPIOINTCTL - GPIOINTCTL reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_GPIOINTCTL(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_GPIOINTCTL_SHIFT)) & RSTCTL1_PRSTCTL2_GPIOINTCTL_MASK)
#define RSTCTL1_PRSTCTL2_PIMCTL_MASK             (0x80000000U)
#define RSTCTL1_PRSTCTL2_PIMCTL_SHIFT            (31U)
/*! PIMCTL - INPUTMUX reset control
 *  0b1..Set Reset
 *  0b0..Clear Reset
 */
#define RSTCTL1_PRSTCTL2_PIMCTL(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_PIMCTL_SHIFT)) & RSTCTL1_PRSTCTL2_PIMCTL_MASK)
/*! @} */

/*! @name PRSTCTL0_SET - Peripheral Reset Control Register 0 SET */
/*! @{ */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_MASK      (0x100U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_SHIFT     (8U)
/*! FLEXCOMM0 - Flexcomm0 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM0(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM0_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_MASK      (0x200U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_SHIFT     (9U)
/*! FLEXCOMM1 - Flexcomm1 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM1(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM1_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_MASK      (0x400U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_SHIFT     (10U)
/*! FLEXCOMM2 - Flexcomm2 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM2(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM2_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_MASK      (0x800U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_SHIFT     (11U)
/*! FLEXCOMM3 - Flexcomm3 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM3(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM3_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_MASK      (0x1000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_SHIFT     (12U)
/*! FLEXCOMM4 - Flexcomm4 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM4(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM4_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_MASK      (0x2000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_SHIFT     (13U)
/*! FLEXCOMM5 - Flexcomm5 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM5(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM5_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_MASK      (0x4000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_SHIFT     (14U)
/*! FLEXCOMM6 - Flexcomm6 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM6(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM6_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_MASK      (0x8000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_SHIFT     (15U)
/*! FLEXCOMM7 - Flexcomm7 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM7(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM7_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_MASK      (0x10000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_SHIFT     (16U)
/*! FLEXCOMM8 - Flexcomm8 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM8(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM8_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_MASK      (0x20000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_SHIFT     (17U)
/*! FLEXCOMM9 - Flexcomm9 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM9(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM9_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_MASK     (0x40000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_SHIFT    (18U)
/*! FLEXCOMM10 - Flexcomm10 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM10(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM10_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_MASK     (0x80000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_SHIFT    (19U)
/*! FLEXCOMM11 - Flexcomm11 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM11(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM11_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_MASK     (0x100000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_SHIFT    (20U)
/*! FLEXCOMM12 - Flexcomm12 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM12(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM12_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_MASK     (0x200000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_SHIFT    (21U)
/*! FLEXCOMM13 - Flexcomm13 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM13(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM13_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_MASK     (0x400000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_SHIFT    (22U)
/*! FLEXCOMM14 - Flexcomm14 SPI0 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM14(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM14_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_MASK (0x800000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_SHIFT (23U)
/*! FLEXCOMM15_I2C - Flexcomm15 I2C reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM15_I2C_MASK)
#define RSTCTL1_PRSTCTL0_SET_DMIC0_MASK          (0x1000000U)
#define RSTCTL1_PRSTCTL0_SET_DMIC0_SHIFT         (24U)
/*! DMIC0 - DMIC0 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_DMIC0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_SET_DMIC0_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_MASK     (0x2000000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_SHIFT    (25U)
/*! FLEXCOMM16 - Flexcomm16 SPI1 reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXCOMM16(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXCOMM16_MASK)
#define RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_MASK  (0x8000000U)
#define RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_SHIFT (27U)
/*! OSEVENT_TIMER - OSEVENT Timer reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_SHIFT)) & RSTCTL1_PRSTCTL0_SET_OSEVENT_TIMER_MASK)
#define RSTCTL1_PRSTCTL0_SET_FLEXIO_MASK         (0x20000000U)
#define RSTCTL1_PRSTCTL0_SET_FLEXIO_SHIFT        (29U)
/*! FLEXIO - FEXIO reset set
 *  0b1..Sets the PRSTCTL0 Bit
 *  0b0..No Effect
 */
#define RSTCTL1_PRSTCTL0_SET_FLEXIO(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_SET_FLEXIO_SHIFT)) & RSTCTL1_PRSTCTL0_SET_FLEXIO_MASK)
/*! @} */

/*! @name PRSTCTL1_SET - Peripheral Reset Control Register 1 SET */
/*! @{ */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO0_MASK        (0x1U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO0_SHIFT       (0U)
/*! HSGPIO0 - HSGPIO0 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO0_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO1_MASK        (0x2U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO1_SHIFT       (1U)
/*! HSGPIO1 - HSGPIO1 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO1_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO2_MASK        (0x4U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO2_SHIFT       (2U)
/*! HSGPIO2 - HSGPIO2 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO2(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO2_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO2_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO3_MASK        (0x8U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO3_SHIFT       (3U)
/*! HSGPIO3 - HSGPIO3 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO3(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO3_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO3_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO4_MASK        (0x10U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO4_SHIFT       (4U)
/*! HSGPIO4 - HSGPIO4 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO4(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO4_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO4_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO5_MASK        (0x20U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO5_SHIFT       (5U)
/*! HSGPIO5 - HSGPIO5 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO5(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO5_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO5_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO6_MASK        (0x40U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO6_SHIFT       (6U)
/*! HSGPIO6 - HSGPIO6 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO6(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO6_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO6_MASK)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO7_MASK        (0x80U)
#define RSTCTL1_PRSTCTL1_SET_HSGPIO7_SHIFT       (7U)
/*! HSGPIO7 - HSGPIO7 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_HSGPIO7(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_HSGPIO7_SHIFT)) & RSTCTL1_PRSTCTL1_SET_HSGPIO7_MASK)
#define RSTCTL1_PRSTCTL1_SET_CRC_MASK            (0x10000U)
#define RSTCTL1_PRSTCTL1_SET_CRC_SHIFT           (16U)
/*! CRC - CRC reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_CRC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_SET_CRC_MASK)
#define RSTCTL1_PRSTCTL1_SET_DMAC0_MASK          (0x800000U)
#define RSTCTL1_PRSTCTL1_SET_DMAC0_SHIFT         (23U)
/*! DMAC0 - DMAC0 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_DMAC0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_DMAC0_SHIFT)) & RSTCTL1_PRSTCTL1_SET_DMAC0_MASK)
#define RSTCTL1_PRSTCTL1_SET_DMAC1_MASK          (0x1000000U)
#define RSTCTL1_PRSTCTL1_SET_DMAC1_SHIFT         (24U)
/*! DMAC1 - DMAC1 reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_DMAC1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_DMAC1_SHIFT)) & RSTCTL1_PRSTCTL1_SET_DMAC1_MASK)
#define RSTCTL1_PRSTCTL1_SET_MU_MASK             (0x10000000U)
#define RSTCTL1_PRSTCTL1_SET_MU_SHIFT            (28U)
/*! MU - MU reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_MU(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_MU_SHIFT)) & RSTCTL1_PRSTCTL1_SET_MU_MASK)
#define RSTCTL1_PRSTCTL1_SET_SEMA_MASK           (0x20000000U)
#define RSTCTL1_PRSTCTL1_SET_SEMA_SHIFT          (29U)
/*! SEMA - SEMA reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_SEMA(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_SEMA_SHIFT)) & RSTCTL1_PRSTCTL1_SET_SEMA_MASK)
#define RSTCTL1_PRSTCTL1_SET_FREQME_MASK         (0x80000000U)
#define RSTCTL1_PRSTCTL1_SET_FREQME_SHIFT        (31U)
/*! FREQME - FREQME reset set
 *  0b1..Sets the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_SET_FREQME(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_SET_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_SET_FREQME_MASK)
/*! @} */

/*! @name PRSTCTL2_SET - Peripheral Reset Control Register 2 SET */
/*! @{ */
#define RSTCTL1_PRSTCTL2_SET_CT32BIT0_MASK       (0x1U)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT0_SHIFT      (0U)
/*! CT32BIT0 - CT32BIT0 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_CT32BIT0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT0_MASK)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT1_MASK       (0x2U)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT1_SHIFT      (1U)
/*! CT32BIT1 - CT32BIT1 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_CT32BIT1(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT1_MASK)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT2_MASK       (0x4U)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT2_SHIFT      (2U)
/*! CT32BIT2 - CT32BIT2 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_CT32BIT2(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT2_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT2_MASK)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT3_MASK       (0x8U)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT3_SHIFT      (3U)
/*! CT32BIT3 - CT32BIT3 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_CT32BIT3(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT3_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT3_MASK)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT4_MASK       (0x10U)
#define RSTCTL1_PRSTCTL2_SET_CT32BIT4_SHIFT      (4U)
/*! CT32BIT4 - CT32BIT4 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_CT32BIT4(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_CT32BIT4_SHIFT)) & RSTCTL1_PRSTCTL2_SET_CT32BIT4_MASK)
#define RSTCTL1_PRSTCTL2_SET_MRT0_MASK           (0x100U)
#define RSTCTL1_PRSTCTL2_SET_MRT0_SHIFT          (8U)
/*! MRT0 - MRT0 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_MRT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_MRT0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_MRT0_MASK)
#define RSTCTL1_PRSTCTL2_SET_WWDT1_MASK          (0x400U)
#define RSTCTL1_PRSTCTL2_SET_WWDT1_SHIFT         (10U)
/*! WWDT1 - WWDT1 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_WWDT1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_WWDT1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_WWDT1_MASK)
#define RSTCTL1_PRSTCTL2_SET_I3C0_MASK           (0x10000U)
#define RSTCTL1_PRSTCTL2_SET_I3C0_SHIFT          (16U)
/*! I3C0 - I3C0 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_I3C0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_I3C0_SHIFT)) & RSTCTL1_PRSTCTL2_SET_I3C0_MASK)
#define RSTCTL1_PRSTCTL2_SET_I3C1_MASK           (0x20000U)
#define RSTCTL1_PRSTCTL2_SET_I3C1_SHIFT          (17U)
/*! I3C1 - I3C1 reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_I3C1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_I3C1_SHIFT)) & RSTCTL1_PRSTCTL2_SET_I3C1_MASK)
#define RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_MASK     (0x40000000U)
#define RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_SHIFT    (30U)
/*! GPIOINTCTL - GPIOINTCTL reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_GPIOINTCTL(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_SHIFT)) & RSTCTL1_PRSTCTL2_SET_GPIOINTCTL_MASK)
#define RSTCTL1_PRSTCTL2_SET_PIMCTL_MASK         (0x80000000U)
#define RSTCTL1_PRSTCTL2_SET_PIMCTL_SHIFT        (31U)
/*! PIMCTL - PIMCTL reset set
 *  0b1..Sets the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_SET_PIMCTL(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_SET_PIMCTL_SHIFT)) & RSTCTL1_PRSTCTL2_SET_PIMCTL_MASK)
/*! @} */

/*! @name PRSTCTL0_CLR - Peripheral Reset Control Register 0 CLR */
/*! @{ */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_MASK      (0x100U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_SHIFT     (8U)
/*! FLEXCOMM0 - Flexcomm0 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM0_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_MASK      (0x200U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_SHIFT     (9U)
/*! FLEXCOMM1 - Flexcomm1 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM1_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_MASK      (0x400U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_SHIFT     (10U)
/*! FLEXCOMM2 - Flexcomm2 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM2_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_MASK      (0x800U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_SHIFT     (11U)
/*! FLEXCOMM3 - Flexcomm3 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM3_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_MASK      (0x1000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_SHIFT     (12U)
/*! FLEXCOMM4 - Flexcomm4 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM4_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_MASK      (0x2000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_SHIFT     (13U)
/*! FLEXCOMM5 - Flexcomm5 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM5_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_MASK      (0x4000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_SHIFT     (14U)
/*! FLEXCOMM6 - Flexcomm6 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM6_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_MASK      (0x8000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_SHIFT     (15U)
/*! FLEXCOMM7 - Flexcomm7 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM7_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_MASK      (0x10000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_SHIFT     (16U)
/*! FLEXCOMM8 - Flexcomm8 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM8_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_MASK      (0x20000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_SHIFT     (17U)
/*! FLEXCOMM9 - Flexcomm9 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9(x)        (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM9_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_MASK     (0x40000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_SHIFT    (18U)
/*! FLEXCOMM10 - Flexcomm10 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM10_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_MASK     (0x80000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_SHIFT    (19U)
/*! FLEXCOMM11 - Flexcomm11 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM11_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_MASK     (0x100000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_SHIFT    (20U)
/*! FLEXCOMM12 - Flexcomm12 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM12_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_MASK     (0x200000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_SHIFT    (21U)
/*! FLEXCOMM13 - Flexcomm13 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM13_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_MASK     (0x400000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_SHIFT    (22U)
/*! FLEXCOMM14 - FLexcomm SPI0 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM14_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_MASK (0x800000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_SHIFT (23U)
/*! FLEXCOMM15_I2C - Flexcomm I2C reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C(x)   (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM15_I2C_MASK)
#define RSTCTL1_PRSTCTL0_CLR_DMIC0_MASK          (0x1000000U)
#define RSTCTL1_PRSTCTL0_CLR_DMIC0_SHIFT         (24U)
/*! DMIC0 - DMIC0 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_DMIC0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_DMIC0_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_DMIC0_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_MASK     (0x2000000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_SHIFT    (25U)
/*! FLEXCOMM16 - Flexcomm SPI1 reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXCOMM16_MASK)
#define RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_MASK  (0x8000000U)
#define RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_SHIFT (27U)
/*! OSEVENT_TIMER - OSEVENT Timer reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER(x)    (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_OSEVENT_TIMER_MASK)
#define RSTCTL1_PRSTCTL0_CLR_FLEXIO_MASK         (0x20000000U)
#define RSTCTL1_PRSTCTL0_CLR_FLEXIO_SHIFT        (29U)
/*! FLEXIO - FLEXIO reset clear
 *  0b1..Clears the PRSTCTL0 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL0_CLR_FLEXIO(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL0_CLR_FLEXIO_SHIFT)) & RSTCTL1_PRSTCTL0_CLR_FLEXIO_MASK)
/*! @} */

/*! @name PRSTCTL1_CLR - Peripheral Reset Control Register 1 CLR */
/*! @{ */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0_MASK        (0x1U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0_SHIFT       (0U)
/*! HSGPIO0 - HSGPIO0 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO0(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO0_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO0_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1_MASK        (0x2U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1_SHIFT       (1U)
/*! HSGPIO1 - HSGPIO1 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO1(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO1_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO1_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO2_MASK        (0x4U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO2_SHIFT       (2U)
/*! HSGPIO2 - HSGPIO2 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO2(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO2_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO2_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO3_MASK        (0x8U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO3_SHIFT       (3U)
/*! HSGPIO3 - HSGPIO3 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO3(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO3_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO3_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO4_MASK        (0x10U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO4_SHIFT       (4U)
/*! HSGPIO4 - HSGPIO4 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO4(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO4_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO4_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO5_MASK        (0x20U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO5_SHIFT       (5U)
/*! HSGPIO5 - HSGPIO5 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO5(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO5_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO5_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO6_MASK        (0x40U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO6_SHIFT       (6U)
/*! HSGPIO6 - HSGPIO6 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO6(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO6_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO6_MASK)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO7_MASK        (0x80U)
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO7_SHIFT       (7U)
/*! HSGPIO7 - HSGPIO7 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_HSGPIO7(x)          (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_HSGPIO7_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_HSGPIO7_MASK)
#define RSTCTL1_PRSTCTL1_CLR_CRC_MASK            (0x10000U)
#define RSTCTL1_PRSTCTL1_CLR_CRC_SHIFT           (16U)
/*! CRC - CRC reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_CRC(x)              (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_CRC_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_CRC_MASK)
#define RSTCTL1_PRSTCTL1_CLR_DMAC0_MASK          (0x800000U)
#define RSTCTL1_PRSTCTL1_CLR_DMAC0_SHIFT         (23U)
/*! DMAC0 - DMAC0 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_DMAC0(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_DMAC0_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_DMAC0_MASK)
#define RSTCTL1_PRSTCTL1_CLR_DMAC1_MASK          (0x1000000U)
#define RSTCTL1_PRSTCTL1_CLR_DMAC1_SHIFT         (24U)
/*! DMAC1 - DMAC1 reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_DMAC1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_DMAC1_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_DMAC1_MASK)
#define RSTCTL1_PRSTCTL1_CLR_MU_MASK             (0x10000000U)
#define RSTCTL1_PRSTCTL1_CLR_MU_SHIFT            (28U)
/*! MU - MU reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_MU(x)               (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_MU_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_MU_MASK)
#define RSTCTL1_PRSTCTL1_CLR_SEMA_MASK           (0x20000000U)
#define RSTCTL1_PRSTCTL1_CLR_SEMA_SHIFT          (29U)
/*! SEMA - SMEA reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_SEMA(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_SEMA_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_SEMA_MASK)
#define RSTCTL1_PRSTCTL1_CLR_FREQME_MASK         (0x80000000U)
#define RSTCTL1_PRSTCTL1_CLR_FREQME_SHIFT        (31U)
/*! FREQME - FREQME reset clear
 *  0b1..Clears the PRSTCTL1 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL1_CLR_FREQME(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL1_CLR_FREQME_SHIFT)) & RSTCTL1_PRSTCTL1_CLR_FREQME_MASK)
/*! @} */

/*! @name PRSTCTL2_CLR - Peripheral Reset Control Register 2 CLR */
/*! @{ */
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT0_MASK       (0x1U)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT0_SHIFT      (0U)
/*! CT32BIT0 - CT32BIT0 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT0(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT0_MASK)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT1_MASK       (0x2U)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT1_SHIFT      (1U)
/*! CT32BIT1 - CT32BIT1 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT1(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT1_MASK)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT2_MASK       (0x4U)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT2_SHIFT      (2U)
/*! CT32BIT2 - CT32BIT2 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT2(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT2_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT2_MASK)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT3_MASK       (0x8U)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT3_SHIFT      (3U)
/*! CT32BIT3 - CT32BIT3 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT3(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT3_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT3_MASK)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT4_MASK       (0x10U)
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT4_SHIFT      (4U)
/*! CT32BIT4 - CT32BIT4 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_CT32BIT4(x)         (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_CT32BIT4_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_CT32BIT4_MASK)
#define RSTCTL1_PRSTCTL2_CLR_MRT0_MASK           (0x100U)
#define RSTCTL1_PRSTCTL2_CLR_MRT0_SHIFT          (8U)
/*! MRT0 - MRT0 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_MRT0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_MRT0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_MRT0_MASK)
#define RSTCTL1_PRSTCTL2_CLR_WWDT1_MASK          (0x400U)
#define RSTCTL1_PRSTCTL2_CLR_WWDT1_SHIFT         (10U)
/*! WWDT1 - WWDT1 reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_WWDT1(x)            (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_WWDT1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_WWDT1_MASK)
#define RSTCTL1_PRSTCTL2_CLR_I3C0_MASK           (0x10000U)
#define RSTCTL1_PRSTCTL2_CLR_I3C0_SHIFT          (16U)
/*! I3C0 - I3C[1:0] reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_I3C0(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_I3C0_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_I3C0_MASK)
#define RSTCTL1_PRSTCTL2_CLR_I3C1_MASK           (0x20000U)
#define RSTCTL1_PRSTCTL2_CLR_I3C1_SHIFT          (17U)
/*! I3C1 - I3C[1:0] reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_I3C1(x)             (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_I3C1_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_I3C1_MASK)
#define RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_MASK     (0x40000000U)
#define RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_SHIFT    (30U)
/*! GPIOINTCTL - GPIOINTCTL reset clear
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL(x)       (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_GPIOINTCTL_MASK)
#define RSTCTL1_PRSTCTL2_CLR_PIMCTL_MASK         (0x80000000U)
#define RSTCTL1_PRSTCTL2_CLR_PIMCTL_SHIFT        (31U)
/*! PIMCTL
 *  0b1..Clears the PRSTCTL2 Bit
 *  0b0..No effect
 */
#define RSTCTL1_PRSTCTL2_CLR_PIMCTL(x)           (((uint32_t)(((uint32_t)(x)) << RSTCTL1_PRSTCTL2_CLR_PIMCTL_SHIFT)) & RSTCTL1_PRSTCTL2_CLR_PIMCTL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group RSTCTL1_Register_Masks */


/* RSTCTL1 - Peripheral instance base addresses */
/** Peripheral RSTCTL1 base address */
#define RSTCTL1_BASE                             (0x40020000u)
/** Peripheral RSTCTL1 base pointer */
#define RSTCTL1                                  ((RSTCTL1_Type *)RSTCTL1_BASE)
/** Array initializer of RSTCTL1 peripheral base addresses */
#define RSTCTL1_BASE_ADDRS                       { RSTCTL1_BASE }
/** Array initializer of RSTCTL1 peripheral base pointers */
#define RSTCTL1_BASE_PTRS                        { RSTCTL1 }

/*!
 * @}
 */ /* end of group RSTCTL1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- RTC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
 * @{
 */

/** RTC - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< RTC Control, offset: 0x0 */
  __IO uint32_t MATCH;                             /**< RTC Match, offset: 0x4 */
  __IO uint32_t COUNT;                             /**< RTC Counter, offset: 0x8 */
  __IO uint32_t WAKE;                              /**< High-resolution/Wake-up Timer Control, offset: 0xC */
  __I  uint32_t SUBSEC;                            /**< RTC Sub-second Counter, offset: 0x10 */
       uint8_t RESERVED_0[44];
  __IO uint32_t GPREG[8];                          /**< General Purpose, array offset: 0x40, array step: 0x4 */
} RTC_Type;

/* ----------------------------------------------------------------------------
   -- RTC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup RTC_Register_Masks RTC Register Masks
 * @{
 */

/*! @name CTRL - RTC Control */
/*! @{ */
#define RTC_CTRL_SWRESET_MASK                    (0x1U)
#define RTC_CTRL_SWRESET_SHIFT                   (0U)
/*! SWRESET - Software Reset Control
 *  0b0..Not in reset. The RTC is not held in reset. Clear SWRESET before configuring or initiating any operation of the RTC.
 *  0b1..In reset. The RTC is held in reset. All registers in the RTC change to their reset value except OFD.
 */
#define RTC_CTRL_SWRESET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
#define RTC_CTRL_ALARM1HZ_MASK                   (0x4U)
#define RTC_CTRL_ALARM1HZ_SHIFT                  (2U)
/*! ALARM1HZ - RTC 1 Hz Timer Alarm Flag Status
 *  0b0..No match. No match condition has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.
 *  0b1..Match. The value in MATCH[MATVAL] equals the value in COUNT[VAL]. This flag generates an RTC alarm
 *       interrupt/wake-up request, RTC_ALARM, which can also wake up the device from any low power mode. Write 1 to
 *       clear.
 */
#define RTC_CTRL_ALARM1HZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
#define RTC_CTRL_WAKE1KHZ_MASK                   (0x8U)
#define RTC_CTRL_WAKE1KHZ_SHIFT                  (3U)
/*! WAKE1KHZ - RTC 1 kHz Timer Wake-up Flag Status
 *  0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.
 *  0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up
 *       interrupt request RTC-WAKE which can also wake up the device from any low power mode. Write 1 to clear.
 */
#define RTC_CTRL_WAKE1KHZ(x)                     (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
#define RTC_CTRL_ALARMDPD_EN_MASK                (0x10U)
#define RTC_CTRL_ALARMDPD_EN_SHIFT               (4U)
/*! ALARMDPD_EN - RTC 1 Hz Timer Alarm Enable for Deep Power-down
 *  0b0..Disable. A match on the 1 Hz RTC timer does not bring the device out of Deep Power-down mode.
 *  0b1..Enable. A match on the 1 Hz RTC timer brings the device out of Deep Power-down mode.
 */
#define RTC_CTRL_ALARMDPD_EN(x)                  (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
#define RTC_CTRL_WAKEDPD_EN_MASK                 (0x20U)
#define RTC_CTRL_WAKEDPD_EN_SHIFT                (5U)
/*! WAKEDPD_EN - RTC 1 kHz Timer Wake-up Enable for Deep Power-down
 *  0b0..Disable. A match on the 1 kHz RTC timer does not bring the device out of Deep Power-down mode.
 *  0b1..Enable. A match on the 1 kHz RTC timer brings the device out of Deep Power-down mode.
 */
#define RTC_CTRL_WAKEDPD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
#define RTC_CTRL_RTC1KHZ_EN_MASK                 (0x40U)
#define RTC_CTRL_RTC1KHZ_EN_SHIFT                (6U)
/*! RTC1KHZ_EN - RTC 1 kHz Clock Enable
 *  0b0..Disable. A match on the 1 kHz RTC timer does not bring the device out of Deep Power-down mode.
 *  0b1..Enable. The 1 kHz RTC timer is enabled.
 */
#define RTC_CTRL_RTC1KHZ_EN(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
#define RTC_CTRL_RTC_EN_MASK                     (0x80U)
#define RTC_CTRL_RTC_EN_SHIFT                    (7U)
/*! RTC_EN - RTC enable
 *  0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. RTC_EN should be
 *       0 when writing to load a value in the RTC counter (COUNT) register .
 *  0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. The first clock to the RTC counter
 *       occurs 1 s after RTC_EN is set. To also enable the high-resolution, 1 kHz clock, set CTRL[RTC1KHZ_EN] = 1.
 */
#define RTC_CTRL_RTC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
#define RTC_CTRL_RTC_OSC_PD_MASK                 (0x100U)
#define RTC_CTRL_RTC_OSC_PD_SHIFT                (8U)
/*! RTC_OSC_PD - The RTC Oscillator Enable
 *  0b0..Enable. The RTC oscillator is enabled. RTC_OSC_PD must be cleared for the RTC module to function.
 *  0b1..Shut Off. The RTC operation is disabled. The RTC oscillator is shut-off to limit power consumption.
 */
#define RTC_CTRL_RTC_OSC_PD(x)                   (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
#define RTC_CTRL_RTC_SUBSEC_ENA_MASK             (0x400U)
#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT            (10U)
/*! RTC_SUBSEC_ENA - 32-KHz Sub-second Counter Enable
 *  0b0..Disable. The sub-second counter (if implemented) is disabled. RTC_SUBSEC_ENA is cleared by a system-level
 *       POR or BOD reset or by an RTC_EN reset. On modules not equipped with a sub-second counter, RTC_SUBSEC_ENA
 *       will always read as 0.
 *  0b1..Enable. The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the
 *       first one-second interval after RTC_SUBSEC_ENA is set. RTC_SUBSEC_ENA can only be set after the RTC_EN
 *       has been set by a previous write operation. The RTC sub-second counter must be re-enabled whenever the chip
 *       exits Deep Power-down mode.
 */
#define RTC_CTRL_RTC_SUBSEC_ENA(x)               (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)
#define RTC_CTRL_RTC_OSC_loadcap_MASK            (0xF0000000U)
#define RTC_CTRL_RTC_OSC_loadcap_SHIFT           (28U)
/*! RTC_OSC_loadcap - Capacitive Load Selection
 */
#define RTC_CTRL_RTC_OSC_loadcap(x)              (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_loadcap_SHIFT)) & RTC_CTRL_RTC_OSC_loadcap_MASK)
/*! @} */

/*! @name MATCH - RTC Match */
/*! @{ */
#define RTC_MATCH_MATVAL_MASK                    (0xFFFFFFFFU)
#define RTC_MATCH_MATVAL_SHIFT                   (0U)
/*! MATVAL - Match Value
 */
#define RTC_MATCH_MATVAL(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
/*! @} */

/*! @name COUNT - RTC Counter */
/*! @{ */
#define RTC_COUNT_VAL_MASK                       (0xFFFFFFFFU)
#define RTC_COUNT_VAL_SHIFT                      (0U)
/*! VAL - Value
 */
#define RTC_COUNT_VAL(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
/*! @} */

/*! @name WAKE - High-resolution/Wake-up Timer Control */
/*! @{ */
#define RTC_WAKE_VAL_MASK                        (0xFFFFU)
#define RTC_WAKE_VAL_SHIFT                       (0U)
/*! VAL - Value
 */
#define RTC_WAKE_VAL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
/*! @} */

/*! @name SUBSEC - RTC Sub-second Counter */
/*! @{ */
#define RTC_SUBSEC_RTC_SUBSEC_MASK               (0x7FFFU)
#define RTC_SUBSEC_RTC_SUBSEC_SHIFT              (0U)
/*! RTC_SUBSEC - RTC Sub-second Counter
 */
#define RTC_SUBSEC_RTC_SUBSEC(x)                 (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_RTC_SUBSEC_SHIFT)) & RTC_SUBSEC_RTC_SUBSEC_MASK)
/*! @} */

/*! @name GPREG - General Purpose */
/*! @{ */
#define RTC_GPREG_GPDATA_MASK                    (0xFFFFFFFFU)
#define RTC_GPREG_GPDATA_SHIFT                   (0U)
/*! GPDATA - General Purpose Data
 */
#define RTC_GPREG_GPDATA(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
/*! @} */

/* The count of RTC_GPREG */
#define RTC_GPREG_COUNT                          (8U)


/*!
 * @}
 */ /* end of group RTC_Register_Masks */


/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE                                 (0x40030000u)
/** Peripheral RTC base pointer */
#define RTC                                      ((RTC_Type *)RTC_BASE)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS                           { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS                            { RTC }
/** Interrupt vectors for the RTC peripheral type */
#define RTC_IRQS                                 { RTC_IRQn }

/*!
 * @}
 */ /* end of group RTC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SCT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
 * @{
 */

/** SCT - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONFIG;                            /**< SCTimer Configuration, offset: 0x0 */
  __IO uint32_t CTRL;                              /**< SCT Control, offset: 0x4 */
  __IO uint32_t LIMIT;                             /**< SCT Limit Event Select, offset: 0x8 */
  __IO uint32_t HALT;                              /**< Halt Event Select, offset: 0xC */
  __IO uint32_t STOP;                              /**< Stop Event Select, offset: 0x10 */
  __IO uint32_t START;                             /**< Start Event Select, offset: 0x14 */
       uint8_t RESERVED_0[40];
  __IO uint32_t COUNT;                             /**< Counter, offset: 0x40 */
  __IO uint32_t STATE;                             /**< State, offset: 0x44 */
  __I  uint32_t INPUT;                             /**< Input, offset: 0x48 */
  __IO uint32_t REGMODE;                           /**< Match/Capture Mode, offset: 0x4C */
  __IO uint32_t OUTPUT;                            /**< Output, offset: 0x50 */
  __IO uint32_t OUTPUTDIRCTRL;                     /**< Output Counter Direction Control, offset: 0x54 */
  __IO uint32_t RES;                               /**< Output Conflict Resolution, offset: 0x58 */
  __IO uint32_t DMAREQ0;                           /**< DMA Request 0, offset: 0x5C */
  __IO uint32_t DMAREQ1;                           /**< DMA Request 1, offset: 0x60 */
       uint8_t RESERVED_1[140];
  __IO uint32_t EVEN;                              /**< Event Interrupt Enable, offset: 0xF0 */
  __IO uint32_t EVFLAG;                            /**< Event Flag, offset: 0xF4 */
  __IO uint32_t CONEN;                             /**< Conflict Interrupt Enable, offset: 0xF8 */
  __IO uint32_t CONFLAG;                           /**< Conflict Flag, offset: 0xFC */
  union {                                          /* offset: 0x100 */
    __IO uint32_t CAP[16];                           /**< Capture Value, array offset: 0x100, array step: 0x4 */
    __IO uint32_t MATCH[16];                         /**< Match Value, array offset: 0x100, array step: 0x4 */
  };
       uint8_t RESERVED_2[192];
  union {                                          /* offset: 0x200 */
    __IO uint32_t CAPCTRL[16];                       /**< Capture Control, array offset: 0x200, array step: 0x4 */
    __IO uint32_t MATCHREL[16];                      /**< Match Reload Value, array offset: 0x200, array step: 0x4 */
  };
       uint8_t RESERVED_3[192];
  struct {                                         /* offset: 0x300, array step: 0x8 */
    __IO uint32_t STATE;                             /**< Event n State, array offset: 0x300, array step: 0x8 */
    __IO uint32_t CTRL;                              /**< Event n Control, array offset: 0x304, array step: 0x8 */
  } EV[16];
       uint8_t RESERVED_4[384];
  struct {                                         /* offset: 0x500, array step: 0x8 */
    __IO uint32_t SET;                               /**< Output n Set, array offset: 0x500, array step: 0x8 */
    __IO uint32_t CLR;                               /**< Output n Clear, array offset: 0x504, array step: 0x8 */
  } OUT[10];
} SCT_Type;

/* ----------------------------------------------------------------------------
   -- SCT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SCT_Register_Masks SCT Register Masks
 * @{
 */

/*! @name CONFIG - SCTimer Configuration */
/*! @{ */
#define SCT_CONFIG_UNIFY_MASK                    (0x1U)
#define SCT_CONFIG_UNIFY_SHIFT                   (0U)
/*! UNIFY - SCT Operation
 *  0b0..Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.
 *  0b1..Unified counter. The SCT operates as a unified 32-bit counter.
 */
#define SCT_CONFIG_UNIFY(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
#define SCT_CONFIG_CLKMODE_MASK                  (0x6U)
#define SCT_CONFIG_CLKMODE_SHIFT                 (1U)
/*! CLKMODE - SCT Clock Mode
 *  0b00..System Clock Mode. The system clock clocks the entire SCT module including all counters and counter prescalers.
 *  0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are
 *        only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The
 *        minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the
 *        high-performance, sampled-clock mode.
 *  0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including all
 *        counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the
 *        clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.
 *  0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL
 *        field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system
 *        clock. The input clock rate must be at least half the system clock rate and can be the same or faster than
 *        the system clock.
 */
#define SCT_CONFIG_CLKMODE(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
#define SCT_CONFIG_CKSEL_MASK                    (0x78U)
#define SCT_CONFIG_CKSEL_SHIFT                   (3U)
/*! CKSEL - SCT Clock Select. The specific functionality of the designated input/edge is dependent
 *    on the CLKMODE bit selection in this register.
 *  0b0000..Rising edges on input 0
 *  0b0001..Falling edges on input 0
 *  0b0010..Rising edges on input 1
 *  0b0011..Falling edges on input 1
 *  0b0100..Rising edges on input 2
 *  0b0101..Falling edges on input 2
 *  0b0110..Rising edges on input 3
 *  0b0111..Falling edges on input 3
 *  0b1000..Rising edges on input 4
 *  0b1001..Falling edges on input 4
 *  0b1010..Rising edges on input 5
 *  0b1011..Falling edges on input 5
 *  0b1100..Rising edges on input 6
 *  0b1101..Falling edges on input 6
 *  0b1110..Rising edges on input 7
 *  0b1111..Falling edges on input 7
 */
#define SCT_CONFIG_CKSEL(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
#define SCT_CONFIG_NORELOAD_L_MASK               (0x80U)
#define SCT_CONFIG_NORELOAD_L_SHIFT              (7U)
/*! NORELOAD_L - No Reload Lower Match
 *  0b0..Reload. The default setting.
 *  0b1..No Reload. Prevents the lower match registers from being reloaded from their respective reload registers.
 */
#define SCT_CONFIG_NORELOAD_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK)
#define SCT_CONFIG_NORELOAD_H_MASK               (0x100U)
#define SCT_CONFIG_NORELOAD_H_SHIFT              (8U)
/*! NORELOAD_H - No Reload Higher Match
 *  0b0..Reload. The default setting.
 *  0b1..No Reload. Prevents the higher match registers from being reloaded from their respective reload registers.
 */
#define SCT_CONFIG_NORELOAD_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
#define SCT_CONFIG_INSYNC_MASK                   (0x1FE00U)
#define SCT_CONFIG_INSYNC_SHIFT                  (9U)
/*! INSYNC - Input Synchronization
 */
#define SCT_CONFIG_INSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
#define SCT_CONFIG_AUTOLIMIT_L_MASK              (0x20000U)
#define SCT_CONFIG_AUTOLIMIT_L_SHIFT             (17U)
/*! AUTOLIMIT_L - Auto Limit Lower
 *  0b0..Disable.
 *  0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
 */
#define SCT_CONFIG_AUTOLIMIT_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
#define SCT_CONFIG_AUTOLIMIT_H_MASK              (0x40000U)
#define SCT_CONFIG_AUTOLIMIT_H_SHIFT             (18U)
/*! AUTOLIMIT_H - Auto Limit Higher
 *  0b0..Disable.
 *  0b1..Enable. A match on match register 0 is the LIMIT condition. No need to define an associated event.
 */
#define SCT_CONFIG_AUTOLIMIT_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
/*! @} */

/*! @name CTRL - SCT Control */
/*! @{ */
#define SCT_CTRL_DOWN_L_MASK                     (0x1U)
#define SCT_CTRL_DOWN_L_SHIFT                    (0U)
/*! DOWN_L - Down Counter Low
 *  0b0..Up. The L or unified counter is counting up.
 *  0b1..Down. The L or unified counter is counting down.
 */
#define SCT_CTRL_DOWN_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
#define SCT_CTRL_STOP_L_MASK                     (0x2U)
#define SCT_CTRL_STOP_L_SHIFT                    (1U)
/*! STOP_L - Stop Counter Low
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_STOP_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
#define SCT_CTRL_HALT_L_MASK                     (0x4U)
#define SCT_CTRL_HALT_L_SHIFT                    (2U)
/*! HALT_L - Halt Counter Low
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_HALT_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
#define SCT_CTRL_CLRCTR_L_MASK                   (0x8U)
#define SCT_CTRL_CLRCTR_L_SHIFT                  (3U)
/*! CLRCTR_L - Clear Counter Low
 */
#define SCT_CTRL_CLRCTR_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
#define SCT_CTRL_BIDIR_L_MASK                    (0x10U)
#define SCT_CTRL_BIDIR_L_SHIFT                   (4U)
/*! BIDIR_L - Bidirectional Select Low
 *  0b0..Up. The counter counts up to a limit condition, then is cleared to zero.
 *  0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.
 */
#define SCT_CTRL_BIDIR_L(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
#define SCT_CTRL_PRE_L_MASK                      (0x1FE0U)
#define SCT_CTRL_PRE_L_SHIFT                     (5U)
/*! PRE_L - Prescaler for Low Counter
 */
#define SCT_CTRL_PRE_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
#define SCT_CTRL_DOWN_H_MASK                     (0x10000U)
#define SCT_CTRL_DOWN_H_SHIFT                    (16U)
/*! DOWN_H - Down Counter High
 *  0b0..Up. The H counter is counting up.
 *  0b1..Down. The H counter is counting down.
 */
#define SCT_CTRL_DOWN_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
#define SCT_CTRL_STOP_H_MASK                     (0x20000U)
#define SCT_CTRL_STOP_H_SHIFT                    (17U)
/*! STOP_H - Stop Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_STOP_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
#define SCT_CTRL_HALT_H_MASK                     (0x40000U)
#define SCT_CTRL_HALT_H_SHIFT                    (18U)
/*! HALT_H - Halt Counter High
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_CTRL_HALT_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
#define SCT_CTRL_CLRCTR_H_MASK                   (0x80000U)
#define SCT_CTRL_CLRCTR_H_SHIFT                  (19U)
/*! CLRCTR_H - Clear Counter High
 */
#define SCT_CTRL_CLRCTR_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
#define SCT_CTRL_BIDIR_H_MASK                    (0x100000U)
#define SCT_CTRL_BIDIR_H_SHIFT                   (20U)
/*! BIDIR_H - Bidirectional Select High
 *  0b0..Up. The H counter counts up to its limit condition, then is cleared to zero.
 *  0b1..Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0.
 */
#define SCT_CTRL_BIDIR_H(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
#define SCT_CTRL_PRE_H_MASK                      (0x1FE00000U)
#define SCT_CTRL_PRE_H_SHIFT                     (21U)
/*! PRE_H - Prescaler for High Counter
 */
#define SCT_CTRL_PRE_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
/*! @} */

/*! @name LIMIT - SCT Limit Event Select */
/*! @{ */
#define SCT_LIMIT_LIMMSK_L_MASK                  (0xFFFFU)
#define SCT_LIMIT_LIMMSK_L_SHIFT                 (0U)
/*! LIMMSK_L - Limit Event Counter Low
 */
#define SCT_LIMIT_LIMMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
#define SCT_LIMIT_LIMMSK_H_MASK                  (0xFFFF0000U)
#define SCT_LIMIT_LIMMSK_H_SHIFT                 (16U)
/*! LIMMSK_H - Limit Event Counter High
 */
#define SCT_LIMIT_LIMMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
/*! @} */

/*! @name HALT - Halt Event Select */
/*! @{ */
#define SCT_HALT_HALTMSK_L_MASK                  (0xFFFFU)
#define SCT_HALT_HALTMSK_L_SHIFT                 (0U)
/*! HALTMSK_L - Halt Event Low
 */
#define SCT_HALT_HALTMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
#define SCT_HALT_HALTMSK_H_MASK                  (0xFFFF0000U)
#define SCT_HALT_HALTMSK_H_SHIFT                 (16U)
/*! HALTMSK_H - Halt Event High
 */
#define SCT_HALT_HALTMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
/*! @} */

/*! @name STOP - Stop Event Select */
/*! @{ */
#define SCT_STOP_STOPMSK_L_MASK                  (0xFFFFU)
#define SCT_STOP_STOPMSK_L_SHIFT                 (0U)
/*! STOPMSK_L - Stop Event Low
 */
#define SCT_STOP_STOPMSK_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
#define SCT_STOP_STOPMSK_H_MASK                  (0xFFFF0000U)
#define SCT_STOP_STOPMSK_H_SHIFT                 (16U)
/*! STOPMSK_H - Stop Event High
 */
#define SCT_STOP_STOPMSK_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
/*! @} */

/*! @name START - Start Event Select */
/*! @{ */
#define SCT_START_STARTMSK_L_MASK                (0xFFFFU)
#define SCT_START_STARTMSK_L_SHIFT               (0U)
/*! STARTMSK_L - If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 =
 *    bit 1, etc.). The number of bits = number of events in this SCT.
 */
#define SCT_START_STARTMSK_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
#define SCT_START_STARTMSK_H_MASK                (0xFFFF0000U)
#define SCT_START_STARTMSK_H_SHIFT               (16U)
/*! STARTMSK_H - If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 =
 *    bit 17, etc.). The number of bits = number of events in this SCT.
 */
#define SCT_START_STARTMSK_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
/*! @} */

/*! @name COUNT - Counter */
/*! @{ */
#define SCT_COUNT_CTR_L_MASK                     (0xFFFFU)
#define SCT_COUNT_CTR_L_SHIFT                    (0U)
/*! CTR_L - Counter Low
 */
#define SCT_COUNT_CTR_L(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
#define SCT_COUNT_CTR_H_MASK                     (0xFFFF0000U)
#define SCT_COUNT_CTR_H_SHIFT                    (16U)
/*! CTR_H - Counter High
 */
#define SCT_COUNT_CTR_H(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
/*! @} */

/*! @name STATE - State */
/*! @{ */
#define SCT_STATE_STATE_L_MASK                   (0x1FU)
#define SCT_STATE_STATE_L_SHIFT                  (0U)
/*! STATE_L - State variable
 */
#define SCT_STATE_STATE_L(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
#define SCT_STATE_STATE_H_MASK                   (0x1F0000U)
#define SCT_STATE_STATE_H_SHIFT                  (16U)
/*! STATE_H - State variable
 */
#define SCT_STATE_STATE_H(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
/*! @} */

/*! @name INPUT - Input */
/*! @{ */
#define SCT_INPUT_AIN0_MASK                      (0x1U)
#define SCT_INPUT_AIN0_SHIFT                     (0U)
/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
#define SCT_INPUT_AIN1_MASK                      (0x2U)
#define SCT_INPUT_AIN1_SHIFT                     (1U)
/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
#define SCT_INPUT_AIN2_MASK                      (0x4U)
#define SCT_INPUT_AIN2_SHIFT                     (2U)
/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
#define SCT_INPUT_AIN3_MASK                      (0x8U)
#define SCT_INPUT_AIN3_SHIFT                     (3U)
/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
#define SCT_INPUT_AIN4_MASK                      (0x10U)
#define SCT_INPUT_AIN4_SHIFT                     (4U)
/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
#define SCT_INPUT_AIN5_MASK                      (0x20U)
#define SCT_INPUT_AIN5_SHIFT                     (5U)
/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
#define SCT_INPUT_AIN6_MASK                      (0x40U)
#define SCT_INPUT_AIN6_SHIFT                     (6U)
/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
#define SCT_INPUT_AIN7_MASK                      (0x80U)
#define SCT_INPUT_AIN7_SHIFT                     (7U)
/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
#define SCT_INPUT_AIN8_MASK                      (0x100U)
#define SCT_INPUT_AIN8_SHIFT                     (8U)
/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
#define SCT_INPUT_AIN9_MASK                      (0x200U)
#define SCT_INPUT_AIN9_SHIFT                     (9U)
/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
#define SCT_INPUT_AIN10_MASK                     (0x400U)
#define SCT_INPUT_AIN10_SHIFT                    (10U)
/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
#define SCT_INPUT_AIN11_MASK                     (0x800U)
#define SCT_INPUT_AIN11_SHIFT                    (11U)
/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
#define SCT_INPUT_AIN12_MASK                     (0x1000U)
#define SCT_INPUT_AIN12_SHIFT                    (12U)
/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
#define SCT_INPUT_AIN13_MASK                     (0x2000U)
#define SCT_INPUT_AIN13_SHIFT                    (13U)
/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
#define SCT_INPUT_AIN14_MASK                     (0x4000U)
#define SCT_INPUT_AIN14_SHIFT                    (14U)
/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
#define SCT_INPUT_AIN15_MASK                     (0x8000U)
#define SCT_INPUT_AIN15_SHIFT                    (15U)
/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge.
 */
#define SCT_INPUT_AIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
#define SCT_INPUT_SIN0_MASK                      (0x10000U)
#define SCT_INPUT_SIN0_SHIFT                     (16U)
/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN0(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
#define SCT_INPUT_SIN1_MASK                      (0x20000U)
#define SCT_INPUT_SIN1_SHIFT                     (17U)
/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN1(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
#define SCT_INPUT_SIN2_MASK                      (0x40000U)
#define SCT_INPUT_SIN2_SHIFT                     (18U)
/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN2(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
#define SCT_INPUT_SIN3_MASK                      (0x80000U)
#define SCT_INPUT_SIN3_SHIFT                     (19U)
/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN3(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
#define SCT_INPUT_SIN4_MASK                      (0x100000U)
#define SCT_INPUT_SIN4_SHIFT                     (20U)
/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN4(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
#define SCT_INPUT_SIN5_MASK                      (0x200000U)
#define SCT_INPUT_SIN5_SHIFT                     (21U)
/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN5(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
#define SCT_INPUT_SIN6_MASK                      (0x400000U)
#define SCT_INPUT_SIN6_SHIFT                     (22U)
/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN6(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
#define SCT_INPUT_SIN7_MASK                      (0x800000U)
#define SCT_INPUT_SIN7_SHIFT                     (23U)
/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN7(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
#define SCT_INPUT_SIN8_MASK                      (0x1000000U)
#define SCT_INPUT_SIN8_SHIFT                     (24U)
/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN8(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
#define SCT_INPUT_SIN9_MASK                      (0x2000000U)
#define SCT_INPUT_SIN9_SHIFT                     (25U)
/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN9(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
#define SCT_INPUT_SIN10_MASK                     (0x4000000U)
#define SCT_INPUT_SIN10_SHIFT                    (26U)
/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN10(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
#define SCT_INPUT_SIN11_MASK                     (0x8000000U)
#define SCT_INPUT_SIN11_SHIFT                    (27U)
/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN11(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
#define SCT_INPUT_SIN12_MASK                     (0x10000000U)
#define SCT_INPUT_SIN12_SHIFT                    (28U)
/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN12(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
#define SCT_INPUT_SIN13_MASK                     (0x20000000U)
#define SCT_INPUT_SIN13_SHIFT                    (29U)
/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN13(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
#define SCT_INPUT_SIN14_MASK                     (0x40000000U)
#define SCT_INPUT_SIN14_SHIFT                    (30U)
/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN14(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
#define SCT_INPUT_SIN15_MASK                     (0x80000000U)
#define SCT_INPUT_SIN15_SHIFT                    (31U)
/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC.
 */
#define SCT_INPUT_SIN15(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
/*! @} */

/*! @name REGMODE - Match/Capture Mode */
/*! @{ */
#define SCT_REGMODE_REGMOD_L_MASK                (0xFFFFU)
#define SCT_REGMODE_REGMOD_L_SHIFT               (0U)
/*! REGMOD_L
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
#define SCT_REGMODE_REGMOD_L0_MASK               (0x1U)
#define SCT_REGMODE_REGMOD_L0_SHIFT              (0U)
/*! REGMOD_L0 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L0_SHIFT)) & SCT_REGMODE_REGMOD_L0_MASK)
#define SCT_REGMODE_REGMOD_L1_MASK               (0x2U)
#define SCT_REGMODE_REGMOD_L1_SHIFT              (1U)
/*! REGMOD_L1 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L1_SHIFT)) & SCT_REGMODE_REGMOD_L1_MASK)
#define SCT_REGMODE_REGMOD_L2_MASK               (0x4U)
#define SCT_REGMODE_REGMOD_L2_SHIFT              (2U)
/*! REGMOD_L2 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L2_SHIFT)) & SCT_REGMODE_REGMOD_L2_MASK)
#define SCT_REGMODE_REGMOD_L3_MASK               (0x8U)
#define SCT_REGMODE_REGMOD_L3_SHIFT              (3U)
/*! REGMOD_L3 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L3_SHIFT)) & SCT_REGMODE_REGMOD_L3_MASK)
#define SCT_REGMODE_REGMOD_L4_MASK               (0x10U)
#define SCT_REGMODE_REGMOD_L4_SHIFT              (4U)
/*! REGMOD_L4 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L4_SHIFT)) & SCT_REGMODE_REGMOD_L4_MASK)
#define SCT_REGMODE_REGMOD_L5_MASK               (0x20U)
#define SCT_REGMODE_REGMOD_L5_SHIFT              (5U)
/*! REGMOD_L5 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L5_SHIFT)) & SCT_REGMODE_REGMOD_L5_MASK)
#define SCT_REGMODE_REGMOD_L6_MASK               (0x40U)
#define SCT_REGMODE_REGMOD_L6_SHIFT              (6U)
/*! REGMOD_L6 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L6_SHIFT)) & SCT_REGMODE_REGMOD_L6_MASK)
#define SCT_REGMODE_REGMOD_L7_MASK               (0x80U)
#define SCT_REGMODE_REGMOD_L7_SHIFT              (7U)
/*! REGMOD_L7 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L7_SHIFT)) & SCT_REGMODE_REGMOD_L7_MASK)
#define SCT_REGMODE_REGMOD_L8_MASK               (0x100U)
#define SCT_REGMODE_REGMOD_L8_SHIFT              (8U)
/*! REGMOD_L8 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L8_SHIFT)) & SCT_REGMODE_REGMOD_L8_MASK)
#define SCT_REGMODE_REGMOD_L9_MASK               (0x200U)
#define SCT_REGMODE_REGMOD_L9_SHIFT              (9U)
/*! REGMOD_L9 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L9_SHIFT)) & SCT_REGMODE_REGMOD_L9_MASK)
#define SCT_REGMODE_REGMOD_L10_MASK              (0x400U)
#define SCT_REGMODE_REGMOD_L10_SHIFT             (10U)
/*! REGMOD_L10 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L10_SHIFT)) & SCT_REGMODE_REGMOD_L10_MASK)
#define SCT_REGMODE_REGMOD_L11_MASK              (0x800U)
#define SCT_REGMODE_REGMOD_L11_SHIFT             (11U)
/*! REGMOD_L11 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L11_SHIFT)) & SCT_REGMODE_REGMOD_L11_MASK)
#define SCT_REGMODE_REGMOD_L12_MASK              (0x1000U)
#define SCT_REGMODE_REGMOD_L12_SHIFT             (12U)
/*! REGMOD_L12 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L12_SHIFT)) & SCT_REGMODE_REGMOD_L12_MASK)
#define SCT_REGMODE_REGMOD_L13_MASK              (0x2000U)
#define SCT_REGMODE_REGMOD_L13_SHIFT             (13U)
/*! REGMOD_L13 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L13_SHIFT)) & SCT_REGMODE_REGMOD_L13_MASK)
#define SCT_REGMODE_REGMOD_L14_MASK              (0x4000U)
#define SCT_REGMODE_REGMOD_L14_SHIFT             (14U)
/*! REGMOD_L14 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L14_SHIFT)) & SCT_REGMODE_REGMOD_L14_MASK)
#define SCT_REGMODE_REGMOD_L15_MASK              (0x8000U)
#define SCT_REGMODE_REGMOD_L15_SHIFT             (15U)
/*! REGMOD_L15 - Register Mode Low n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_L15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L15_SHIFT)) & SCT_REGMODE_REGMOD_L15_MASK)
#define SCT_REGMODE_REGMOD_H_MASK                (0xFFFF0000U)
#define SCT_REGMODE_REGMOD_H_SHIFT               (16U)
/*! REGMOD_H
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
#define SCT_REGMODE_REGMOD_H0_MASK               (0x10000U)
#define SCT_REGMODE_REGMOD_H0_SHIFT              (16U)
/*! REGMOD_H0 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H0(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H0_SHIFT)) & SCT_REGMODE_REGMOD_H0_MASK)
#define SCT_REGMODE_REGMOD_H1_MASK               (0x20000U)
#define SCT_REGMODE_REGMOD_H1_SHIFT              (17U)
/*! REGMOD_H1 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H1(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H1_SHIFT)) & SCT_REGMODE_REGMOD_H1_MASK)
#define SCT_REGMODE_REGMOD_H2_MASK               (0x40000U)
#define SCT_REGMODE_REGMOD_H2_SHIFT              (18U)
/*! REGMOD_H2 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H2(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H2_SHIFT)) & SCT_REGMODE_REGMOD_H2_MASK)
#define SCT_REGMODE_REGMOD_H3_MASK               (0x80000U)
#define SCT_REGMODE_REGMOD_H3_SHIFT              (19U)
/*! REGMOD_H3 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H3(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H3_SHIFT)) & SCT_REGMODE_REGMOD_H3_MASK)
#define SCT_REGMODE_REGMOD_H4_MASK               (0x100000U)
#define SCT_REGMODE_REGMOD_H4_SHIFT              (20U)
/*! REGMOD_H4 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H4(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H4_SHIFT)) & SCT_REGMODE_REGMOD_H4_MASK)
#define SCT_REGMODE_REGMOD_H5_MASK               (0x200000U)
#define SCT_REGMODE_REGMOD_H5_SHIFT              (21U)
/*! REGMOD_H5 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H5(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H5_SHIFT)) & SCT_REGMODE_REGMOD_H5_MASK)
#define SCT_REGMODE_REGMOD_H6_MASK               (0x400000U)
#define SCT_REGMODE_REGMOD_H6_SHIFT              (22U)
/*! REGMOD_H6 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H6(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H6_SHIFT)) & SCT_REGMODE_REGMOD_H6_MASK)
#define SCT_REGMODE_REGMOD_H7_MASK               (0x800000U)
#define SCT_REGMODE_REGMOD_H7_SHIFT              (23U)
/*! REGMOD_H7 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H7(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H7_SHIFT)) & SCT_REGMODE_REGMOD_H7_MASK)
#define SCT_REGMODE_REGMOD_H8_MASK               (0x1000000U)
#define SCT_REGMODE_REGMOD_H8_SHIFT              (24U)
/*! REGMOD_H8 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H8(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H8_SHIFT)) & SCT_REGMODE_REGMOD_H8_MASK)
#define SCT_REGMODE_REGMOD_H9_MASK               (0x2000000U)
#define SCT_REGMODE_REGMOD_H9_SHIFT              (25U)
/*! REGMOD_H9 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H9(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H9_SHIFT)) & SCT_REGMODE_REGMOD_H9_MASK)
#define SCT_REGMODE_REGMOD_H10_MASK              (0x4000000U)
#define SCT_REGMODE_REGMOD_H10_SHIFT             (26U)
/*! REGMOD_H10 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H10(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H10_SHIFT)) & SCT_REGMODE_REGMOD_H10_MASK)
#define SCT_REGMODE_REGMOD_H11_MASK              (0x8000000U)
#define SCT_REGMODE_REGMOD_H11_SHIFT             (27U)
/*! REGMOD_H11 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H11(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H11_SHIFT)) & SCT_REGMODE_REGMOD_H11_MASK)
#define SCT_REGMODE_REGMOD_H12_MASK              (0x10000000U)
#define SCT_REGMODE_REGMOD_H12_SHIFT             (28U)
/*! REGMOD_H12 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H12(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H12_SHIFT)) & SCT_REGMODE_REGMOD_H12_MASK)
#define SCT_REGMODE_REGMOD_H13_MASK              (0x20000000U)
#define SCT_REGMODE_REGMOD_H13_SHIFT             (29U)
/*! REGMOD_H13 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H13(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H13_SHIFT)) & SCT_REGMODE_REGMOD_H13_MASK)
#define SCT_REGMODE_REGMOD_H14_MASK              (0x40000000U)
#define SCT_REGMODE_REGMOD_H14_SHIFT             (30U)
/*! REGMOD_H14 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H14(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H14_SHIFT)) & SCT_REGMODE_REGMOD_H14_MASK)
#define SCT_REGMODE_REGMOD_H15_MASK              (0x80000000U)
#define SCT_REGMODE_REGMOD_H15_SHIFT             (31U)
/*! REGMOD_H15 - Register Mode High n
 *  0b0..Match. Register n operates as a match register
 *  0b1..Capture. Register n operates as a capture register
 */
#define SCT_REGMODE_REGMOD_H15(x)                (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H15_SHIFT)) & SCT_REGMODE_REGMOD_H15_MASK)
/*! @} */

/*! @name OUTPUT - Output */
/*! @{ */
#define SCT_OUTPUT_OUT0_MASK                     (0x1U)
#define SCT_OUTPUT_OUT0_SHIFT                    (0U)
/*! OUT0 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT0_SHIFT)) & SCT_OUTPUT_OUT0_MASK)
#define SCT_OUTPUT_OUT1_MASK                     (0x2U)
#define SCT_OUTPUT_OUT1_SHIFT                    (1U)
/*! OUT1 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT1_SHIFT)) & SCT_OUTPUT_OUT1_MASK)
#define SCT_OUTPUT_OUT2_MASK                     (0x4U)
#define SCT_OUTPUT_OUT2_SHIFT                    (2U)
/*! OUT2 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT2_SHIFT)) & SCT_OUTPUT_OUT2_MASK)
#define SCT_OUTPUT_OUT3_MASK                     (0x8U)
#define SCT_OUTPUT_OUT3_SHIFT                    (3U)
/*! OUT3 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT3_SHIFT)) & SCT_OUTPUT_OUT3_MASK)
#define SCT_OUTPUT_OUT4_MASK                     (0x10U)
#define SCT_OUTPUT_OUT4_SHIFT                    (4U)
/*! OUT4 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT4_SHIFT)) & SCT_OUTPUT_OUT4_MASK)
#define SCT_OUTPUT_OUT5_MASK                     (0x20U)
#define SCT_OUTPUT_OUT5_SHIFT                    (5U)
/*! OUT5 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT5_SHIFT)) & SCT_OUTPUT_OUT5_MASK)
#define SCT_OUTPUT_OUT6_MASK                     (0x40U)
#define SCT_OUTPUT_OUT6_SHIFT                    (6U)
/*! OUT6 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT6_SHIFT)) & SCT_OUTPUT_OUT6_MASK)
#define SCT_OUTPUT_OUT7_MASK                     (0x80U)
#define SCT_OUTPUT_OUT7_SHIFT                    (7U)
/*! OUT7 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT7_SHIFT)) & SCT_OUTPUT_OUT7_MASK)
#define SCT_OUTPUT_OUT8_MASK                     (0x100U)
#define SCT_OUTPUT_OUT8_SHIFT                    (8U)
/*! OUT8 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT8_SHIFT)) & SCT_OUTPUT_OUT8_MASK)
#define SCT_OUTPUT_OUT9_MASK                     (0x200U)
#define SCT_OUTPUT_OUT9_SHIFT                    (9U)
/*! OUT9 - Output n
 *  0b0..Writing a 0 forces the corresponding output low
 *  0b1..Writing a 1 forces the corresponding output high
 */
#define SCT_OUTPUT_OUT9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT9_SHIFT)) & SCT_OUTPUT_OUT9_MASK)
/*! @} */

/*! @name OUTPUTDIRCTRL - Output Counter Direction Control */
/*! @{ */
#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK           (0x3U)
#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT          (0U)
/*! SETCLR0 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR0(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK           (0xCU)
#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT          (2U)
/*! SETCLR1 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR1(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK           (0x30U)
#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT          (4U)
/*! SETCLR2 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR2(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK           (0xC0U)
#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT          (6U)
/*! SETCLR3 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR3(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK           (0x300U)
#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT          (8U)
/*! SETCLR4 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR4(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK           (0xC00U)
#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT          (10U)
/*! SETCLR5 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR5(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK           (0x3000U)
#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT          (12U)
/*! SETCLR6 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR6(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK           (0xC000U)
#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT          (14U)
/*! SETCLR7 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR7(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK           (0x30000U)
#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT          (16U)
/*! SETCLR8 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR8(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK           (0xC0000U)
#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT          (18U)
/*! SETCLR9 - Set/Clear Operation on Output n
 *  0b00..Set and clear do not depend on the direction of any counter.
 *  0b01..Set and clear are reversed when counter L or the unified counter is counting down.
 *  0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.
 *  0b11..Reserved. Do not program this value.
 */
#define SCT_OUTPUTDIRCTRL_SETCLR9(x)             (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
/*! @} */

/*! @name RES - Output Conflict Resolution */
/*! @{ */
#define SCT_RES_O0RES_MASK                       (0x3U)
#define SCT_RES_O0RES_SHIFT                      (0U)
/*! O0RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O0RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
#define SCT_RES_O1RES_MASK                       (0xCU)
#define SCT_RES_O1RES_SHIFT                      (2U)
/*! O1RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O1RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
#define SCT_RES_O2RES_MASK                       (0x30U)
#define SCT_RES_O2RES_SHIFT                      (4U)
/*! O2RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O2RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
#define SCT_RES_O3RES_MASK                       (0xC0U)
#define SCT_RES_O3RES_SHIFT                      (6U)
/*! O3RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O3RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
#define SCT_RES_O4RES_MASK                       (0x300U)
#define SCT_RES_O4RES_SHIFT                      (8U)
/*! O4RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O4RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
#define SCT_RES_O5RES_MASK                       (0xC00U)
#define SCT_RES_O5RES_SHIFT                      (10U)
/*! O5RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O5RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
#define SCT_RES_O6RES_MASK                       (0x3000U)
#define SCT_RES_O6RES_SHIFT                      (12U)
/*! O6RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O6RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
#define SCT_RES_O7RES_MASK                       (0xC000U)
#define SCT_RES_O7RES_SHIFT                      (14U)
/*! O7RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O7RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
#define SCT_RES_O8RES_MASK                       (0x30000U)
#define SCT_RES_O8RES_SHIFT                      (16U)
/*! O8RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O8RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
#define SCT_RES_O9RES_MASK                       (0xC0000U)
#define SCT_RES_O9RES_SHIFT                      (18U)
/*! O9RES - Effect of simultaneous set and clear on output n
 *  0b00..No change
 *  0b01..Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b10..Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)
 *  0b11..Toggle output
 */
#define SCT_RES_O9RES(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
/*! @} */

/*! @name DMAREQ0 - DMA Request 0 */
/*! @{ */
#define SCT_DMAREQ0_DEV_0_MASK                   (0x1U)
#define SCT_DMAREQ0_DEV_0_SHIFT                  (0U)
/*! DEV_0 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK)
#define SCT_DMAREQ0_DEV_1_MASK                   (0x2U)
#define SCT_DMAREQ0_DEV_1_SHIFT                  (1U)
/*! DEV_1 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_1_SHIFT)) & SCT_DMAREQ0_DEV_1_MASK)
#define SCT_DMAREQ0_DEV_2_MASK                   (0x4U)
#define SCT_DMAREQ0_DEV_2_SHIFT                  (2U)
/*! DEV_2 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_2_SHIFT)) & SCT_DMAREQ0_DEV_2_MASK)
#define SCT_DMAREQ0_DEV_3_MASK                   (0x8U)
#define SCT_DMAREQ0_DEV_3_SHIFT                  (3U)
/*! DEV_3 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_3_SHIFT)) & SCT_DMAREQ0_DEV_3_MASK)
#define SCT_DMAREQ0_DEV_4_MASK                   (0x10U)
#define SCT_DMAREQ0_DEV_4_SHIFT                  (4U)
/*! DEV_4 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_4_SHIFT)) & SCT_DMAREQ0_DEV_4_MASK)
#define SCT_DMAREQ0_DEV_5_MASK                   (0x20U)
#define SCT_DMAREQ0_DEV_5_SHIFT                  (5U)
/*! DEV_5 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_5_SHIFT)) & SCT_DMAREQ0_DEV_5_MASK)
#define SCT_DMAREQ0_DEV_6_MASK                   (0x40U)
#define SCT_DMAREQ0_DEV_6_SHIFT                  (6U)
/*! DEV_6 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_6_SHIFT)) & SCT_DMAREQ0_DEV_6_MASK)
#define SCT_DMAREQ0_DEV_7_MASK                   (0x80U)
#define SCT_DMAREQ0_DEV_7_SHIFT                  (7U)
/*! DEV_7 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_7_SHIFT)) & SCT_DMAREQ0_DEV_7_MASK)
#define SCT_DMAREQ0_DEV_8_MASK                   (0x100U)
#define SCT_DMAREQ0_DEV_8_SHIFT                  (8U)
/*! DEV_8 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_8_SHIFT)) & SCT_DMAREQ0_DEV_8_MASK)
#define SCT_DMAREQ0_DEV_9_MASK                   (0x200U)
#define SCT_DMAREQ0_DEV_9_SHIFT                  (9U)
/*! DEV_9 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_9_SHIFT)) & SCT_DMAREQ0_DEV_9_MASK)
#define SCT_DMAREQ0_DEV_10_MASK                  (0x400U)
#define SCT_DMAREQ0_DEV_10_SHIFT                 (10U)
/*! DEV_10 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_10_SHIFT)) & SCT_DMAREQ0_DEV_10_MASK)
#define SCT_DMAREQ0_DEV_11_MASK                  (0x800U)
#define SCT_DMAREQ0_DEV_11_SHIFT                 (11U)
/*! DEV_11 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_11_SHIFT)) & SCT_DMAREQ0_DEV_11_MASK)
#define SCT_DMAREQ0_DEV_12_MASK                  (0x1000U)
#define SCT_DMAREQ0_DEV_12_SHIFT                 (12U)
/*! DEV_12 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_12_SHIFT)) & SCT_DMAREQ0_DEV_12_MASK)
#define SCT_DMAREQ0_DEV_13_MASK                  (0x2000U)
#define SCT_DMAREQ0_DEV_13_SHIFT                 (13U)
/*! DEV_13 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_13_SHIFT)) & SCT_DMAREQ0_DEV_13_MASK)
#define SCT_DMAREQ0_DEV_14_MASK                  (0x4000U)
#define SCT_DMAREQ0_DEV_14_SHIFT                 (14U)
/*! DEV_14 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_14_SHIFT)) & SCT_DMAREQ0_DEV_14_MASK)
#define SCT_DMAREQ0_DEV_15_MASK                  (0x8000U)
#define SCT_DMAREQ0_DEV_15_SHIFT                 (15U)
/*! DEV_15 - DMA Request Event n
 */
#define SCT_DMAREQ0_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_15_SHIFT)) & SCT_DMAREQ0_DEV_15_MASK)
#define SCT_DMAREQ0_DRL0_MASK                    (0x40000000U)
#define SCT_DMAREQ0_DRL0_SHIFT                   (30U)
/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.
 */
#define SCT_DMAREQ0_DRL0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK)
#define SCT_DMAREQ0_DRQ0_MASK                    (0x80000000U)
#define SCT_DMAREQ0_DRQ0_SHIFT                   (31U)
/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA
 *    channel is enabled and properly set up, it is unlikely that software will see this flag. DRQ0
 *    will be cleared rapidly by the DMA service. If the flag remains set there could be an issue with
 *    DMA setup.
 */
#define SCT_DMAREQ0_DRQ0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK)
/*! @} */

/*! @name DMAREQ1 - DMA Request 1 */
/*! @{ */
#define SCT_DMAREQ1_DEV_0_MASK                   (0x1U)
#define SCT_DMAREQ1_DEV_0_SHIFT                  (0U)
/*! DEV_0 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_0(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_0_SHIFT)) & SCT_DMAREQ1_DEV_0_MASK)
#define SCT_DMAREQ1_DEV_1_MASK                   (0x2U)
#define SCT_DMAREQ1_DEV_1_SHIFT                  (1U)
/*! DEV_1 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_1(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK)
#define SCT_DMAREQ1_DEV_2_MASK                   (0x4U)
#define SCT_DMAREQ1_DEV_2_SHIFT                  (2U)
/*! DEV_2 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_2(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_2_SHIFT)) & SCT_DMAREQ1_DEV_2_MASK)
#define SCT_DMAREQ1_DEV_3_MASK                   (0x8U)
#define SCT_DMAREQ1_DEV_3_SHIFT                  (3U)
/*! DEV_3 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_3(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_3_SHIFT)) & SCT_DMAREQ1_DEV_3_MASK)
#define SCT_DMAREQ1_DEV_4_MASK                   (0x10U)
#define SCT_DMAREQ1_DEV_4_SHIFT                  (4U)
/*! DEV_4 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_4(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_4_SHIFT)) & SCT_DMAREQ1_DEV_4_MASK)
#define SCT_DMAREQ1_DEV_5_MASK                   (0x20U)
#define SCT_DMAREQ1_DEV_5_SHIFT                  (5U)
/*! DEV_5 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_5(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_5_SHIFT)) & SCT_DMAREQ1_DEV_5_MASK)
#define SCT_DMAREQ1_DEV_6_MASK                   (0x40U)
#define SCT_DMAREQ1_DEV_6_SHIFT                  (6U)
/*! DEV_6 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_6(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_6_SHIFT)) & SCT_DMAREQ1_DEV_6_MASK)
#define SCT_DMAREQ1_DEV_7_MASK                   (0x80U)
#define SCT_DMAREQ1_DEV_7_SHIFT                  (7U)
/*! DEV_7 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_7(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_7_SHIFT)) & SCT_DMAREQ1_DEV_7_MASK)
#define SCT_DMAREQ1_DEV_8_MASK                   (0x100U)
#define SCT_DMAREQ1_DEV_8_SHIFT                  (8U)
/*! DEV_8 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_8(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_8_SHIFT)) & SCT_DMAREQ1_DEV_8_MASK)
#define SCT_DMAREQ1_DEV_9_MASK                   (0x200U)
#define SCT_DMAREQ1_DEV_9_SHIFT                  (9U)
/*! DEV_9 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_9(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_9_SHIFT)) & SCT_DMAREQ1_DEV_9_MASK)
#define SCT_DMAREQ1_DEV_10_MASK                  (0x400U)
#define SCT_DMAREQ1_DEV_10_SHIFT                 (10U)
/*! DEV_10 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_10(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_10_SHIFT)) & SCT_DMAREQ1_DEV_10_MASK)
#define SCT_DMAREQ1_DEV_11_MASK                  (0x800U)
#define SCT_DMAREQ1_DEV_11_SHIFT                 (11U)
/*! DEV_11 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_11(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_11_SHIFT)) & SCT_DMAREQ1_DEV_11_MASK)
#define SCT_DMAREQ1_DEV_12_MASK                  (0x1000U)
#define SCT_DMAREQ1_DEV_12_SHIFT                 (12U)
/*! DEV_12 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_12(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_12_SHIFT)) & SCT_DMAREQ1_DEV_12_MASK)
#define SCT_DMAREQ1_DEV_13_MASK                  (0x2000U)
#define SCT_DMAREQ1_DEV_13_SHIFT                 (13U)
/*! DEV_13 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_13(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_13_SHIFT)) & SCT_DMAREQ1_DEV_13_MASK)
#define SCT_DMAREQ1_DEV_14_MASK                  (0x4000U)
#define SCT_DMAREQ1_DEV_14_SHIFT                 (14U)
/*! DEV_14 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_14(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_14_SHIFT)) & SCT_DMAREQ1_DEV_14_MASK)
#define SCT_DMAREQ1_DEV_15_MASK                  (0x8000U)
#define SCT_DMAREQ1_DEV_15_SHIFT                 (15U)
/*! DEV_15 - DMA Request Event n
 */
#define SCT_DMAREQ1_DEV_15(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_15_SHIFT)) & SCT_DMAREQ1_DEV_15_MASK)
#define SCT_DMAREQ1_DRL1_MASK                    (0x40000000U)
#define SCT_DMAREQ1_DRL1_SHIFT                   (30U)
/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
 */
#define SCT_DMAREQ1_DRL1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK)
#define SCT_DMAREQ1_DRQ1_MASK                    (0x80000000U)
#define SCT_DMAREQ1_DRQ1_SHIFT                   (31U)
/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA
 *    channel is enabled and properly set up, it is unlikely that software will see this flag. DRQ1
 *    will be cleared rapidly by the DMA service. If the flag remains set there could be an issue with
 *    DMA setup.
 */
#define SCT_DMAREQ1_DRQ1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK)
/*! @} */

/*! @name EVEN - Event Interrupt Enable */
/*! @{ */
#define SCT_EVEN_IEN0_MASK                       (0x1U)
#define SCT_EVEN_IEN0_SHIFT                      (0U)
/*! IEN0 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN0(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN0_SHIFT)) & SCT_EVEN_IEN0_MASK)
#define SCT_EVEN_IEN1_MASK                       (0x2U)
#define SCT_EVEN_IEN1_SHIFT                      (1U)
/*! IEN1 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN1(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN1_SHIFT)) & SCT_EVEN_IEN1_MASK)
#define SCT_EVEN_IEN2_MASK                       (0x4U)
#define SCT_EVEN_IEN2_SHIFT                      (2U)
/*! IEN2 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN2(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN2_SHIFT)) & SCT_EVEN_IEN2_MASK)
#define SCT_EVEN_IEN3_MASK                       (0x8U)
#define SCT_EVEN_IEN3_SHIFT                      (3U)
/*! IEN3 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN3(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN3_SHIFT)) & SCT_EVEN_IEN3_MASK)
#define SCT_EVEN_IEN4_MASK                       (0x10U)
#define SCT_EVEN_IEN4_SHIFT                      (4U)
/*! IEN4 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN4(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN4_SHIFT)) & SCT_EVEN_IEN4_MASK)
#define SCT_EVEN_IEN5_MASK                       (0x20U)
#define SCT_EVEN_IEN5_SHIFT                      (5U)
/*! IEN5 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN5(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN5_SHIFT)) & SCT_EVEN_IEN5_MASK)
#define SCT_EVEN_IEN6_MASK                       (0x40U)
#define SCT_EVEN_IEN6_SHIFT                      (6U)
/*! IEN6 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN6(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN6_SHIFT)) & SCT_EVEN_IEN6_MASK)
#define SCT_EVEN_IEN7_MASK                       (0x80U)
#define SCT_EVEN_IEN7_SHIFT                      (7U)
/*! IEN7 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN7(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN7_SHIFT)) & SCT_EVEN_IEN7_MASK)
#define SCT_EVEN_IEN8_MASK                       (0x100U)
#define SCT_EVEN_IEN8_SHIFT                      (8U)
/*! IEN8 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN8(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN8_SHIFT)) & SCT_EVEN_IEN8_MASK)
#define SCT_EVEN_IEN9_MASK                       (0x200U)
#define SCT_EVEN_IEN9_SHIFT                      (9U)
/*! IEN9 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN9(x)                         (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN9_SHIFT)) & SCT_EVEN_IEN9_MASK)
#define SCT_EVEN_IEN10_MASK                      (0x400U)
#define SCT_EVEN_IEN10_SHIFT                     (10U)
/*! IEN10 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN10(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN10_SHIFT)) & SCT_EVEN_IEN10_MASK)
#define SCT_EVEN_IEN11_MASK                      (0x800U)
#define SCT_EVEN_IEN11_SHIFT                     (11U)
/*! IEN11 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN11(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN11_SHIFT)) & SCT_EVEN_IEN11_MASK)
#define SCT_EVEN_IEN12_MASK                      (0x1000U)
#define SCT_EVEN_IEN12_SHIFT                     (12U)
/*! IEN12 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN12(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN12_SHIFT)) & SCT_EVEN_IEN12_MASK)
#define SCT_EVEN_IEN13_MASK                      (0x2000U)
#define SCT_EVEN_IEN13_SHIFT                     (13U)
/*! IEN13 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN13(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN13_SHIFT)) & SCT_EVEN_IEN13_MASK)
#define SCT_EVEN_IEN14_MASK                      (0x4000U)
#define SCT_EVEN_IEN14_SHIFT                     (14U)
/*! IEN14 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN14(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN14_SHIFT)) & SCT_EVEN_IEN14_MASK)
#define SCT_EVEN_IEN15_MASK                      (0x8000U)
#define SCT_EVEN_IEN15_SHIFT                     (15U)
/*! IEN15 - Event Interrupt Enable n
 *  0b0..Disable
 *  0b1..Enable
 */
#define SCT_EVEN_IEN15(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN15_SHIFT)) & SCT_EVEN_IEN15_MASK)
/*! @} */

/*! @name EVFLAG - Event Flag */
/*! @{ */
#define SCT_EVFLAG_FLAG0_MASK                    (0x1U)
#define SCT_EVFLAG_FLAG0_SHIFT                   (0U)
/*! FLAG0 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG0(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG0_SHIFT)) & SCT_EVFLAG_FLAG0_MASK)
#define SCT_EVFLAG_FLAG1_MASK                    (0x2U)
#define SCT_EVFLAG_FLAG1_SHIFT                   (1U)
/*! FLAG1 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG1(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG1_SHIFT)) & SCT_EVFLAG_FLAG1_MASK)
#define SCT_EVFLAG_FLAG2_MASK                    (0x4U)
#define SCT_EVFLAG_FLAG2_SHIFT                   (2U)
/*! FLAG2 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG2(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG2_SHIFT)) & SCT_EVFLAG_FLAG2_MASK)
#define SCT_EVFLAG_FLAG3_MASK                    (0x8U)
#define SCT_EVFLAG_FLAG3_SHIFT                   (3U)
/*! FLAG3 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG3(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG3_SHIFT)) & SCT_EVFLAG_FLAG3_MASK)
#define SCT_EVFLAG_FLAG4_MASK                    (0x10U)
#define SCT_EVFLAG_FLAG4_SHIFT                   (4U)
/*! FLAG4 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG4(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG4_SHIFT)) & SCT_EVFLAG_FLAG4_MASK)
#define SCT_EVFLAG_FLAG5_MASK                    (0x20U)
#define SCT_EVFLAG_FLAG5_SHIFT                   (5U)
/*! FLAG5 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG5(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG5_SHIFT)) & SCT_EVFLAG_FLAG5_MASK)
#define SCT_EVFLAG_FLAG6_MASK                    (0x40U)
#define SCT_EVFLAG_FLAG6_SHIFT                   (6U)
/*! FLAG6 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG6(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG6_SHIFT)) & SCT_EVFLAG_FLAG6_MASK)
#define SCT_EVFLAG_FLAG7_MASK                    (0x80U)
#define SCT_EVFLAG_FLAG7_SHIFT                   (7U)
/*! FLAG7 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG7(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG7_SHIFT)) & SCT_EVFLAG_FLAG7_MASK)
#define SCT_EVFLAG_FLAG8_MASK                    (0x100U)
#define SCT_EVFLAG_FLAG8_SHIFT                   (8U)
/*! FLAG8 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG8(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG8_SHIFT)) & SCT_EVFLAG_FLAG8_MASK)
#define SCT_EVFLAG_FLAG9_MASK                    (0x200U)
#define SCT_EVFLAG_FLAG9_SHIFT                   (9U)
/*! FLAG9 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG9(x)                      (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG9_SHIFT)) & SCT_EVFLAG_FLAG9_MASK)
#define SCT_EVFLAG_FLAG10_MASK                   (0x400U)
#define SCT_EVFLAG_FLAG10_SHIFT                  (10U)
/*! FLAG10 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG10(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG10_SHIFT)) & SCT_EVFLAG_FLAG10_MASK)
#define SCT_EVFLAG_FLAG11_MASK                   (0x800U)
#define SCT_EVFLAG_FLAG11_SHIFT                  (11U)
/*! FLAG11 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG11(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG11_SHIFT)) & SCT_EVFLAG_FLAG11_MASK)
#define SCT_EVFLAG_FLAG12_MASK                   (0x1000U)
#define SCT_EVFLAG_FLAG12_SHIFT                  (12U)
/*! FLAG12 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG12(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG12_SHIFT)) & SCT_EVFLAG_FLAG12_MASK)
#define SCT_EVFLAG_FLAG13_MASK                   (0x2000U)
#define SCT_EVFLAG_FLAG13_SHIFT                  (13U)
/*! FLAG13 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG13(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG13_SHIFT)) & SCT_EVFLAG_FLAG13_MASK)
#define SCT_EVFLAG_FLAG14_MASK                   (0x4000U)
#define SCT_EVFLAG_FLAG14_SHIFT                  (14U)
/*! FLAG14 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG14(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG14_SHIFT)) & SCT_EVFLAG_FLAG14_MASK)
#define SCT_EVFLAG_FLAG15_MASK                   (0x8000U)
#define SCT_EVFLAG_FLAG15_SHIFT                  (15U)
/*! FLAG15 - Event Flag n
 *  0b0..No Flag
 *  0b1..Event n Flag
 */
#define SCT_EVFLAG_FLAG15(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG15_SHIFT)) & SCT_EVFLAG_FLAG15_MASK)
/*! @} */

/*! @name CONEN - Conflict Interrupt Enable */
/*! @{ */
#define SCT_CONEN_NCEN0_MASK                     (0x1U)
#define SCT_CONEN_NCEN0_SHIFT                    (0U)
/*! NCEN0 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN0(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN0_SHIFT)) & SCT_CONEN_NCEN0_MASK)
#define SCT_CONEN_NCEN1_MASK                     (0x2U)
#define SCT_CONEN_NCEN1_SHIFT                    (1U)
/*! NCEN1 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN1(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN1_SHIFT)) & SCT_CONEN_NCEN1_MASK)
#define SCT_CONEN_NCEN2_MASK                     (0x4U)
#define SCT_CONEN_NCEN2_SHIFT                    (2U)
/*! NCEN2 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN2(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN2_SHIFT)) & SCT_CONEN_NCEN2_MASK)
#define SCT_CONEN_NCEN3_MASK                     (0x8U)
#define SCT_CONEN_NCEN3_SHIFT                    (3U)
/*! NCEN3 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN3(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN3_SHIFT)) & SCT_CONEN_NCEN3_MASK)
#define SCT_CONEN_NCEN4_MASK                     (0x10U)
#define SCT_CONEN_NCEN4_SHIFT                    (4U)
/*! NCEN4 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN4(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN4_SHIFT)) & SCT_CONEN_NCEN4_MASK)
#define SCT_CONEN_NCEN5_MASK                     (0x20U)
#define SCT_CONEN_NCEN5_SHIFT                    (5U)
/*! NCEN5 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN5(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN5_SHIFT)) & SCT_CONEN_NCEN5_MASK)
#define SCT_CONEN_NCEN6_MASK                     (0x40U)
#define SCT_CONEN_NCEN6_SHIFT                    (6U)
/*! NCEN6 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN6(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN6_SHIFT)) & SCT_CONEN_NCEN6_MASK)
#define SCT_CONEN_NCEN7_MASK                     (0x80U)
#define SCT_CONEN_NCEN7_SHIFT                    (7U)
/*! NCEN7 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN7(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN7_SHIFT)) & SCT_CONEN_NCEN7_MASK)
#define SCT_CONEN_NCEN8_MASK                     (0x100U)
#define SCT_CONEN_NCEN8_SHIFT                    (8U)
/*! NCEN8 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN8(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN8_SHIFT)) & SCT_CONEN_NCEN8_MASK)
#define SCT_CONEN_NCEN9_MASK                     (0x200U)
#define SCT_CONEN_NCEN9_SHIFT                    (9U)
/*! NCEN9 - No Change Conflict Event/Interrupt Enable
 *  0b0..No interrupt
 *  0b1..Interrupt
 */
#define SCT_CONEN_NCEN9(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN9_SHIFT)) & SCT_CONEN_NCEN9_MASK)
/*! @} */

/*! @name CONFLAG - Conflict Flag */
/*! @{ */
#define SCT_CONFLAG_NCFLAG0_MASK                 (0x1U)
#define SCT_CONFLAG_NCFLAG0_SHIFT                (0U)
/*! NCFLAG0 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG0(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG0_SHIFT)) & SCT_CONFLAG_NCFLAG0_MASK)
#define SCT_CONFLAG_NCFLAG1_MASK                 (0x2U)
#define SCT_CONFLAG_NCFLAG1_SHIFT                (1U)
/*! NCFLAG1 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG1(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG1_SHIFT)) & SCT_CONFLAG_NCFLAG1_MASK)
#define SCT_CONFLAG_NCFLAG2_MASK                 (0x4U)
#define SCT_CONFLAG_NCFLAG2_SHIFT                (2U)
/*! NCFLAG2 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG2(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG2_SHIFT)) & SCT_CONFLAG_NCFLAG2_MASK)
#define SCT_CONFLAG_NCFLAG3_MASK                 (0x8U)
#define SCT_CONFLAG_NCFLAG3_SHIFT                (3U)
/*! NCFLAG3 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG3(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG3_SHIFT)) & SCT_CONFLAG_NCFLAG3_MASK)
#define SCT_CONFLAG_NCFLAG4_MASK                 (0x10U)
#define SCT_CONFLAG_NCFLAG4_SHIFT                (4U)
/*! NCFLAG4 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG4(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG4_SHIFT)) & SCT_CONFLAG_NCFLAG4_MASK)
#define SCT_CONFLAG_NCFLAG5_MASK                 (0x20U)
#define SCT_CONFLAG_NCFLAG5_SHIFT                (5U)
/*! NCFLAG5 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG5(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG5_SHIFT)) & SCT_CONFLAG_NCFLAG5_MASK)
#define SCT_CONFLAG_NCFLAG6_MASK                 (0x40U)
#define SCT_CONFLAG_NCFLAG6_SHIFT                (6U)
/*! NCFLAG6 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG6(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG6_SHIFT)) & SCT_CONFLAG_NCFLAG6_MASK)
#define SCT_CONFLAG_NCFLAG7_MASK                 (0x80U)
#define SCT_CONFLAG_NCFLAG7_SHIFT                (7U)
/*! NCFLAG7 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG7(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG7_SHIFT)) & SCT_CONFLAG_NCFLAG7_MASK)
#define SCT_CONFLAG_NCFLAG8_MASK                 (0x100U)
#define SCT_CONFLAG_NCFLAG8_SHIFT                (8U)
/*! NCFLAG8 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG8(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG8_SHIFT)) & SCT_CONFLAG_NCFLAG8_MASK)
#define SCT_CONFLAG_NCFLAG9_MASK                 (0x200U)
#define SCT_CONFLAG_NCFLAG9_SHIFT                (9U)
/*! NCFLAG9 - No Change Conflict Event Flag
 *  0b0..No Conflict Event
 *  0b1..A No Change Conflict Event occured
 */
#define SCT_CONFLAG_NCFLAG9(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG9_SHIFT)) & SCT_CONFLAG_NCFLAG9_MASK)
#define SCT_CONFLAG_BUSERRL_MASK                 (0x40000000U)
#define SCT_CONFLAG_BUSERRL_SHIFT                (30U)
/*! BUSERRL - Bus Error Low/Unified
 */
#define SCT_CONFLAG_BUSERRL(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
#define SCT_CONFLAG_BUSERRH_MASK                 (0x80000000U)
#define SCT_CONFLAG_BUSERRH_SHIFT                (31U)
/*! BUSERRH - Bus Error High
 */
#define SCT_CONFLAG_BUSERRH(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
/*! @} */

/*! @name CAP - Capture Value */
/*! @{ */
#define SCT_CAP_CAPn_L_MASK                      (0xFFFFU)
#define SCT_CAP_CAPn_L_SHIFT                     (0U)
/*! CAPn_L - Capture n Low
 */
#define SCT_CAP_CAPn_L(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK)
#define SCT_CAP_CAPn_H_MASK                      (0xFFFF0000U)
#define SCT_CAP_CAPn_H_SHIFT                     (16U)
/*! CAPn_H - Capture n High
 */
#define SCT_CAP_CAPn_H(x)                        (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK)
/*! @} */

/* The count of SCT_CAP */
#define SCT_CAP_COUNT                            (16U)

/*! @name MATCH - Match Value */
/*! @{ */
#define SCT_MATCH_MATCHn_L_MASK                  (0xFFFFU)
#define SCT_MATCH_MATCHn_L_SHIFT                 (0U)
/*! MATCHn_L - Match n Low
 */
#define SCT_MATCH_MATCHn_L(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK)
#define SCT_MATCH_MATCHn_H_MASK                  (0xFFFF0000U)
#define SCT_MATCH_MATCHn_H_SHIFT                 (16U)
/*! MATCHn_H - Match n High
 */
#define SCT_MATCH_MATCHn_H(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK)
/*! @} */

/* The count of SCT_MATCH */
#define SCT_MATCH_COUNT                          (16U)

/*! @name CAPCTRL - Capture Control */
/*! @{ */
#define SCT_CAPCTRL_CAPCONn_L_MASK               (0xFFFFU)
#define SCT_CAPCTRL_CAPCONn_L_SHIFT              (0U)
/*! CAPCONn_L - Capture Control n Low
 */
#define SCT_CAPCTRL_CAPCONn_L(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK)
#define SCT_CAPCTRL_CAPCONn_H_MASK               (0xFFFF0000U)
#define SCT_CAPCTRL_CAPCONn_H_SHIFT              (16U)
/*! CAPCONn_H - Capture Control n High
 */
#define SCT_CAPCTRL_CAPCONn_H(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK)
/*! @} */

/* The count of SCT_CAPCTRL */
#define SCT_CAPCTRL_COUNT                        (16U)

/*! @name MATCHREL - Match Reload Value */
/*! @{ */
#define SCT_MATCHREL_RELOADn_L_MASK              (0xFFFFU)
#define SCT_MATCHREL_RELOADn_L_SHIFT             (0U)
/*! RELOADn_L - Reload n Low
 */
#define SCT_MATCHREL_RELOADn_L(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK)
#define SCT_MATCHREL_RELOADn_H_MASK              (0xFFFF0000U)
#define SCT_MATCHREL_RELOADn_H_SHIFT             (16U)
/*! RELOADn_H - Reload n High
 */
#define SCT_MATCHREL_RELOADn_H(x)                (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK)
/*! @} */

/* The count of SCT_MATCHREL */
#define SCT_MATCHREL_COUNT                       (16U)

/*! @name EV_STATE - Event n State */
/*! @{ */
#define SCT_EV_STATE_STATEMSKn_MASK              (0xFFFFFFFFU)
#define SCT_EV_STATE_STATEMSKn_SHIFT             (0U)
/*! STATEMSKn - Event State Mask n
 */
#define SCT_EV_STATE_STATEMSKn(x)                (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK)
/*! @} */

/* The count of SCT_EV_STATE */
#define SCT_EV_STATE_COUNT                       (16U)

/*! @name EV_CTRL - Event n Control */
/*! @{ */
#define SCT_EV_CTRL_MATCHSEL_MASK                (0xFU)
#define SCT_EV_CTRL_MATCHSEL_SHIFT               (0U)
/*! MATCHSEL - Match Select
 */
#define SCT_EV_CTRL_MATCHSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK)
#define SCT_EV_CTRL_HEVENT_MASK                  (0x10U)
#define SCT_EV_CTRL_HEVENT_SHIFT                 (4U)
/*! HEVENT - High Event
 *  0b0..Low Counter
 *  0b1..High Counter
 */
#define SCT_EV_CTRL_HEVENT(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK)
#define SCT_EV_CTRL_OUTSEL_MASK                  (0x20U)
#define SCT_EV_CTRL_OUTSEL_SHIFT                 (5U)
/*! OUTSEL - Input/Output Select
 *  0b0..Selects the inputs selected by IOSEL.
 *  0b1..Selects the outputs selected by IOSEL.
 */
#define SCT_EV_CTRL_OUTSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK)
#define SCT_EV_CTRL_IOSEL_MASK                   (0x3C0U)
#define SCT_EV_CTRL_IOSEL_SHIFT                  (6U)
/*! IOSEL - Input/Output Signal Select
 */
#define SCT_EV_CTRL_IOSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK)
#define SCT_EV_CTRL_IOCOND_MASK                  (0xC00U)
#define SCT_EV_CTRL_IOCOND_SHIFT                 (10U)
/*! IOCOND - Input/Output Condition
 *  0b00..Low
 *  0b01..Rise
 *  0b10..Fall
 *  0b11..High
 */
#define SCT_EV_CTRL_IOCOND(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK)
#define SCT_EV_CTRL_COMBMODE_MASK                (0x3000U)
#define SCT_EV_CTRL_COMBMODE_SHIFT               (12U)
/*! COMBMODE - Combination Mode
 *  0b00..OR. The event occurs when either the specified match or I/O condition occurs.
 *  0b01..MATCH. Uses the specified match only.
 *  0b10..IO. Uses the specified I/O condition only.
 *  0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.
 */
#define SCT_EV_CTRL_COMBMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK)
#define SCT_EV_CTRL_STATELD_MASK                 (0x4000U)
#define SCT_EV_CTRL_STATELD_SHIFT                (14U)
/*! STATELD - State Load
 *  0b0..Add. STATEV value is added into STATE (the carry-out is ignored).
 *  0b1..Load. STATEV value is loaded into STATE.
 */
#define SCT_EV_CTRL_STATELD(x)                   (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK)
#define SCT_EV_CTRL_STATEV_MASK                  (0xF8000U)
#define SCT_EV_CTRL_STATEV_SHIFT                 (15U)
/*! STATEV - State Value
 */
#define SCT_EV_CTRL_STATEV(x)                    (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK)
#define SCT_EV_CTRL_MATCHMEM_MASK                (0x100000U)
#define SCT_EV_CTRL_MATCHMEM_SHIFT               (20U)
/*! MATCHMEM - Match Mem
 */
#define SCT_EV_CTRL_MATCHMEM(x)                  (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK)
#define SCT_EV_CTRL_DIRECTION_MASK               (0x600000U)
#define SCT_EV_CTRL_DIRECTION_SHIFT              (21U)
/*! DIRECTION - Direction
 *  0b00..Direction independent. This event is triggered regardless of the count direction.
 *  0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.
 *  0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.
 *  0b11..Reserved
 */
#define SCT_EV_CTRL_DIRECTION(x)                 (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK)
/*! @} */

/* The count of SCT_EV_CTRL */
#define SCT_EV_CTRL_COUNT                        (16U)

/*! @name OUT_SET - Output n Set */
/*! @{ */
#define SCT_OUT_SET_SET_MASK                     (0xFFFFU)
#define SCT_OUT_SET_SET_SHIFT                    (0U)
/*! SET - Set
 */
#define SCT_OUT_SET_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
/*! @} */

/* The count of SCT_OUT_SET */
#define SCT_OUT_SET_COUNT                        (10U)

/*! @name OUT_CLR - Output n Clear */
/*! @{ */
#define SCT_OUT_CLR_CLR_MASK                     (0xFFFFU)
#define SCT_OUT_CLR_CLR_SHIFT                    (0U)
/*! CLR - Clear
 */
#define SCT_OUT_CLR_CLR(x)                       (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
/*! @} */

/* The count of SCT_OUT_CLR */
#define SCT_OUT_CLR_COUNT                        (10U)


/*!
 * @}
 */ /* end of group SCT_Register_Masks */


/* SCT - Peripheral instance base addresses */
/** Peripheral SCT0 base address */
#define SCT0_BASE                                (0x40146000u)
/** Peripheral SCT0 base pointer */
#define SCT0                                     ((SCT_Type *)SCT0_BASE)
/** Array initializer of SCT peripheral base addresses */
#define SCT_BASE_ADDRS                           { SCT0_BASE }
/** Array initializer of SCT peripheral base pointers */
#define SCT_BASE_PTRS                            { SCT0 }

/*!
 * @}
 */ /* end of group SCT_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SEMA42 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer
 * @{
 */

/** SEMA42 - Register Layout Typedef */
typedef struct {
  __IO uint8_t GATE3;                              /**< Gate Register, offset: 0x0 */
  __IO uint8_t GATE2;                              /**< Gate Register, offset: 0x1 */
  __IO uint8_t GATE1;                              /**< Gate Register, offset: 0x2 */
  __IO uint8_t GATE0;                              /**< Gate Register, offset: 0x3 */
  __IO uint8_t GATE7;                              /**< Gate Register, offset: 0x4 */
  __IO uint8_t GATE6;                              /**< Gate Register, offset: 0x5 */
  __IO uint8_t GATE5;                              /**< Gate Register, offset: 0x6 */
  __IO uint8_t GATE4;                              /**< Gate Register, offset: 0x7 */
  __IO uint8_t GATE11;                             /**< Gate Register, offset: 0x8 */
  __IO uint8_t GATE10;                             /**< Gate Register, offset: 0x9 */
  __IO uint8_t GATE9;                              /**< Gate Register, offset: 0xA */
  __IO uint8_t GATE8;                              /**< Gate Register, offset: 0xB */
  __IO uint8_t GATE15;                             /**< Gate Register, offset: 0xC */
  __IO uint8_t GATE14;                             /**< Gate Register, offset: 0xD */
  __IO uint8_t GATE13;                             /**< Gate Register, offset: 0xE */
  __IO uint8_t GATE12;                             /**< Gate Register, offset: 0xF */
       uint8_t RESERVED_0[50];
  union {                                          /* offset: 0x42 */
    __I  uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
    __O  uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
  };
} SEMA42_Type;

/* ----------------------------------------------------------------------------
   -- SEMA42 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks
 * @{
 */

/*! @name GATE3 - Gate Register */
/*! @{ */
#define SEMA42_GATE3_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE3_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE3_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK)
/*! @} */

/*! @name GATE2 - Gate Register */
/*! @{ */
#define SEMA42_GATE2_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE2_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE2_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK)
/*! @} */

/*! @name GATE1 - Gate Register */
/*! @{ */
#define SEMA42_GATE1_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE1_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE1_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK)
/*! @} */

/*! @name GATE0 - Gate Register */
/*! @{ */
#define SEMA42_GATE0_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE0_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE0_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK)
/*! @} */

/*! @name GATE7 - Gate Register */
/*! @{ */
#define SEMA42_GATE7_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE7_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE7_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK)
/*! @} */

/*! @name GATE6 - Gate Register */
/*! @{ */
#define SEMA42_GATE6_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE6_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE6_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK)
/*! @} */

/*! @name GATE5 - Gate Register */
/*! @{ */
#define SEMA42_GATE5_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE5_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE5_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK)
/*! @} */

/*! @name GATE4 - Gate Register */
/*! @{ */
#define SEMA42_GATE4_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE4_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE4_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK)
/*! @} */

/*! @name GATE11 - Gate Register */
/*! @{ */
#define SEMA42_GATE11_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE11_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE11_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK)
/*! @} */

/*! @name GATE10 - Gate Register */
/*! @{ */
#define SEMA42_GATE10_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE10_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE10_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK)
/*! @} */

/*! @name GATE9 - Gate Register */
/*! @{ */
#define SEMA42_GATE9_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE9_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE9_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK)
/*! @} */

/*! @name GATE8 - Gate Register */
/*! @{ */
#define SEMA42_GATE8_GTFSM_MASK                  (0xFU)
#define SEMA42_GATE8_GTFSM_SHIFT                 (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE8_GTFSM(x)                    (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK)
/*! @} */

/*! @name GATE15 - Gate Register */
/*! @{ */
#define SEMA42_GATE15_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE15_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE15_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK)
/*! @} */

/*! @name GATE14 - Gate Register */
/*! @{ */
#define SEMA42_GATE14_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE14_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE14_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK)
/*! @} */

/*! @name GATE13 - Gate Register */
/*! @{ */
#define SEMA42_GATE13_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE13_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE13_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK)
/*! @} */

/*! @name GATE12 - Gate Register */
/*! @{ */
#define SEMA42_GATE12_GTFSM_MASK                 (0xFU)
#define SEMA42_GATE12_GTFSM_SHIFT                (0U)
/*! GTFSM - Gate Finite State Machine.
 *  0b0000..The gate is unlocked (free).
 *  0b0001..The gate has been locked by processor 0.
 *  0b0010..The gate has been locked by processor 1.
 *  0b0011..The gate has been locked by processor 2.
 *  0b0100..The gate has been locked by processor 3.
 *  0b0101..The gate has been locked by processor 4.
 *  0b0110..The gate has been locked by processor 5.
 *  0b0111..The gate has been locked by processor 6.
 *  0b1000..The gate has been locked by processor 7.
 *  0b1001..The gate has been locked by processor 8.
 *  0b1010..The gate has been locked by processor 9.
 *  0b1011..The gate has been locked by processor 10.
 *  0b1100..The gate has been locked by processor 11.
 *  0b1101..The gate has been locked by processor 12.
 *  0b1110..The gate has been locked by processor 13.
 *  0b1111..The gate has been locked by processor 14.
 */
#define SEMA42_GATE12_GTFSM(x)                   (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK)
/*! @} */

/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */
#define SEMA42_RSTGT_R_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_R_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset Gate Number
 */
#define SEMA42_RSTGT_R_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK)
#define SEMA42_RSTGT_R_RSTGMS_MASK               (0xF00U)
#define SEMA42_RSTGT_R_RSTGMS_SHIFT              (8U)
/*! RSTGMS - Reset Gate Bus Master
 */
#define SEMA42_RSTGT_R_RSTGMS(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK)
#define SEMA42_RSTGT_R_RSTGSM_MASK               (0x3000U)
#define SEMA42_RSTGT_R_RSTGSM_SHIFT              (12U)
/*! RSTGSM - Reset Gate Finite State Machine
 *  0b00..Idle, waiting for the first data pattern write.
 *  0b01..Waiting for the second data pattern write
 *  0b10..After the reset is performed, this machine returns to the idle (waiting for the first data pattern
 *        write) state. The "01" state persists for only a single clock cycle. Software cannot observe this state.
 *  0b11..This state encoding is never used and is therefore reserved.
 */
#define SEMA42_RSTGT_R_RSTGSM(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK)
#define SEMA42_RSTGT_R_ROZ_MASK                  (0xC000U)
#define SEMA42_RSTGT_R_ROZ_SHIFT                 (14U)
/*! ROZ - ROZ
 */
#define SEMA42_RSTGT_R_ROZ(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_ROZ_SHIFT)) & SEMA42_RSTGT_R_ROZ_MASK)
/*! @} */

/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */
#define SEMA42_RSTGT_W_RSTGTN_MASK               (0xFFU)
#define SEMA42_RSTGT_W_RSTGTN_SHIFT              (0U)
/*! RSTGTN - Reset Gate Number
 */
#define SEMA42_RSTGT_W_RSTGTN(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK)
#define SEMA42_RSTGT_W_RSTGDP_MASK               (0xFF00U)
#define SEMA42_RSTGT_W_RSTGDP_SHIFT              (8U)
/*! RSTGDP - Reset Gate Data Pattern
 */
#define SEMA42_RSTGT_W_RSTGDP(x)                 (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SEMA42_Register_Masks */


/* SEMA42 - Peripheral instance base addresses */
/** Peripheral SEMA42 base address */
#define SEMA42_BASE                              (0x40112000u)
/** Peripheral SEMA42 base pointer */
#define SEMA42                                   ((SEMA42_Type *)SEMA42_BASE)
/** Array initializer of SEMA42 peripheral base addresses */
#define SEMA42_BASE_ADDRS                        { SEMA42_BASE }
/** Array initializer of SEMA42 peripheral base pointers */
#define SEMA42_BASE_PTRS                         { SEMA42 }

/*!
 * @}
 */ /* end of group SEMA42_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SPI Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
 * @{
 */

/** SPI - Register Layout Typedef */
typedef struct {
       uint8_t RESERVED_0[1024];
  __IO uint32_t CFG;                               /**< Configuration Register, offset: 0x400 */
  __IO uint32_t DLY;                               /**< Delay Register, offset: 0x404 */
  __IO uint32_t STAT;                              /**< Status Register, offset: 0x408 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Register, offset: 0x40C */
  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear Register, offset: 0x410 */
       uint8_t RESERVED_1[16];
  __IO uint32_t DIV;                               /**< Clock Divider Register, offset: 0x424 */
  __I  uint32_t INTSTAT;                           /**< Interrupt Status Register, offset: 0x428 */
       uint8_t RESERVED_2[2516];
  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration Register, offset: 0xE00 */
  __IO uint32_t FIFOSTAT;                          /**< FIFO Status Register, offset: 0xE04 */
  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Register, offset: 0xE08 */
       uint8_t RESERVED_3[4];
  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable Register, offset: 0xE10 */
  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear Register, offset: 0xE14 */
  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status Register, offset: 0xE18 */
       uint8_t RESERVED_4[4];
  __O  uint32_t FIFOWR;                            /**< FIFO Write Data Register, offset: 0xE20 */
       uint8_t RESERVED_5[12];
  __I  uint32_t FIFORD;                            /**< FIFO Read Data Register, offset: 0xE30 */
       uint8_t RESERVED_6[12];
  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with no FIFO Pop Register, offset: 0xE40 */
       uint8_t RESERVED_7[4];
  __I  uint32_t FIFOSIZE;                          /**< FIFO Size Register, offset: 0xE48 */
       uint8_t RESERVED_8[432];
  __I  uint32_t ID;                                /**< Peripheral Identification Register, offset: 0xFFC */
} SPI_Type;

/* ----------------------------------------------------------------------------
   -- SPI Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SPI_Register_Masks SPI Register Masks
 * @{
 */

/*! @name CFG - Configuration Register */
/*! @{ */
#define SPI_CFG_ENABLE_MASK                      (0x1U)
#define SPI_CFG_ENABLE_SHIFT                     (0U)
/*! ENABLE - SPI Enable
 *  0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.
 *  0b1..Enabled. The SPI is enabled for operation.
 */
#define SPI_CFG_ENABLE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
#define SPI_CFG_MASTER_MASK                      (0x4U)
#define SPI_CFG_MASTER_SHIFT                     (2U)
/*! MASTER - Master Mode Select
 *  0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs; MISO is an output.
 *  0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs; MISO is an input.
 */
#define SPI_CFG_MASTER(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
#define SPI_CFG_LSBF_MASK                        (0x8U)
#define SPI_CFG_LSBF_SHIFT                       (3U)
/*! LSBF - LSB First Mode Enable
 *  0b0..Standard. Data is transmitted and received in standard MSB-first order.
 *  0b1..Reverse. Data is transmitted and received in reverse order (LSB first).
 */
#define SPI_CFG_LSBF(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
#define SPI_CFG_CPHA_MASK                        (0x10U)
#define SPI_CFG_CPHA_SHIFT                       (4U)
/*! CPHA - Clock Phase Select
 *  0b0..Change. The SPI captures serial data on the 1st clock transition of the transfer (when the clock changes
 *       away from the rest state); data is changed on the following edge.
 *  0b1..Capture. The SPI changes serial data on the 1st clock data is captured on the following edge.
 */
#define SPI_CFG_CPHA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
#define SPI_CFG_CPOL_MASK                        (0x20U)
#define SPI_CFG_CPOL_SHIFT                       (5U)
/*! CPOL - Clock Polarity Select
 *  0b0..Low. The rest state of the clock (between transfers) is low.
 *  0b1..High. The rest state of the clock (between transfers) is high.
 */
#define SPI_CFG_CPOL(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
#define SPI_CFG_LOOP_MASK                        (0x80U)
#define SPI_CFG_LOOP_SHIFT                       (7U)
/*! LOOP - Loopback Mode Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_CFG_LOOP(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
#define SPI_CFG_SPOL0_MASK                       (0x100U)
#define SPI_CFG_SPOL0_SHIFT                      (8U)
/*! SPOL0 - SSEL0 Polarity Select
 *  0b0..Low. The SSEL0 pin is active low.
 *  0b1..High. The SSEL0 pin is active high.
 */
#define SPI_CFG_SPOL0(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
#define SPI_CFG_SPOL1_MASK                       (0x200U)
#define SPI_CFG_SPOL1_SHIFT                      (9U)
/*! SPOL1 - SSEL1 Polarity Select
 *  0b0..Low. The SSEL1 pin is active low.
 *  0b1..High. The SSEL1 pin is active high.
 */
#define SPI_CFG_SPOL1(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
#define SPI_CFG_SPOL2_MASK                       (0x400U)
#define SPI_CFG_SPOL2_SHIFT                      (10U)
/*! SPOL2 - SSEL2 Polarity Select
 *  0b0..Low. The SSEL2 pin is active low.
 *  0b1..High. The SSEL2 pin is active high.
 */
#define SPI_CFG_SPOL2(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
#define SPI_CFG_SPOL3_MASK                       (0x800U)
#define SPI_CFG_SPOL3_SHIFT                      (11U)
/*! SPOL3 - SSEL3 Polarity Select
 *  0b0..Low. The SSEL3 pin is active low.
 *  0b1..High. The SSEL3 pin is active high.
 */
#define SPI_CFG_SPOL3(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
/*! @} */

/*! @name DLY - Delay Register */
/*! @{ */
#define SPI_DLY_PRE_DELAY_MASK                   (0xFU)
#define SPI_DLY_PRE_DELAY_SHIFT                  (0U)
/*! PRE_DELAY - Pre-Delay
 *  0b0000..No additional time is inserted
 *  0b0001..1 SPI clock time is inserted
 *  0b0010..2 SPI clock times are inserted
 *  0b1111..15 SPI clock times are inserted
 */
#define SPI_DLY_PRE_DELAY(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
#define SPI_DLY_POST_DELAY_MASK                  (0xF0U)
#define SPI_DLY_POST_DELAY_SHIFT                 (4U)
/*! POST_DELAY - Post-Delay
 *  0b0000..No additional time is inserted
 *  0b0001..1 SPI clock time is inserted
 *  0b0010..2 SPI clock times are inserted
 *  0b1111..15 SPI clock times are inserted
 */
#define SPI_DLY_POST_DELAY(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
#define SPI_DLY_FRAME_DELAY_MASK                 (0xF00U)
#define SPI_DLY_FRAME_DELAY_SHIFT                (8U)
/*! FRAME_DELAY - Frame Delay
 *  0b0000..No additional time is inserted
 *  0b0001..1 SPI clock time is inserted
 *  0b0010..2 SPI clock times are inserted
 *  0b1111..15 SPI clock times are inserted
 */
#define SPI_DLY_FRAME_DELAY(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
#define SPI_DLY_TRANSFER_DELAY_MASK              (0xF000U)
#define SPI_DLY_TRANSFER_DELAY_SHIFT             (12U)
/*! TRANSFER_DELAY - Transfer Delay
 *  0b0000..The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time)
 *  0b0001..The minimum time that SSEL is deasserted is 2 SPI clock times
 *  0b0010..The minimum time that SSEL is deasserted is 3 SPI clock times
 *  0b1111..The minimum time that SSEL is deasserted is 16 SPI clock times
 */
#define SPI_DLY_TRANSFER_DELAY(x)                (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
/*! @} */

/*! @name STAT - Status Register */
/*! @{ */
#define SPI_STAT_SSA_MASK                        (0x10U)
#define SPI_STAT_SSA_SHIFT                       (4U)
/*! SSA - Slave Select Assert
 */
#define SPI_STAT_SSA(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
#define SPI_STAT_SSD_MASK                        (0x20U)
#define SPI_STAT_SSD_SHIFT                       (5U)
/*! SSD - Slave Select Deassert
 */
#define SPI_STAT_SSD(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
#define SPI_STAT_STALLED_MASK                    (0x40U)
#define SPI_STAT_STALLED_SHIFT                   (6U)
/*! STALLED - Stalled Status Flag
 */
#define SPI_STAT_STALLED(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
#define SPI_STAT_ENDTRANSFER_MASK                (0x80U)
#define SPI_STAT_ENDTRANSFER_SHIFT               (7U)
/*! ENDTRANSFER - End Transfer Control
 */
#define SPI_STAT_ENDTRANSFER(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
#define SPI_STAT_MSTIDLE_MASK                    (0x100U)
#define SPI_STAT_MSTIDLE_SHIFT                   (8U)
/*! MSTIDLE - Master Idle Status Flag
 */
#define SPI_STAT_MSTIDLE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Register */
/*! @{ */
#define SPI_INTENSET_SSAEN_MASK                  (0x10U)
#define SPI_INTENSET_SSAEN_SHIFT                 (4U)
/*! SSAEN - Slave Select Assert Interrupt Enable
 *  0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.
 *  0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
 */
#define SPI_INTENSET_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
#define SPI_INTENSET_SSDEN_MASK                  (0x20U)
#define SPI_INTENSET_SSDEN_SHIFT                 (5U)
/*! SSDEN - Slave Select Deassert Interrupt Enable
 *  0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.
 *  0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
 */
#define SPI_INTENSET_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
#define SPI_INTENSET_MSTIDLEEN_MASK              (0x100U)
#define SPI_INTENSET_MSTIDLEEN_SHIFT             (8U)
/*! MSTIDLEEN - Master Idle Interrupt Enable
 *  0b0..No interrupt will be generated when the SPI master function is idle.
 *  0b1..An interrupt will be generated when the SPI master function is fully idle.
 */
#define SPI_INTENSET_MSTIDLEEN(x)                (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear Register */
/*! @{ */
#define SPI_INTENCLR_SSAEN_MASK                  (0x10U)
#define SPI_INTENCLR_SSAEN_SHIFT                 (4U)
/*! SSAEN - Slave Select Assert Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN])
 */
#define SPI_INTENCLR_SSAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
#define SPI_INTENCLR_SSDEN_MASK                  (0x20U)
#define SPI_INTENCLR_SSDEN_SHIFT                 (5U)
/*! SSDEN - Slave Select Deassert Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN])
 */
#define SPI_INTENCLR_SSDEN(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
#define SPI_INTENCLR_MSTIDLE_MASK                (0x100U)
#define SPI_INTENCLR_MSTIDLE_SHIFT               (8U)
/*! MSTIDLE - Master Idle Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE])
 */
#define SPI_INTENCLR_MSTIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
/*! @} */

/*! @name DIV - Clock Divider Register */
/*! @{ */
#define SPI_DIV_DIVVAL_MASK                      (0xFFFFU)
#define SPI_DIV_DIVVAL_SHIFT                     (0U)
/*! DIVVAL - Rate Divider Value
 */
#define SPI_DIV_DIVVAL(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt Status Register */
/*! @{ */
#define SPI_INTSTAT_SSA_MASK                     (0x10U)
#define SPI_INTSTAT_SSA_SHIFT                    (4U)
/*! SSA - Slave Select Assert Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_INTSTAT_SSA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
#define SPI_INTSTAT_SSD_MASK                     (0x20U)
#define SPI_INTSTAT_SSD_SHIFT                    (5U)
/*! SSD - Slave Select Deassert Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_INTSTAT_SSD(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
#define SPI_INTSTAT_MSTIDLE_MASK                 (0x100U)
#define SPI_INTSTAT_MSTIDLE_SHIFT                (8U)
/*! MSTIDLE - Master Idle Status Flag Interrupt
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SPI_INTSTAT_MSTIDLE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
/*! @} */

/*! @name FIFOCFG - FIFO Configuration Register */
/*! @{ */
#define SPI_FIFOCFG_ENABLETX_MASK                (0x1U)
#define SPI_FIFOCFG_ENABLETX_SHIFT               (0U)
/*! ENABLETX - Enable the Transmit FIFO
 *  0b0..The transmit FIFO is not enabled
 *  0b1..The transmit FIFO is enabled
 */
#define SPI_FIFOCFG_ENABLETX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
#define SPI_FIFOCFG_ENABLERX_MASK                (0x2U)
#define SPI_FIFOCFG_ENABLERX_SHIFT               (1U)
/*! ENABLERX - Enable the Receive FIFO
 *  0b0..The receive FIFO is not enabled
 *  0b1..The receive FIFO is enabled
 */
#define SPI_FIFOCFG_ENABLERX(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
#define SPI_FIFOCFG_SIZE_MASK                    (0x30U)
#define SPI_FIFOCFG_SIZE_SHIFT                   (4U)
/*! SIZE - FIFO Size Configuration
 *  0b00..FIFO is configured as 16 entries of 8 bits.
 *  0b01..FIFO is configured as 8 entries of 16 bits.
 *  0b10..Not used
 *  0b11..Not used
 */
#define SPI_FIFOCFG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
#define SPI_FIFOCFG_DMATX_MASK                   (0x1000U)
#define SPI_FIFOCFG_DMATX_SHIFT                  (12U)
/*! DMATX - DMA Configuration for Transmit
 *  0b0..DMA is not used for the transmit function
 *  0b1..Issues DMA request for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define SPI_FIFOCFG_DMATX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
#define SPI_FIFOCFG_DMARX_MASK                   (0x2000U)
#define SPI_FIFOCFG_DMARX_SHIFT                  (13U)
/*! DMARX - DMA Configuration for Receive
 *  0b0..DMA is not used for the receive function.
 *  0b1..Issues a DMA request for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define SPI_FIFOCFG_DMARX(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
#define SPI_FIFOCFG_WAKETX_MASK                  (0x4000U)
#define SPI_FIFOCFG_WAKETX_SHIFT                 (14U)
/*! WAKETX - Wake-up for Transmit FIFO Level
 *  0b0..Only enabled interrupts will wake up the device form reduced power modes
 *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in
 *       FIFOTRIG, even when the TXLVL interrupt is not enabled.
 */
#define SPI_FIFOCFG_WAKETX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
#define SPI_FIFOCFG_WAKERX_MASK                  (0x8000U)
#define SPI_FIFOCFG_WAKERX_SHIFT                 (15U)
/*! WAKERX - Wake-up for Receive FIFO Level
 *  0b0..Only enabled interrupts will wake up the device form reduced power modes.
 *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
 *       FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
 */
#define SPI_FIFOCFG_WAKERX(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
#define SPI_FIFOCFG_EMPTYTX_MASK                 (0x10000U)
#define SPI_FIFOCFG_EMPTYTX_SHIFT                (16U)
/*! EMPTYTX - Empty Command for the Transmit FIFO
 *  0b0..No effect
 *  0b1..The TX FIFO is emptied
 */
#define SPI_FIFOCFG_EMPTYTX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
#define SPI_FIFOCFG_EMPTYRX_MASK                 (0x20000U)
#define SPI_FIFOCFG_EMPTYRX_SHIFT                (17U)
/*! EMPTYRX - Empty Command for the Receive FIFO
 *  0b0..No effect
 *  0b1..The RX FIFO is emptied
 */
#define SPI_FIFOCFG_EMPTYRX(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
#define SPI_FIFOCFG_POPDBG_MASK                  (0x40000U)
#define SPI_FIFOCFG_POPDBG_SHIFT                 (18U)
/*! POPDBG - Pop FIFO for Debug Reads
 *  0b0..Debug reads of the FIFO do not pop the FIFO
 *  0b1..A debug read will cause the FIFO to pop
 */
#define SPI_FIFOCFG_POPDBG(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
/*! @} */

/*! @name FIFOSTAT - FIFO Status Register */
/*! @{ */
#define SPI_FIFOSTAT_TXERR_MASK                  (0x1U)
#define SPI_FIFOSTAT_TXERR_SHIFT                 (0U)
/*! TXERR - TX FIFO Error
 *  0b0..A transmit FIFO error has not occurred.
 *  0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
 *       FIFO, or by an underflow if the FIFO is empty when data is needed.
 */
#define SPI_FIFOSTAT_TXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
#define SPI_FIFOSTAT_RXERR_MASK                  (0x2U)
#define SPI_FIFOSTAT_RXERR_SHIFT                 (1U)
/*! RXERR - RX FIFO Error
 *  0b0..A receive FIFO overflow has not occurred
 *  0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
 */
#define SPI_FIFOSTAT_RXERR(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
#define SPI_FIFOSTAT_PERINT_MASK                 (0x8U)
#define SPI_FIFOSTAT_PERINT_SHIFT                (3U)
/*! PERINT - Peripheral Interrupt
 *  0b0..The peripheral function has not asserted an interrupt
 *  0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by
 *       reading the peripheral's status register (STAT).
 */
#define SPI_FIFOSTAT_PERINT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
#define SPI_FIFOSTAT_TXEMPTY_MASK                (0x10U)
#define SPI_FIFOSTAT_TXEMPTY_SHIFT               (4U)
/*! TXEMPTY - Transmit FIFO Empty
 *  0b0..The transmit FIFO is not empty
 *  0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
 */
#define SPI_FIFOSTAT_TXEMPTY(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
#define SPI_FIFOSTAT_TXNOTFULL_MASK              (0x20U)
#define SPI_FIFOSTAT_TXNOTFULL_SHIFT             (5U)
/*! TXNOTFULL - Transmit FIFO is Not Full
 *  0b0..The transmit FIFO is full and another write would cause it to overflow
 *  0b1..The transmit FIFO is not full, so more data can be written
 */
#define SPI_FIFOSTAT_TXNOTFULL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
#define SPI_FIFOSTAT_RXNOTEMPTY_MASK             (0x40U)
#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT            (6U)
/*! RXNOTEMPTY - Receive FIFO is Not Empty
 *  0b0..When 0, the receive FIFO is empty
 *  0b1..When 1, the receive FIFO is not empty, so data can be read
 */
#define SPI_FIFOSTAT_RXNOTEMPTY(x)               (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
#define SPI_FIFOSTAT_RXFULL_MASK                 (0x80U)
#define SPI_FIFOSTAT_RXFULL_SHIFT                (7U)
/*! RXFULL - Receive FIFO is Full
 *  0b0..The receive FIFO is not full
 *  0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out.
 */
#define SPI_FIFOSTAT_RXFULL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
#define SPI_FIFOSTAT_TXLVL_MASK                  (0x1F00U)
#define SPI_FIFOSTAT_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Current Level
 */
#define SPI_FIFOSTAT_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
#define SPI_FIFOSTAT_RXLVL_MASK                  (0x1F0000U)
#define SPI_FIFOSTAT_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Current Level
 */
#define SPI_FIFOSTAT_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
/*! @} */

/*! @name FIFOTRIG - FIFO Trigger Register */
/*! @{ */
#define SPI_FIFOTRIG_TXLVLENA_MASK               (0x1U)
#define SPI_FIFOTRIG_TXLVLENA_SHIFT              (0U)
/*! TXLVLENA - Transmit FIFO Level Trigger Enable
 *  0b0..Transmit FIFO level does not generate a FIFO level trigger
 *  0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the FIFOTRIG[TXLVL] field.
 */
#define SPI_FIFOTRIG_TXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
#define SPI_FIFOTRIG_RXLVLENA_MASK               (0x2U)
#define SPI_FIFOTRIG_RXLVLENA_SHIFT              (1U)
/*! RXLVLENA - Receive FIFO Level Trigger Enable
 *  0b0..Receive FIFO level does not generate a FIFO level trigger
 *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the FIFOTRIG[RXLVL] field.
 */
#define SPI_FIFOTRIG_RXLVLENA(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
#define SPI_FIFOTRIG_TXLVL_MASK                  (0xF00U)
#define SPI_FIFOTRIG_TXLVL_SHIFT                 (8U)
/*! TXLVL - Transmit FIFO Level Trigger Point
 *  0b0000..Trigger when the TX FIFO becomes empty
 *  0b0001..Trigger when the TX FIFO level decreases to 1 entry
 *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
 */
#define SPI_FIFOTRIG_TXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
#define SPI_FIFOTRIG_RXLVL_MASK                  (0xF0000U)
#define SPI_FIFOTRIG_RXLVL_SHIFT                 (16U)
/*! RXLVL - Receive FIFO Level Trigger Point
 *  0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
 *  0b0001..Trigger when the RX FIFO has received 2 entries
 *  0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
 */
#define SPI_FIFOTRIG_RXLVL(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENSET - FIFO Interrupt Enable Register */
/*! @{ */
#define SPI_FIFOINTENSET_TXERR_MASK              (0x1U)
#define SPI_FIFOINTENSET_TXERR_SHIFT             (0U)
/*! TXERR - TX Error Interrupt Enable
 *  0b0..No interrupt will be generated for a transmit error
 *  0b1..An interrupt will be generated when a transmit error occurs
 */
#define SPI_FIFOINTENSET_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
#define SPI_FIFOINTENSET_RXERR_MASK              (0x2U)
#define SPI_FIFOINTENSET_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No interrupt will be generated for a receive error
 *  0b1..An interrupt will be generated when a receive error occurs
 */
#define SPI_FIFOINTENSET_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
#define SPI_FIFOINTENSET_TXLVL_MASK              (0x4U)
#define SPI_FIFOINTENSET_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the TX FIFO level
 *  0b1..If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
 */
#define SPI_FIFOINTENSET_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
#define SPI_FIFOINTENSET_RXLVL_MASK              (0x8U)
#define SPI_FIFOINTENSET_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the RX FIFO level
 *  0b1..If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level increases to the level specified by FIFOTRIG[RXLVL]
 */
#define SPI_FIFOINTENSET_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear Register */
/*! @{ */
#define SPI_FIFOINTENCLR_TXERR_MASK              (0x1U)
#define SPI_FIFOINTENCLR_TXERR_SHIFT             (0U)
/*! TXERR - TX Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR]
 */
#define SPI_FIFOINTENCLR_TXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
#define SPI_FIFOINTENCLR_RXERR_MASK              (0x2U)
#define SPI_FIFOINTENCLR_RXERR_SHIFT             (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR]
 */
#define SPI_FIFOINTENCLR_RXERR(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
#define SPI_FIFOINTENCLR_TXLVL_MASK              (0x4U)
#define SPI_FIFOINTENCLR_TXLVL_SHIFT             (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL]
 */
#define SPI_FIFOINTENCLR_TXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
#define SPI_FIFOINTENCLR_RXLVL_MASK              (0x8U)
#define SPI_FIFOINTENCLR_RXLVL_SHIFT             (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL]
 */
#define SPI_FIFOINTENCLR_RXLVL(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTSTAT - FIFO Interrupt Status Register */
/*! @{ */
#define SPI_FIFOINTSTAT_TXERR_MASK               (0x1U)
#define SPI_FIFOINTSTAT_TXERR_SHIFT              (0U)
/*! TXERR - TX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_TXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
#define SPI_FIFOINTSTAT_RXERR_MASK               (0x2U)
#define SPI_FIFOINTSTAT_RXERR_SHIFT              (1U)
/*! RXERR - RX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_RXERR(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
#define SPI_FIFOINTSTAT_TXLVL_MASK               (0x4U)
#define SPI_FIFOINTSTAT_TXLVL_SHIFT              (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_TXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
#define SPI_FIFOINTSTAT_RXLVL_MASK               (0x8U)
#define SPI_FIFOINTSTAT_RXLVL_SHIFT              (3U)
/*! RXLVL - Receive FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_RXLVL(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
#define SPI_FIFOINTSTAT_PERINT_MASK              (0x10U)
#define SPI_FIFOINTSTAT_PERINT_SHIFT             (4U)
/*! PERINT - Peripheral Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define SPI_FIFOINTSTAT_PERINT(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
/*! @} */

/*! @name FIFOWR - FIFO Write Data Register */
/*! @{ */
#define SPI_FIFOWR_TXDATA_MASK                   (0xFFFFU)
#define SPI_FIFOWR_TXDATA_SHIFT                  (0U)
/*! TXDATA - Transmit Data to the FIFO
 */
#define SPI_FIFOWR_TXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
#define SPI_FIFOWR_TXSSEL0_N_MASK                (0x10000U)
#define SPI_FIFOWR_TXSSEL0_N_SHIFT               (16U)
/*! TXSSEL0_N - Transmit Slave Select 0
 *  0b0..SSEL0 is asserted
 *  0b1..SSEL0 is not asserted
 */
#define SPI_FIFOWR_TXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
#define SPI_FIFOWR_TXSSEL1_N_MASK                (0x20000U)
#define SPI_FIFOWR_TXSSEL1_N_SHIFT               (17U)
/*! TXSSEL1_N - Transmit Slave Select 1
 *  0b0..SSEL1 is asserted
 *  0b1..SSEL1 is not asserted
 */
#define SPI_FIFOWR_TXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
#define SPI_FIFOWR_TXSSEL2_N_MASK                (0x40000U)
#define SPI_FIFOWR_TXSSEL2_N_SHIFT               (18U)
/*! TXSSEL2_N - Transmit Slave Select 2
 *  0b0..SSEL2 is asserted
 *  0b1..SSEL2 is not asserted
 */
#define SPI_FIFOWR_TXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
#define SPI_FIFOWR_TXSSEL3_N_MASK                (0x80000U)
#define SPI_FIFOWR_TXSSEL3_N_SHIFT               (19U)
/*! TXSSEL3_N - Transmit Slave Select 3
 *  0b0..SSEL3 is asserted
 *  0b1..SSEL3 is not asserted
 */
#define SPI_FIFOWR_TXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
#define SPI_FIFOWR_EOT_MASK                      (0x100000U)
#define SPI_FIFOWR_EOT_SHIFT                     (20U)
/*! EOT - End of Transfer
 *  0b0..SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.
 *  0b1..SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.
 */
#define SPI_FIFOWR_EOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
#define SPI_FIFOWR_EOF_MASK                      (0x200000U)
#define SPI_FIFOWR_EOF_SHIFT                     (21U)
/*! EOF - End of Frame
 *  0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.
 *  0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be
 *       inserted before subsequent data is transmitted.
 */
#define SPI_FIFOWR_EOF(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
#define SPI_FIFOWR_RXIGNORE_MASK                 (0x400000U)
#define SPI_FIFOWR_RXIGNORE_SHIFT                (22U)
/*! RXIGNORE - Receive Ignore
 *  0b0..Read received data. Received data must be read, to allow transmission to proceed. SPI transmit will halt
 *       when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not
 *       read before new data is received.
 *  0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received
 *       data. No receiver flags are generated.
 */
#define SPI_FIFOWR_RXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
#define SPI_FIFOWR_TXIGNORE_MASK                 (0x800000U)
#define SPI_FIFOWR_TXIGNORE_SHIFT                (23U)
/*! TXIGNORE - Transmit Ignore
 *  0b0..Write transmit data. Transmit data must be written for each data exchange between master and slave. In
 *       slave mode, an underrun error occurs if transmit data is not provided before needed in a data frame.
 *  0b1..Ignore transmit data. Data can be received without transmitting data (after FIFOWR has been initialized
 *       to set TXIGNORE). No transmitter flags are generated. When configured with TXIGNORE = 1, the slave sets the
 *       data to always 0.
 */
#define SPI_FIFOWR_TXIGNORE(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK)
#define SPI_FIFOWR_LEN_MASK                      (0xF000000U)
#define SPI_FIFOWR_LEN_SHIFT                     (24U)
/*! LEN - Data Length
 *  0b0000..Reserved
 *  0b0001..Reserved
 *  0b0010..Reserved
 *  0b0011..Data transfer is 4 bits in length
 *  0b0100..Data transfer is 5 bits in length
 *  0b1111..Data transfer is 16 bits in length
 */
#define SPI_FIFOWR_LEN(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
/*! @} */

/*! @name FIFORD - FIFO Read Data Register */
/*! @{ */
#define SPI_FIFORD_RXDATA_MASK                   (0xFFFFU)
#define SPI_FIFORD_RXDATA_SHIFT                  (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define SPI_FIFORD_RXDATA(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
#define SPI_FIFORD_RXSSEL0_N_MASK                (0x10000U)
#define SPI_FIFORD_RXSSEL0_N_SHIFT               (16U)
/*! RXSSEL0_N - Slave Select 0 for Receive
 *  0b0..Slave Select 0 is active
 *  0b1..Slave Select 0 is not active
 */
#define SPI_FIFORD_RXSSEL0_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
#define SPI_FIFORD_RXSSEL1_N_MASK                (0x20000U)
#define SPI_FIFORD_RXSSEL1_N_SHIFT               (17U)
/*! RXSSEL1_N - Slave Select 1 for Receive
 *  0b0..Slave Select 1 is active
 *  0b1..Slave Select 1 is not active
 */
#define SPI_FIFORD_RXSSEL1_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
#define SPI_FIFORD_RXSSEL2_N_MASK                (0x40000U)
#define SPI_FIFORD_RXSSEL2_N_SHIFT               (18U)
/*! RXSSEL2_N - Slave Select 2 for Receive
 *  0b0..Slave Select 2 is active
 *  0b1..Slave Select 2 is not active
 */
#define SPI_FIFORD_RXSSEL2_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
#define SPI_FIFORD_RXSSEL3_N_MASK                (0x80000U)
#define SPI_FIFORD_RXSSEL3_N_SHIFT               (19U)
/*! RXSSEL3_N - Slave Select 3 for Receive
 *  0b0..Slave Select 3 is active
 *  0b1..Slave Select 3 is not active
 */
#define SPI_FIFORD_RXSSEL3_N(x)                  (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
#define SPI_FIFORD_SOT_MASK                      (0x100000U)
#define SPI_FIFORD_SOT_SHIFT                     (20U)
/*! SOT - Start of Transfer Flag
 *  0b0..This is not the 1st data after the SSELs went from deasserted to asserted
 *  0b1..This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previous transfer has
 *       ended). This information can be used to identify the 1st piece of data in cases where the transfer length is
 *       greater than 16 bits.
 */
#define SPI_FIFORD_SOT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
/*! @} */

/*! @name FIFORDNOPOP - FIFO Data Read with no FIFO Pop Register */
/*! @{ */
#define SPI_FIFORDNOPOP_RXDATA_MASK              (0xFFFFU)
#define SPI_FIFORDNOPOP_RXDATA_SHIFT             (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define SPI_FIFORDNOPOP_RXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK           (0x10000U)
#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT          (16U)
/*! RXSSEL0_N - Slave Select 0 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL0_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK           (0x20000U)
#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT          (17U)
/*! RXSSEL1_N - Slave Select 1 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL1_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK           (0x40000U)
#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT          (18U)
/*! RXSSEL2_N - Slave Select 2 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL2_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK           (0x80000U)
#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT          (19U)
/*! RXSSEL3_N - Slave Select 3 for Receive
 *  0b0..Not selected
 *  0b1..Selected
 */
#define SPI_FIFORDNOPOP_RXSSEL3_N(x)             (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
#define SPI_FIFORDNOPOP_SOT_MASK                 (0x100000U)
#define SPI_FIFORDNOPOP_SOT_SHIFT                (20U)
/*! SOT - Start of Transfer Flag
 *  0b0..Not active
 *  0b1..Active
 */
#define SPI_FIFORDNOPOP_SOT(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
/*! @} */

/*! @name FIFOSIZE - FIFO Size Register */
/*! @{ */
#define SPI_FIFOSIZE_FIFOSIZE_MASK               (0x1FU)
#define SPI_FIFOSIZE_FIFOSIZE_SHIFT              (0U)
/*! FIFOSIZE - FIFO Size
 */
#define SPI_FIFOSIZE_FIFOSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK)
/*! @} */

/*! @name ID - Peripheral Identification Register */
/*! @{ */
#define SPI_ID_APERTURE_MASK                     (0xFFU)
#define SPI_ID_APERTURE_SHIFT                    (0U)
/*! APERTURE - Aperture
 */
#define SPI_ID_APERTURE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
#define SPI_ID_MINOR_REV_MASK                    (0xF00U)
#define SPI_ID_MINOR_REV_SHIFT                   (8U)
/*! MINOR_REV - Minor revision of module implementation
 */
#define SPI_ID_MINOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
#define SPI_ID_MAJOR_REV_MASK                    (0xF000U)
#define SPI_ID_MAJOR_REV_SHIFT                   (12U)
/*! MAJOR_REV - Major revision of module implementation
 */
#define SPI_ID_MAJOR_REV(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
#define SPI_ID_ID_MASK                           (0xFFFF0000U)
#define SPI_ID_ID_SHIFT                          (16U)
/*! ID - Module identifier for the selected function
 */
#define SPI_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SPI_Register_Masks */


/* SPI - Peripheral instance base addresses */
/** Peripheral SPI0 base address */
#define SPI0_BASE                                (0x40106000u)
/** Peripheral SPI0 base pointer */
#define SPI0                                     ((SPI_Type *)SPI0_BASE)
/** Peripheral SPI1 base address */
#define SPI1_BASE                                (0x40107000u)
/** Peripheral SPI1 base pointer */
#define SPI1                                     ((SPI_Type *)SPI1_BASE)
/** Peripheral SPI2 base address */
#define SPI2_BASE                                (0x40108000u)
/** Peripheral SPI2 base pointer */
#define SPI2                                     ((SPI_Type *)SPI2_BASE)
/** Peripheral SPI3 base address */
#define SPI3_BASE                                (0x40109000u)
/** Peripheral SPI3 base pointer */
#define SPI3                                     ((SPI_Type *)SPI3_BASE)
/** Peripheral SPI4 base address */
#define SPI4_BASE                                (0x40122000u)
/** Peripheral SPI4 base pointer */
#define SPI4                                     ((SPI_Type *)SPI4_BASE)
/** Peripheral SPI5 base address */
#define SPI5_BASE                                (0x40123000u)
/** Peripheral SPI5 base pointer */
#define SPI5                                     ((SPI_Type *)SPI5_BASE)
/** Peripheral SPI6 base address */
#define SPI6_BASE                                (0x40124000u)
/** Peripheral SPI6 base pointer */
#define SPI6                                     ((SPI_Type *)SPI6_BASE)
/** Peripheral SPI7 base address */
#define SPI7_BASE                                (0x40125000u)
/** Peripheral SPI7 base pointer */
#define SPI7                                     ((SPI_Type *)SPI7_BASE)
/** Peripheral SPI8 base address */
#define SPI8_BASE                                (0x40209000u)
/** Peripheral SPI8 base pointer */
#define SPI8                                     ((SPI_Type *)SPI8_BASE)
/** Peripheral SPI9 base address */
#define SPI9_BASE                                (0x4020A000u)
/** Peripheral SPI9 base pointer */
#define SPI9                                     ((SPI_Type *)SPI9_BASE)
/** Peripheral SPI10 base address */
#define SPI10_BASE                               (0x4020B000u)
/** Peripheral SPI10 base pointer */
#define SPI10                                    ((SPI_Type *)SPI10_BASE)
/** Peripheral SPI11 base address */
#define SPI11_BASE                               (0x4020C000u)
/** Peripheral SPI11 base pointer */
#define SPI11                                    ((SPI_Type *)SPI11_BASE)
/** Peripheral SPI12 base address */
#define SPI12_BASE                               (0x4020D000u)
/** Peripheral SPI12 base pointer */
#define SPI12                                    ((SPI_Type *)SPI12_BASE)
/** Peripheral SPI13 base address */
#define SPI13_BASE                               (0x4020E000u)
/** Peripheral SPI13 base pointer */
#define SPI13                                    ((SPI_Type *)SPI13_BASE)
/** Peripheral SPI14 base address */
#define SPI14_BASE                               (0x40126000u)
/** Peripheral SPI14 base pointer */
#define SPI14                                    ((SPI_Type *)SPI14_BASE)
/** Peripheral SPI16 base address */
#define SPI16_BASE                               (0x40128000u)
/** Peripheral SPI16 base pointer */
#define SPI16                                    ((SPI_Type *)SPI16_BASE)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE, SPI10_BASE, SPI11_BASE, SPI12_BASE, SPI13_BASE, SPI14_BASE, SPI16_BASE }
/** Array initializer of SPI peripheral base pointers */
#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9, SPI10, SPI11, SPI12, SPI13, SPI14, SPI16 }
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS                                 { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, FLEXCOMM14_IRQn, FLEXCOMM16_IRQn }

/*!
 * @}
 */ /* end of group SPI_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCTL0 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCTL0_Peripheral_Access_Layer SYSCTL0 Peripheral Access Layer
 * @{
 */

/** SYSCTL0 - Register Layout Typedef */
typedef struct {
  __IO uint32_t UPDATECLKOUT;                      /**< Update Clock Lockout, offset: 0x0 */
  __IO uint32_t DSP_VECT_REMAP;                    /**< DSP Vector Remap, offset: 0x4 */
       uint8_t RESERVED_0[4];
  __IO uint32_t DSPSTALL;                          /**< DSP Stall Control, offset: 0xC */
  __IO uint32_t AHBMATRIXPRIOR;                    /**< AHB MAX Priority, offset: 0x10 */
  __IO uint32_t PACKERENABLE;                      /**< Packer Enable, offset: 0x14 */
       uint8_t RESERVED_1[8];
  __IO uint32_t AHBBRIDGEBUFFER[2];                /**< AHB Buffer, array offset: 0x20, array step: 0x4 */
       uint8_t RESERVED_2[4];
  __IO uint32_t BOOTROM_LCKOUT;                    /**< BOOT ROM lockout, offset: 0x2C */
  __IO uint32_t M33NMISRCSEL;                      /**< M33 NMI source selection, offset: 0x30 */
  __IO uint32_t SYSTEM_STICK_CALIB;                /**< System secure tick calibration, offset: 0x34 */
  __IO uint32_t SYSTEM_NSTICK_CALIB;               /**< System non-secure tick calibration, offset: 0x38 */
  __IO uint32_t CONFIG_LCKOUT;                     /**< System Configuration Lock-Out, offset: 0x3C */
  __IO uint32_t SRAMCFGENABLE0;                    /**< System SRAM Configuration Enable, offset: 0x40 */
  __I  uint32_t SRAMCFGENABLE1;                    /**< System SRAM Configuration Enable, offset: 0x44 */
       uint8_t RESERVED_3[4];
  __IO uint32_t SOFTPARTCFG;                       /**< Software configuration, offset: 0x4C */
  __IO uint32_t PERICFGENABLE0;                    /**< PERICFG Enable 0, offset: 0x50 */
  __IO uint32_t PERICFGENABLE1;                    /**< PERICFG Enable 1, offset: 0x54 */
  __IO uint32_t PERICFGENABLE2;                    /**< PERICFG Enable 2, offset: 0x58 */
       uint8_t RESERVED_4[4];
  __IO uint32_t PRODUCT_ID;                        /**< Product ID, offset: 0x60 */
  __I  uint32_t SILICONREV_ID;                     /**< Silicon Revision ID, offset: 0x64 */
  __I  uint32_t JTAG_ID;                           /**< JTAG ID, offset: 0x68 */
       uint8_t RESERVED_5[4];
  __IO uint32_t NSGPIO_PSYNC;                      /**< Non-secure GPIO PSYNC, offset: 0x70 */
  __IO uint32_t SGPIO_PSYNC;                       /**< Secure GPIO PSYNC, offset: 0x74 */
       uint8_t RESERVED_6[8];
  __IO uint32_t AUTOCLKGATEOVERRIDE0;              /**< Auto clock gate override 0, offset: 0x80 */
  __IO uint32_t AUTOCLKGATEOVERRIDE1;              /**< Auto clock gate override 1, offset: 0x84 */
       uint8_t RESERVED_7[24];
  __IO uint32_t CLKGATEOVERRIDE0;                  /**< Clock gate override 0, offset: 0xA0 */
       uint8_t RESERVED_8[88];
  __IO uint32_t AHB_SRAM_ACCESS_DISABLE;           /**< AHB SRAM access disable, offset: 0xFC */
  __IO uint32_t AXI_SRAM_ACCESS_DISABLE;           /**< AXI SRAM access disable, offset: 0x100 */
  __IO uint32_t DSP_SRAM_ACCESS_DISABLE;           /**< DSP SRAM access disable, offset: 0x104 */
  __IO uint32_t AUTO_SRAM_DISABLE;                 /**< AUTO SRAM disable, offset: 0x108 */
  __IO uint32_t AUTO_SRAM_STDBY_DISABLE;           /**< AUTO SRAM Standby disable, offset: 0x10C */
  __IO uint32_t PQ_MEM_CTRL;                       /**< Power-Quad Memory Control, offset: 0x110 */
  __IO uint32_t FLEXSPI0_MEM_CTRL;                 /**< FlexSPI0 Memory Control, offset: 0x114 */
  __IO uint32_t USBHS_MEM_CTRL;                    /**< USBHS Memory Control, offset: 0x118 */
  __IO uint32_t USDHC0_MEM_CTRL;                   /**< USDHC0 Memory Control, offset: 0x11C */
  __IO uint32_t USDHC1_MEM_CTRL;                   /**< USDHC1 Memory Control, offset: 0x120 */
  __IO uint32_t CASPER_MEM_CTRL;                   /**< CASPER Memory Control, offset: 0x124 */
  __IO uint32_t ROM_MEM_CTRL;                      /**< ROM Memory Control, offset: 0x128 */
  __IO uint32_t FLEXSPI1_MEM_CTRL;                 /**< FlexSPI1 Memory Control, offset: 0x12C */
  __IO uint32_t GPU_MEM_CTRL;                      /**< GPU Memory Control, offset: 0x130 */
  __IO uint32_t MIPI_MEM_CTRL;                     /**< MIPI Memory Control, offset: 0x134 */
  __IO uint32_t DCN_MEM_CTRL;                      /**< LCDIF Memory Control, offset: 0x138 */
  __IO uint32_t SMARTDMA_MEM_CTRL;                 /**< SMARTDMA Memory Control, offset: 0x13C */
       uint8_t RESERVED_9[576];
  __IO uint32_t OQSPI_BOOTROM_SCRATCHN;            /**< OQSPI BOOTROM Scratch, offset: 0x380 */
       uint8_t RESERVED_10[28];
  __IO uint32_t CLOUSTON_PORRST_DR0;               /**< CLOUSTON PORRST DR0, offset: 0x3A0 */
  __IO uint32_t CLOUSTON_PORRST_DR1;               /**< CLOUSTON PORRST DR1, offset: 0x3A4 */
  __IO uint32_t CLOUSTON_ALLRST_DR0;               /**< CLOUSTON ALLRST DR0, offset: 0x3A8 */
  __IO uint32_t CLOUSTON_ALLRST_DR1;               /**< CLOUSTON ALLRST DR1, offset: 0x3AC */
       uint8_t RESERVED_11[64];
  __IO uint32_t SCRATCHN;                          /**< Scratch, offset: 0x3F0 */
       uint8_t RESERVED_12[12];
  __IO uint32_t MIPI_DSI_CTRL;                     /**< MIPI DSI Control, offset: 0x400 */
       uint8_t RESERVED_13[8];
  __IO uint32_t USB0CLKCTRL;                       /**< USB Clock Control, offset: 0x40C */
  __I  uint32_t USB0CLKSTAT;                       /**< USB Clock Status, offset: 0x410 */
  __IO uint32_t USBPHYPLL0LOCKTIMEDIV2;            /**< USB PHY PLL0 lock time division, offset: 0x414 */
       uint8_t RESERVED_14[488];
  __IO uint32_t PDSLEEPCFG0;                       /**< Sleep configuration 0, offset: 0x600 */
  __IO uint32_t PDSLEEPCFG1;                       /**< Sleep configuration 1, offset: 0x604 */
  __IO uint32_t PDSLEEPCFG2;                       /**< Sleep configuration 2, offset: 0x608 */
  __IO uint32_t PDSLEEPCFG3;                       /**< Sleep configuration 3, offset: 0x60C */
  __IO uint32_t PDRUNCFG0;                         /**< Run configuration 0, offset: 0x610 */
  __IO uint32_t PDRUNCFG1;                         /**< Run configuration 1, offset: 0x614 */
  __IO uint32_t PDRUNCFG2;                         /**< Run configuration 2, offset: 0x618 */
  __IO uint32_t PDRUNCFG3;                         /**< Run configuration 3, offset: 0x61C */
  __O  uint32_t PDRUNCFG0_SET;                     /**< Run configuration 0 set, offset: 0x620 */
  __O  uint32_t PDRUNCFG1_SET;                     /**< Run configuration 1 set, offset: 0x624 */
  __O  uint32_t PDRUNCFG2_SET;                     /**< Run configuration 2 set, offset: 0x628 */
  __O  uint32_t PDRUNCFG3_SET;                     /**< Run configuration 3 set, offset: 0x62C */
  __O  uint32_t PDRUNCFG0_CLR;                     /**< Run configuration 0 clear, offset: 0x630 */
  __O  uint32_t PDRUNCFG1_CLR;                     /**< Run configuration 1 clear, offset: 0x634 */
  __IO uint32_t PDRUNCFG2_CLR;                     /**< Run configuration 2 clear, offset: 0x638 */
  __IO uint32_t PDRUNCFG3_CLR;                     /**< Run configuration 3 clear, offset: 0x63C */
       uint8_t RESERVED_15[32];
  __IO uint32_t PDWAKECFG;                         /**< PD Wake Configuration, offset: 0x660 */
       uint8_t RESERVED_16[28];
  __IO uint32_t STARTEN0;                          /**< Start Enable 0, offset: 0x680 */
  __IO uint32_t STARTEN1;                          /**< Start Enable 1, offset: 0x684 */
       uint8_t RESERVED_17[24];
  __IO uint32_t STARTEN0_SET;                      /**< Start Enable 0 Set, offset: 0x6A0 */
  __O  uint32_t STARTEN1_SET;                      /**< Start Enable 1 Set, offset: 0x6A4 */
       uint8_t RESERVED_18[24];
  __IO uint32_t STARTEN0_CLR;                      /**< Start Enable 0 clear, offset: 0x6C0 */
  __O  uint32_t STARTEN1_CLR;                      /**< Start Enable 1 clear, offset: 0x6C4 */
       uint8_t RESERVED_19[184];
  __IO uint32_t HWWAKE;                            /**< Hardware Wake, offset: 0x780 */
       uint8_t RESERVED_20[1672];
  __IO uint32_t TEMPSENSORCTL;                     /**< Temperature Sensor Control, offset: 0xE0C */
  __IO uint32_t DSPMEMSPEEDCTL;                    /**< DSP Memory Speed Control, offset: 0xE10 */
       uint8_t RESERVED_21[188];
  __IO uint32_t DBG_CTRL;                          /**< Debug Control, offset: 0xED0 */
       uint8_t RESERVED_22[12];
  __IO uint32_t TESTCLK_TRIM;                      /**< Test Clock Trim, offset: 0xEE0 */
       uint8_t RESERVED_23[12];
  __IO uint32_t FLEXSPI0PADCTL;                    /**< FLEXSPI0 Pad Control, offset: 0xEF0 */
  __IO uint32_t FLEXSPI1PADCTL;                    /**< FLEXSPI1 Pad Control, offset: 0xEF4 */
  __IO uint32_t SDIO0PADCTL;                       /**< SDIO0 Pad Control, offset: 0xEF8 */
  __IO uint32_t SDIO1PADCTL;                       /**< SDIO1 Pad Control, offset: 0xEFC */
  __IO uint32_t DICEHWREGN;                        /**< Compound Device Identifier (CDI), offset: 0xF00 */
       uint8_t RESERVED_24[28];
  __IO uint32_t MIPI_DSI_TEST_IN1;                 /**< MIPI DSI Test IN1, offset: 0xF20 */
  __IO uint32_t MIPI_DSI_TEST_IN2;                 /**< MIPI DSI Test IN2, offset: 0xF24 */
  __I  uint32_t MIPI_DSI_TEST_OUT1;                /**< MIPI DSI Test OUT1, offset: 0xF28 */
  __I  uint32_t MIPI_DSI_TEST_OUT2;                /**< MIPI DSI Test OUT2, offset: 0xF2C */
  __O  uint32_t S0AES_UV;                          /**< S0AES UV, offset: 0xF30 */
  __IO uint32_t S0AES_UV_WLOCK;                    /**< S0AES UV WLOCK, offset: 0xF34 */
  __O  uint32_t S1UDS_UV;                          /**< S1UDS UV, offset: 0xF38 */
  __IO uint32_t S1UDS_UV_WLOCK;                    /**< S1UDS UV WLOCK, offset: 0xF3C */
  __I  uint32_t UDS_SEED;                          /**< UDS SEED, offset: 0xF40 */
  __IO uint32_t UDS_SEED_RLOCK;                    /**< UDS SEED RLOCK, offset: 0xF44 */
       uint8_t RESERVED_25[8];
  __IO uint32_t UUID[4];                           /**< UUID, array offset: 0xF50, array step: 0x4 */
  __IO uint32_t UUID_WLOCK;                        /**< UUID WLOCK, offset: 0xF60 */
       uint8_t RESERVED_26[28];
  __IO uint32_t AESKEY_SRCSEL;                     /**< AES Key Source Select, offset: 0xF80 */
  __IO uint32_t OTFADKEY_SRCSEL;                   /**< OTFAD Key Source Select, offset: 0xF84 */
       uint8_t RESERVED_27[24];
  __IO uint32_t DBG_LOCKEN;                        /**< Debug Lock Enable, offset: 0xFA0 */
  __IO uint32_t DBG_FEATURES;                      /**< Debug Features, offset: 0xFA4 */
  __IO uint32_t DBG_FEATURES_DP;                   /**< Debug Features Duplicate, offset: 0xFA8 */
  __IO uint32_t HWUNLOCK_DISABLE;                  /**< HW Unlock / Disable, offset: 0xFAC */
  __IO uint32_t CS_PROTTEST;                       /**< Code Security for TAP Enable, offset: 0xFB0 */
  __IO uint32_t CS_PROTCPU0;                       /**< Code Security for CPU0, offset: 0xFB4 */
  __IO uint32_t CS_PROTCPU1;                       /**< Code Security for CPU1, offset: 0xFB8 */
       uint8_t RESERVED_28[4];
  __IO uint32_t DBG_AUTH_SCRATCH;                  /**< Debug authorization scratch, offset: 0xFC0 */
       uint8_t RESERVED_29[12];
  __IO uint32_t KEY_BLOCK;                         /**< Key block, offset: 0xFD0 */
} SYSCTL0_Type;

/* ----------------------------------------------------------------------------
   -- SYSCTL0 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCTL0_Register_Masks SYSCTL0 Register Masks
 * @{
 */

/*! @name UPDATECLKOUT - Update Clock Lockout */
/*! @{ */
#define SYSCTL0_UPDATECLKOUT_UPDATECLKOUT_MASK   (0x1U)
#define SYSCTL0_UPDATECLKOUT_UPDATECLKOUT_SHIFT  (0U)
/*! UPDATECLKOUT - Update Clock Lockout
 *  0b0..Normal mode
 *  0b1..Protected mode
 */
#define SYSCTL0_UPDATECLKOUT_UPDATECLKOUT(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_UPDATECLKOUT_UPDATECLKOUT_SHIFT)) & SYSCTL0_UPDATECLKOUT_UPDATECLKOUT_MASK)
/*! @} */

/*! @name DSP_VECT_REMAP - DSP Vector Remap */
/*! @{ */
#define SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_MASK (0xFFFU)
#define SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_SHIFT (0U)
/*! DSP_VECT_REMAP - DSP_VECT_REMAP
 */
#define SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_SHIFT)) & SYSCTL0_DSP_VECT_REMAP_DSP_VECT_REMAP_MASK)
#define SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_MASK (0x1000U)
#define SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_SHIFT (12U)
/*! STATVECSELECT - Static Vector Select
 *  0b0..Selects the primary static vector base address on Fusion DSP (0x0000_0000)
 *  0b1..Selects the alternate static vector base address on Fusion DSP (0x0040_0000)
 */
#define SYSCTL0_DSP_VECT_REMAP_STATVECSELECT(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_SHIFT)) & SYSCTL0_DSP_VECT_REMAP_STATVECSELECT_MASK)
/*! @} */

/*! @name DSPSTALL - DSP Stall Control */
/*! @{ */
#define SYSCTL0_DSPSTALL_DSPSTALL_MASK           (0x1U)
#define SYSCTL0_DSPSTALL_DSPSTALL_SHIFT          (0U)
/*! DSPSTALL - DSPSTALL
 *  0b0..Run(Normal mode)
 *  0b1..Stall mode
 */
#define SYSCTL0_DSPSTALL_DSPSTALL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSPSTALL_DSPSTALL_SHIFT)) & SYSCTL0_DSPSTALL_DSPSTALL_MASK)
/*! @} */

/*! @name AHBMATRIXPRIOR - AHB MAX Priority */
/*! @{ */
#define SYSCTL0_AHBMATRIXPRIOR_M0_MASK           (0x3U)
#define SYSCTL0_AHBMATRIXPRIOR_M0_SHIFT          (0U)
/*! M0 - Master 0 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M0_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M0_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M1_MASK           (0xCU)
#define SYSCTL0_AHBMATRIXPRIOR_M1_SHIFT          (2U)
/*! M1 - Master 1 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M1_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M1_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M2_MASK           (0x30U)
#define SYSCTL0_AHBMATRIXPRIOR_M2_SHIFT          (4U)
/*! M2 - Master 2 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M2_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M2_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M3_MASK           (0xC0U)
#define SYSCTL0_AHBMATRIXPRIOR_M3_SHIFT          (6U)
/*! M3 - Master 3 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M3_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M3_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M4_MASK           (0x300U)
#define SYSCTL0_AHBMATRIXPRIOR_M4_SHIFT          (8U)
/*! M4 - Master 4 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M4_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M4_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M5_MASK           (0xC00U)
#define SYSCTL0_AHBMATRIXPRIOR_M5_SHIFT          (10U)
/*! M5 - Master 5 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M5(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M5_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M5_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M6_MASK           (0x3000U)
#define SYSCTL0_AHBMATRIXPRIOR_M6_SHIFT          (12U)
/*! M6 - Master 6 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M6(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M6_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M6_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M7_MASK           (0xC000U)
#define SYSCTL0_AHBMATRIXPRIOR_M7_SHIFT          (14U)
/*! M7 - Master 7 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M7(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M7_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M7_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M8_MASK           (0x30000U)
#define SYSCTL0_AHBMATRIXPRIOR_M8_SHIFT          (16U)
/*! M8 - Master 8 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M8(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M8_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M8_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M9_MASK           (0xC0000U)
#define SYSCTL0_AHBMATRIXPRIOR_M9_SHIFT          (18U)
/*! M9 - Master 9 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M9(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M9_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M9_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M10_MASK          (0x300000U)
#define SYSCTL0_AHBMATRIXPRIOR_M10_SHIFT         (20U)
/*! M10 - Master 10 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M10(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M10_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M10_MASK)
#define SYSCTL0_AHBMATRIXPRIOR_M11_MASK          (0xC00000U)
#define SYSCTL0_AHBMATRIXPRIOR_M11_SHIFT         (22U)
/*! M11 - Master 10 Priority
 */
#define SYSCTL0_AHBMATRIXPRIOR_M11(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBMATRIXPRIOR_M11_SHIFT)) & SYSCTL0_AHBMATRIXPRIOR_M11_MASK)
/*! @} */

/*! @name PACKERENABLE - Packer Enable */
/*! @{ */
#define SYSCTL0_PACKERENABLE_WPRENABLE_MASK      (0x1U)
#define SYSCTL0_PACKERENABLE_WPRENABLE_SHIFT     (0U)
/*! WPRENABLE - Writer Packer Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_PACKERENABLE_WPRENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PACKERENABLE_WPRENABLE_SHIFT)) & SYSCTL0_PACKERENABLE_WPRENABLE_MASK)
#define SYSCTL0_PACKERENABLE_RDPENABLE_MASK      (0x2U)
#define SYSCTL0_PACKERENABLE_RDPENABLE_SHIFT     (1U)
/*! RDPENABLE - Writer Packer Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_PACKERENABLE_RDPENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PACKERENABLE_RDPENABLE_SHIFT)) & SYSCTL0_PACKERENABLE_RDPENABLE_MASK)
#define SYSCTL0_PACKERENABLE_CPRENABLE_MASK      (0x4U)
#define SYSCTL0_PACKERENABLE_CPRENABLE_SHIFT     (2U)
/*! CPRENABLE - Writer Packer Enable
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_PACKERENABLE_CPRENABLE(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PACKERENABLE_CPRENABLE_SHIFT)) & SYSCTL0_PACKERENABLE_CPRENABLE_MASK)
/*! @} */

/*! @name AHBBRIDGEBUFFER - AHB Buffer */
/*! @{ */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_MASK      (0x1U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_SHIFT     (0U)
/*! SLAVE0 - SLAVE0 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE0_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_MASK      (0x2U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_SHIFT     (1U)
/*! SLAVE1 - SLAVE1 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE1_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_MASK      (0x4U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_SHIFT     (2U)
/*! SLAVE2 - SLAVE2 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE2(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE2_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_MASK      (0x8U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_SHIFT     (3U)
/*! SLAVE3 - SLAVE3 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE3(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE3_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_MASK      (0x10U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_SHIFT     (4U)
/*! SLAVE4 - SLAVE4 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE4(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE4_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_MASK      (0x20U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_SHIFT     (5U)
/*! SLAVE5 - SLAVE5 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE5(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE5_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_MASK      (0x40U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_SHIFT     (6U)
/*! SLAVE6 - SLAVE6 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE6(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE6_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_MASK      (0x80U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_SHIFT     (7U)
/*! SLAVE7 - SLAVE7 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE7(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE7_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_MASK      (0x100U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_SHIFT     (8U)
/*! SLAVE8 - SLAVE8 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE8(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE8_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_MASK      (0x200U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_SHIFT     (9U)
/*! SLAVE9 - SLAVE9 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE9(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE9_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_MASK     (0x400U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_SHIFT    (10U)
/*! SLAVE10 - SLAVE10 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE10(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE10_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_MASK     (0x800U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_SHIFT    (11U)
/*! SLAVE11 - SLAVE11 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE11(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE11_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_MASK     (0x1000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_SHIFT    (12U)
/*! SLAVE12 - SLAVE12 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE12(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE12_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_MASK     (0x2000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_SHIFT    (13U)
/*! SLAVE13 - SLAVE13 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE13(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE13_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_MASK     (0x4000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_SHIFT    (14U)
/*! SLAVE14 - SLAVE14 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE14(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE14_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_MASK     (0x8000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_SHIFT    (15U)
/*! SLAVE15 - SLAVE15 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE15(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE15_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_MASK     (0x10000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_SHIFT    (16U)
/*! SLAVE16 - SLAVE16 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE16(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE16_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_MASK     (0x20000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_SHIFT    (17U)
/*! SLAVE17 - SLAVE17 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE17(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE17_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_MASK     (0x40000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_SHIFT    (18U)
/*! SLAVE18 - SLAVE18 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE18(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE18_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_MASK     (0x80000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_SHIFT    (19U)
/*! SLAVE19 - SLAVE19 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE19(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE19_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_MASK     (0x100000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_SHIFT    (20U)
/*! SLAVE20 - SLAVE20 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE20(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE20_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_MASK     (0x200000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_SHIFT    (21U)
/*! SLAVE21 - SLAVE21 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE21(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE21_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_MASK     (0x400000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_SHIFT    (22U)
/*! SLAVE22 - SLAVE22 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE22(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE22_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_MASK     (0x800000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_SHIFT    (23U)
/*! SLAVE23 - SLAVE23 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE23(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE23_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_MASK     (0x1000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_SHIFT    (24U)
/*! SLAVE24 - SLAVE24 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE24(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE24_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_MASK     (0x2000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_SHIFT    (25U)
/*! SLAVE25 - SLAVE25 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE25(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE25_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_MASK     (0x4000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_SHIFT    (26U)
/*! SLAVE26 - SLAVE26 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE26(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE26_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_MASK     (0x8000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_SHIFT    (27U)
/*! SLAVE27 - SLAVE27 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE27(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE27_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_MASK     (0x10000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_SHIFT    (28U)
/*! SLAVE28 - SLAVE28 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE28(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE28_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_MASK     (0x20000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_SHIFT    (29U)
/*! SLAVE29 - SLAVE29 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE29(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE29_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_MASK     (0x40000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_SHIFT    (30U)
/*! SLAVE30 - SLAVE30 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE30(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE30_MASK)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_MASK     (0x80000000U)
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_SHIFT    (31U)
/*! SLAVE31 - SLAVE31 buffering
 *  0b0..No Buffering
 *  0b1..Buffering
 */
#define SYSCTL0_AHBBRIDGEBUFFER_SLAVE31(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_SHIFT)) & SYSCTL0_AHBBRIDGEBUFFER_SLAVE31_MASK)
/*! @} */

/* The count of SYSCTL0_AHBBRIDGEBUFFER */
#define SYSCTL0_AHBBRIDGEBUFFER_COUNT            (2U)

/*! @name BOOTROM_LCKOUT - BOOT ROM lockout */
/*! @{ */
#define SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_MASK (0x1FFFFU)
#define SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_SHIFT (0U)
/*! READ_LCKOUT_SPACE - Read Lockout
 */
#define SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_SHIFT)) & SYSCTL0_BOOTROM_LCKOUT_READ_LCKOUT_SPACE_MASK)
#define SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_MASK   (0xC0000000U)
#define SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_SHIFT  (30U)
/*! WRITE_LOCK - Self Write Disable
 *  0b00..Write disable
 *  0b01..Write disable
 *  0b11..Write disable
 *  0b10..Write enable
 */
#define SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_SHIFT)) & SYSCTL0_BOOTROM_LCKOUT_WRITE_LOCK_MASK)
/*! @} */

/*! @name M33NMISRCSEL - M33 NMI source selection */
/*! @{ */
#define SYSCTL0_M33NMISRCSEL_NMISRCSEL_MASK      (0x7FU)
#define SYSCTL0_M33NMISRCSEL_NMISRCSEL_SHIFT     (0U)
/*! NMISRCSEL - Selects one of the M33 interrupt sources as the NMI source interrupt.
 */
#define SYSCTL0_M33NMISRCSEL_NMISRCSEL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_M33NMISRCSEL_NMISRCSEL_SHIFT)) & SYSCTL0_M33NMISRCSEL_NMISRCSEL_MASK)
#define SYSCTL0_M33NMISRCSEL_NMI_Enable_MASK     (0x80000000U)
#define SYSCTL0_M33NMISRCSEL_NMI_Enable_SHIFT    (31U)
/*! NMI_Enable
 *  0b0..Disable NMI interrupt
 *  0b1..Enable NMI interrupt
 */
#define SYSCTL0_M33NMISRCSEL_NMI_Enable(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_M33NMISRCSEL_NMI_Enable_SHIFT)) & SYSCTL0_M33NMISRCSEL_NMI_Enable_MASK)
/*! @} */

/*! @name SYSTEM_STICK_CALIB - System secure tick calibration */
/*! @{ */
#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_MASK (0x7FFFFFFU)
#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_SHIFT (0U)
/*! SYSTEM_STICK_CALIB - M33 secure tick calibration
 */
#define SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_SHIFT)) & SYSCTL0_SYSTEM_STICK_CALIB_SYSTEM_STICK_CALIB_MASK)
/*! @} */

/*! @name SYSTEM_NSTICK_CALIB - System non-secure tick calibration */
/*! @{ */
#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_MASK (0x7FFFFFFU)
#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_SHIFT (0U)
/*! SYSTEM_NSTICK_CALIB - M33 non secure tick calibration
 */
#define SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_SHIFT)) & SYSCTL0_SYSTEM_NSTICK_CALIB_SYSTEM_NSTICK_CALIB_MASK)
/*! @} */

/*! @name CONFIG_LCKOUT - System Configuration Lock-Out */
/*! @{ */
#define SYSCTL0_CONFIG_LCKOUT_LCKOUT_MASK        (0x1U)
#define SYSCTL0_CONFIG_LCKOUT_LCKOUT_SHIFT       (0U)
/*! LCKOUT - Configuration Lock-Out
 *  0b0..Enable Write to Configuration Registers
 *  0b1..Disable Write to Configuration Registers
 */
#define SYSCTL0_CONFIG_LCKOUT_LCKOUT(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CONFIG_LCKOUT_LCKOUT_SHIFT)) & SYSCTL0_CONFIG_LCKOUT_LCKOUT_MASK)
/*! @} */

/*! @name SRAMCFGENABLE0 - System SRAM Configuration Enable */
/*! @{ */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF0_MASK     (0x1U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF0_SHIFT    (0U)
/*! SRAM_IF0 - SRAM_IF0 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF0_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF0_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF1_MASK     (0x2U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF1_SHIFT    (1U)
/*! SRAM_IF1 - SRAM_IF1 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF1_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF1_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF2_MASK     (0x4U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF2_SHIFT    (2U)
/*! SRAM_IF2 - SRAM_IF2 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF2_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF2_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF3_MASK     (0x8U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF3_SHIFT    (3U)
/*! SRAM_IF3 - SRAM_IF3 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF3(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF3_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF3_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF4_MASK     (0x10U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF4_SHIFT    (4U)
/*! SRAM_IF4 - SRAM_IF4 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF4(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF4_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF4_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF5_MASK     (0x20U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF5_SHIFT    (5U)
/*! SRAM_IF5 - SRAM_IF5 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF5(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF5_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF5_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF6_MASK     (0x40U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF6_SHIFT    (6U)
/*! SRAM_IF6 - SRAM_IF6 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF6(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF6_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF6_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF7_MASK     (0x80U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF7_SHIFT    (7U)
/*! SRAM_IF7 - SRAM_IF7 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF7(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF7_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF7_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF8_MASK     (0x100U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF8_SHIFT    (8U)
/*! SRAM_IF8 - SRAM_IF8 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF8(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF8_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF8_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF9_MASK     (0x200U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF9_SHIFT    (9U)
/*! SRAM_IF9 - SRAM_IF9 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF9(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF9_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF9_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF10_MASK    (0x400U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF10_SHIFT   (10U)
/*! SRAM_IF10 - SRAM_IF10 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF10(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF10_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF10_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF11_MASK    (0x800U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF11_SHIFT   (11U)
/*! SRAM_IF11 - SRAM_IF11 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF11(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF11_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF11_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF12_MASK    (0x1000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF12_SHIFT   (12U)
/*! SRAM_IF12 - SRAM_IF12 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF12(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF12_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF12_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF13_MASK    (0x2000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF13_SHIFT   (13U)
/*! SRAM_IF13 - SRAM_IF13 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF13(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF13_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF13_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF14_MASK    (0x4000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF14_SHIFT   (14U)
/*! SRAM_IF14 - SRAM_IF14 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF14(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF14_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF14_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF15_MASK    (0x8000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF15_SHIFT   (15U)
/*! SRAM_IF15 - SRAM_IF15 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF15(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF15_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF15_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF16_MASK    (0x10000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF16_SHIFT   (16U)
/*! SRAM_IF16 - SRAM_IF16 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF16(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF16_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF16_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF17_MASK    (0x20000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF17_SHIFT   (17U)
/*! SRAM_IF17 - SRAM_IF17 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF17(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF17_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF17_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF18_MASK    (0x40000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF18_SHIFT   (18U)
/*! SRAM_IF18 - SRAM_IF18 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF18(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF18_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF18_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF19_MASK    (0x80000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF19_SHIFT   (19U)
/*! SRAM_IF19 - SRAM_IF19 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF19(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF19_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF19_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF20_MASK    (0x100000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF20_SHIFT   (20U)
/*! SRAM_IF20 - SRAM_IF20 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF20(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF20_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF20_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF21_MASK    (0x200000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF21_SHIFT   (21U)
/*! SRAM_IF21 - SRAM_IF21 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF21(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF21_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF21_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF22_MASK    (0x400000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF22_SHIFT   (22U)
/*! SRAM_IF22 - SRAM_IF22 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF22(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF22_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF22_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF23_MASK    (0x800000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF23_SHIFT   (23U)
/*! SRAM_IF23 - SRAM_IF23 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF23(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF23_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF23_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF24_MASK    (0x1000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF24_SHIFT   (24U)
/*! SRAM_IF24 - SRAM_IF24 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF24(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF24_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF24_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF25_MASK    (0x2000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF25_SHIFT   (25U)
/*! SRAM_IF25 - SRAM_IF25 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF25(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF25_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF25_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF26_MASK    (0x4000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF26_SHIFT   (26U)
/*! SRAM_IF26 - SRAM_IF26 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF26(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF26_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF26_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF27_MASK    (0x8000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF27_SHIFT   (27U)
/*! SRAM_IF27 - SRAM_IF27 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF27(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF27_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF27_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF28_MASK    (0x10000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF28_SHIFT   (28U)
/*! SRAM_IF28 - SRAM_IF28 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF28(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF28_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF28_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF29_MASK    (0x20000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF29_SHIFT   (29U)
/*! SRAM_IF29 - SRAM_IF29 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF29(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF29_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF29_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF30_MASK    (0x40000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF30_SHIFT   (30U)
/*! SRAM_IF30 - SRAM_IF30 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF30(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF30_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF30_MASK)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF31_MASK    (0x80000000U)
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF31_SHIFT   (31U)
/*! SRAM_IF31 - SRAM_IF31 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE0_SRAM_IF31(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE0_SRAM_IF31_SHIFT)) & SYSCTL0_SRAMCFGENABLE0_SRAM_IF31_MASK)
/*! @} */

/*! @name SRAMCFGENABLE1 - System SRAM Configuration Enable */
/*! @{ */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF0_MASK     (0x1U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF0_SHIFT    (0U)
/*! SRAM_IF0 - SRAM_IF0 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF0_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF0_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF1_MASK     (0x2U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF1_SHIFT    (1U)
/*! SRAM_IF1 - SRAM_IF1 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF1_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF1_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF2_MASK     (0x4U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF2_SHIFT    (2U)
/*! SRAM_IF2 - SRAM_IF2 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF2_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF2_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF3_MASK     (0x8U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF3_SHIFT    (3U)
/*! SRAM_IF3 - SRAM_IF3 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF3(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF3_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF3_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF4_MASK     (0x10U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF4_SHIFT    (4U)
/*! SRAM_IF4 - SRAM_IF4 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF4(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF4_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF4_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF5_MASK     (0x20U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF5_SHIFT    (5U)
/*! SRAM_IF5 - SRAM_IF5 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF5(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF5_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF5_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF6_MASK     (0x40U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF6_SHIFT    (6U)
/*! SRAM_IF6 - SRAM_IF6 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF6(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF6_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF6_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF7_MASK     (0x80U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF7_SHIFT    (7U)
/*! SRAM_IF7 - SRAM_IF7 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF7(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF7_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF7_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF8_MASK     (0x100U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF8_SHIFT    (8U)
/*! SRAM_IF8 - SRAM_IF8 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF8(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF8_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF8_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF9_MASK     (0x200U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF9_SHIFT    (9U)
/*! SRAM_IF9 - SRAM_IF9 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF9(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF9_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF9_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF10_MASK    (0x400U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF10_SHIFT   (10U)
/*! SRAM_IF10 - SRAM_IF10 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF10(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF10_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF10_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF11_MASK    (0x800U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF11_SHIFT   (11U)
/*! SRAM_IF11 - SRAM_IF11 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF11(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF11_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF11_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF12_MASK    (0x1000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF12_SHIFT   (12U)
/*! SRAM_IF12 - SRAM_IF12 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF12(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF12_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF12_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF13_MASK    (0x2000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF13_SHIFT   (13U)
/*! SRAM_IF13 - SRAM_IF13 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF13(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF13_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF13_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF14_MASK    (0x4000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF14_SHIFT   (14U)
/*! SRAM_IF14 - SRAM_IF14 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF14(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF14_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF14_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF15_MASK    (0x8000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF15_SHIFT   (15U)
/*! SRAM_IF15 - SRAM_IF15 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF15(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF15_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF15_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF16_MASK    (0x10000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF16_SHIFT   (16U)
/*! SRAM_IF16 - SRAM_IF16 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF16(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF16_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF16_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF17_MASK    (0x20000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF17_SHIFT   (17U)
/*! SRAM_IF17 - SRAM_IF17 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF17(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF17_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF17_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF18_MASK    (0x40000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF18_SHIFT   (18U)
/*! SRAM_IF18 - SRAM_IF18 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF18(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF18_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF18_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF19_MASK    (0x80000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF19_SHIFT   (19U)
/*! SRAM_IF19 - SRAM_IF19 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF19(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF19_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF19_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF20_MASK    (0x100000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF20_SHIFT   (20U)
/*! SRAM_IF20 - SRAM_IF20 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF20(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF20_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF20_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF21_MASK    (0x200000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF21_SHIFT   (21U)
/*! SRAM_IF21 - SRAM_IF21 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF21(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF21_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF21_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF22_MASK    (0x400000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF22_SHIFT   (22U)
/*! SRAM_IF22 - SRAM_IF22 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF22(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF22_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF22_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF23_MASK    (0x800000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF23_SHIFT   (23U)
/*! SRAM_IF23 - SRAM_IF23 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF23(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF23_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF23_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF24_MASK    (0x1000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF24_SHIFT   (24U)
/*! SRAM_IF24 - SRAM_IF24 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF24(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF24_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF24_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF25_MASK    (0x2000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF25_SHIFT   (25U)
/*! SRAM_IF25 - SRAM_IF25 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF25(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF25_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF25_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF26_MASK    (0x4000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF26_SHIFT   (26U)
/*! SRAM_IF26 - SRAM_IF26 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF26(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF26_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF26_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF27_MASK    (0x8000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF27_SHIFT   (27U)
/*! SRAM_IF27 - SRAM_IF27 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF27(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF27_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF27_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF28_MASK    (0x10000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF28_SHIFT   (28U)
/*! SRAM_IF28 - SRAM_IF28 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF28(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF28_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF28_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF29_MASK    (0x20000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF29_SHIFT   (29U)
/*! SRAM_IF29 - SRAM_IF29 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF29(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF29_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF29_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF30_MASK    (0x40000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF30_SHIFT   (30U)
/*! SRAM_IF30 - SRAM_IF30 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF30(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF30_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF30_MASK)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF31_MASK    (0x80000000U)
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF31_SHIFT   (31U)
/*! SRAM_IF31 - SRAM_IF31 buffering
 *  0b0..Disable SRAM
 *  0b1..Enable SRAM
 */
#define SYSCTL0_SRAMCFGENABLE1_SRAM_IF31(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SRAMCFGENABLE1_SRAM_IF31_SHIFT)) & SYSCTL0_SRAMCFGENABLE1_SRAM_IF31_MASK)
/*! @} */

/*! @name SOFTPARTCFG - Software configuration */
/*! @{ */
#define SYSCTL0_SOFTPARTCFG_SECURITY_ENABLED_MASK (0xFU)
#define SYSCTL0_SOFTPARTCFG_SECURITY_ENABLED_SHIFT (0U)
/*! SECURITY_ENABLED - Security Enabled
 *  0b0000..Illegal. Part will be locked.
 *  0b0101..Security is disabled.
 *  0b1010..Security is enabled. (Reset value)
 *  0b1111..Illegal. Part will be locked.
 */
#define SYSCTL0_SOFTPARTCFG_SECURITY_ENABLED(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SOFTPARTCFG_SECURITY_ENABLED_SHIFT)) & SYSCTL0_SOFTPARTCFG_SECURITY_ENABLED_MASK)
#define SYSCTL0_SOFTPARTCFG_TRUSTZONE_ENABLED_MASK (0xF0U)
#define SYSCTL0_SOFTPARTCFG_TRUSTZONE_ENABLED_SHIFT (4U)
/*! TRUSTZONE_ENABLED - Security Enabled
 *  0b0000..Illegal. Part will be locked.
 *  0b0101..Security is disabled.
 *  0b1010..Security is enabled. (Reset value)
 *  0b1111..Illegal. Part will be locked.
 */
#define SYSCTL0_SOFTPARTCFG_TRUSTZONE_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SOFTPARTCFG_TRUSTZONE_ENABLED_SHIFT)) & SYSCTL0_SOFTPARTCFG_TRUSTZONE_ENABLED_MASK)
#define SYSCTL0_SOFTPARTCFG_CLOUSTON_MASK        (0xFFFFFF00U)
#define SYSCTL0_SOFTPARTCFG_CLOUSTON_SHIFT       (8U)
/*! CLOUSTON - 24-Bit R/W Field
 */
#define SYSCTL0_SOFTPARTCFG_CLOUSTON(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SOFTPARTCFG_CLOUSTON_SHIFT)) & SYSCTL0_SOFTPARTCFG_CLOUSTON_MASK)
/*! @} */

/*! @name PERICFGENABLE0 - PERICFG Enable 0 */
/*! @{ */
#define SYSCTL0_PERICFGENABLE0_DSP_MASK          (0x2U)
#define SYSCTL0_PERICFGENABLE0_DSP_SHIFT         (1U)
/*! DSP - DSP
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_DSP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_DSP_SHIFT)) & SYSCTL0_PERICFGENABLE0_DSP_MASK)
#define SYSCTL0_PERICFGENABLE0_AXI_SWITCH_MASK   (0x8U)
#define SYSCTL0_PERICFGENABLE0_AXI_SWITCH_SHIFT  (3U)
/*! AXI_SWITCH - AXI_SWITCH
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_AXI_SWITCH(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_AXI_SWITCH_SHIFT)) & SYSCTL0_PERICFGENABLE0_AXI_SWITCH_MASK)
#define SYSCTL0_PERICFGENABLE0_AXI_CONTROLLER_REGISTERS_MASK (0x10U)
#define SYSCTL0_PERICFGENABLE0_AXI_CONTROLLER_REGISTERS_SHIFT (4U)
/*! AXI_CONTROLLER_REGISTERS - AXI_CONTROLLER_REGISTERS
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_AXI_CONTROLLER_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_AXI_CONTROLLER_REGISTERS_SHIFT)) & SYSCTL0_PERICFGENABLE0_AXI_CONTROLLER_REGISTERS_MASK)
#define SYSCTL0_PERICFGENABLE0_POWERQUAD_MASK    (0x100U)
#define SYSCTL0_PERICFGENABLE0_POWERQUAD_SHIFT   (8U)
/*! POWERQUAD - POWERQUAD
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_POWERQUAD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_POWERQUAD_SHIFT)) & SYSCTL0_PERICFGENABLE0_POWERQUAD_MASK)
#define SYSCTL0_PERICFGENABLE0_CASPER_MASK       (0x200U)
#define SYSCTL0_PERICFGENABLE0_CASPER_SHIFT      (9U)
/*! CASPER - CASPER
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_CASPER(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_CASPER_SHIFT)) & SYSCTL0_PERICFGENABLE0_CASPER_MASK)
#define SYSCTL0_PERICFGENABLE0_HASHCRYPT_MASK    (0x400U)
#define SYSCTL0_PERICFGENABLE0_HASHCRYPT_SHIFT   (10U)
/*! HASHCRYPT - HASHCRYPT
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_HASHCRYPT(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_HASHCRYPT_SHIFT)) & SYSCTL0_PERICFGENABLE0_HASHCRYPT_MASK)
#define SYSCTL0_PERICFGENABLE0_PUF_MASK          (0x800U)
#define SYSCTL0_PERICFGENABLE0_PUF_SHIFT         (11U)
/*! PUF - PUF
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_PUF(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_PUF_SHIFT)) & SYSCTL0_PERICFGENABLE0_PUF_MASK)
#define SYSCTL0_PERICFGENABLE0_RNG_MASK          (0x1000U)
#define SYSCTL0_PERICFGENABLE0_RNG_SHIFT         (12U)
/*! RNG - RNG
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_RNG(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_RNG_SHIFT)) & SYSCTL0_PERICFGENABLE0_RNG_MASK)
#define SYSCTL0_PERICFGENABLE0_OTFAD_MASK        (0x8000U)
#define SYSCTL0_PERICFGENABLE0_OTFAD_SHIFT       (15U)
/*! OTFAD - OTFAD
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_OTFAD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_OTFAD_SHIFT)) & SYSCTL0_PERICFGENABLE0_OTFAD_MASK)
#define SYSCTL0_PERICFGENABLE0_FLEXSPI0_OTFAD_MASK (0x10000U)
#define SYSCTL0_PERICFGENABLE0_FLEXSPI0_OTFAD_SHIFT (16U)
/*! FLEXSPI0_OTFAD - FLEXSPI0_OTFAD
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_FLEXSPI0_OTFAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_FLEXSPI0_OTFAD_SHIFT)) & SYSCTL0_PERICFGENABLE0_FLEXSPI0_OTFAD_MASK)
#define SYSCTL0_PERICFGENABLE0_OTP_CONTROLLER_MASK (0x20000U)
#define SYSCTL0_PERICFGENABLE0_OTP_CONTROLLER_SHIFT (17U)
/*! OTP_CONTROLLER - OTP_CONTROLLER
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_OTP_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_OTP_CONTROLLER_SHIFT)) & SYSCTL0_PERICFGENABLE0_OTP_CONTROLLER_MASK)
#define SYSCTL0_PERICFGENABLE0_FLEXSPI1_MASK     (0x40000U)
#define SYSCTL0_PERICFGENABLE0_FLEXSPI1_SHIFT    (18U)
/*! FLEXSPI1 - FLEXSPI1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_FLEXSPI1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_FLEXSPI1_SHIFT)) & SYSCTL0_PERICFGENABLE0_FLEXSPI1_MASK)
#define SYSCTL0_PERICFGENABLE0_USBHS_PHY_MASK    (0x100000U)
#define SYSCTL0_PERICFGENABLE0_USBHS_PHY_SHIFT   (20U)
/*! USBHS_PHY - USBHS_PHY
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_USBHS_PHY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_USBHS_PHY_SHIFT)) & SYSCTL0_PERICFGENABLE0_USBHS_PHY_MASK)
#define SYSCTL0_PERICFGENABLE0_USBHS_DEVICE_MASK (0x200000U)
#define SYSCTL0_PERICFGENABLE0_USBHS_DEVICE_SHIFT (21U)
/*! USBHS_DEVICE - USBHS_DEVICE
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_USBHS_DEVICE(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_USBHS_DEVICE_SHIFT)) & SYSCTL0_PERICFGENABLE0_USBHS_DEVICE_MASK)
#define SYSCTL0_PERICFGENABLE0_USBHS_HOST_MASK   (0x400000U)
#define SYSCTL0_PERICFGENABLE0_USBHS_HOST_SHIFT  (22U)
/*! USBHS_HOST - USBHS_HOST
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_USBHS_HOST(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_USBHS_HOST_SHIFT)) & SYSCTL0_PERICFGENABLE0_USBHS_HOST_MASK)
#define SYSCTL0_PERICFGENABLE0_USBHS_SRAM_MASK   (0x800000U)
#define SYSCTL0_PERICFGENABLE0_USBHS_SRAM_SHIFT  (23U)
/*! USBHS_SRAM - USBHS_SRAM
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_USBHS_SRAM(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_USBHS_SRAM_SHIFT)) & SYSCTL0_PERICFGENABLE0_USBHS_SRAM_MASK)
#define SYSCTL0_PERICFGENABLE0_SCT_MASK          (0x1000000U)
#define SYSCTL0_PERICFGENABLE0_SCT_SHIFT         (24U)
/*! SCT - SCT
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_SCT(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_SCT_SHIFT)) & SYSCTL0_PERICFGENABLE0_SCT_MASK)
#define SYSCTL0_PERICFGENABLE0_GPU_MASK          (0x4000000U)
#define SYSCTL0_PERICFGENABLE0_GPU_SHIFT         (26U)
/*! GPU - GPU
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_GPU(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_GPU_SHIFT)) & SYSCTL0_PERICFGENABLE0_GPU_MASK)
#define SYSCTL0_PERICFGENABLE0_DISPLAY_CONTROLLER_MASK (0x8000000U)
#define SYSCTL0_PERICFGENABLE0_DISPLAY_CONTROLLER_SHIFT (27U)
/*! DISPLAY_CONTROLLER - DISPLAY CONTROLLER
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_DISPLAY_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_DISPLAY_CONTROLLER_SHIFT)) & SYSCTL0_PERICFGENABLE0_DISPLAY_CONTROLLER_MASK)
#define SYSCTL0_PERICFGENABLE0_MIPI_DSI_CONTROLLER_MASK (0x10000000U)
#define SYSCTL0_PERICFGENABLE0_MIPI_DSI_CONTROLLER_SHIFT (28U)
/*! MIPI_DSI_CONTROLLER - MIPI DSI CONTROLLER
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_MIPI_DSI_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_MIPI_DSI_CONTROLLER_SHIFT)) & SYSCTL0_PERICFGENABLE0_MIPI_DSI_CONTROLLER_MASK)
#define SYSCTL0_PERICFGENABLE0_SMARTDMA_MASK     (0x40000000U)
#define SYSCTL0_PERICFGENABLE0_SMARTDMA_SHIFT    (30U)
/*! SMARTDMA - SMARTDMA
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE0_SMARTDMA(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE0_SMARTDMA_SHIFT)) & SYSCTL0_PERICFGENABLE0_SMARTDMA_MASK)
/*! @} */

/*! @name PERICFGENABLE1 - PERICFG Enable 1 */
/*! @{ */
#define SYSCTL0_PERICFGENABLE1_SDIO0_MASK        (0x4U)
#define SYSCTL0_PERICFGENABLE1_SDIO0_SHIFT       (2U)
/*! SDIO0 - SDIO0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE1_SDIO0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE1_SDIO0_SHIFT)) & SYSCTL0_PERICFGENABLE1_SDIO0_MASK)
#define SYSCTL0_PERICFGENABLE1_SDIO1_MASK        (0x8U)
#define SYSCTL0_PERICFGENABLE1_SDIO1_SHIFT       (3U)
/*! SDIO1 - SDIO1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE1_SDIO1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE1_SDIO1_SHIFT)) & SYSCTL0_PERICFGENABLE1_SDIO1_MASK)
#define SYSCTL0_PERICFGENABLE1_ACMP0_MASK        (0x8000U)
#define SYSCTL0_PERICFGENABLE1_ACMP0_SHIFT       (15U)
/*! ACMP0 - ACMP0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE1_ACMP0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE1_ACMP0_SHIFT)) & SYSCTL0_PERICFGENABLE1_ACMP0_MASK)
#define SYSCTL0_PERICFGENABLE1_ADC0_MASK         (0x10000U)
#define SYSCTL0_PERICFGENABLE1_ADC0_SHIFT        (16U)
/*! ADC0 - ADC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE1_ADC0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE1_ADC0_SHIFT)) & SYSCTL0_PERICFGENABLE1_ADC0_MASK)
/*! @} */

/*! @name PERICFGENABLE2 - PERICFG Enable 2 */
/*! @{ */
#define SYSCTL0_PERICFGENABLE2_UTICK0_MASK       (0x1U)
#define SYSCTL0_PERICFGENABLE2_UTICK0_SHIFT      (0U)
/*! UTICK0 - UTICK0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE2_UTICK0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE2_UTICK0_SHIFT)) & SYSCTL0_PERICFGENABLE2_UTICK0_MASK)
#define SYSCTL0_PERICFGENABLE2_WWDT0_MASK        (0x2U)
#define SYSCTL0_PERICFGENABLE2_WWDT0_SHIFT       (1U)
/*! WWDT0 - WWDT0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL0_PERICFGENABLE2_WWDT0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PERICFGENABLE2_WWDT0_SHIFT)) & SYSCTL0_PERICFGENABLE2_WWDT0_MASK)
/*! @} */

/*! @name PRODUCT_ID - Product ID */
/*! @{ */
#define SYSCTL0_PRODUCT_ID_PRODUCT_ID_MASK       (0xFFFFU)
#define SYSCTL0_PRODUCT_ID_PRODUCT_ID_SHIFT      (0U)
/*! PRODUCT_ID - PRODUCT ID
 */
#define SYSCTL0_PRODUCT_ID_PRODUCT_ID(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PRODUCT_ID_PRODUCT_ID_SHIFT)) & SYSCTL0_PRODUCT_ID_PRODUCT_ID_MASK)
/*! @} */

/*! @name SILICONREV_ID - Silicon Revision ID */
/*! @{ */
#define SYSCTL0_SILICONREV_ID_MINOR_MASK         (0xFU)
#define SYSCTL0_SILICONREV_ID_MINOR_SHIFT        (0U)
/*! MINOR - MINOR
 */
#define SYSCTL0_SILICONREV_ID_MINOR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SILICONREV_ID_MINOR_SHIFT)) & SYSCTL0_SILICONREV_ID_MINOR_MASK)
#define SYSCTL0_SILICONREV_ID_MAJOR_MASK         (0xF0000U)
#define SYSCTL0_SILICONREV_ID_MAJOR_SHIFT        (16U)
/*! MAJOR - MAJOR
 */
#define SYSCTL0_SILICONREV_ID_MAJOR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SILICONREV_ID_MAJOR_SHIFT)) & SYSCTL0_SILICONREV_ID_MAJOR_MASK)
/*! @} */

/*! @name JTAG_ID - JTAG ID */
/*! @{ */
#define SYSCTL0_JTAG_ID_FIXBIT_MASK              (0x1U)
#define SYSCTL0_JTAG_ID_FIXBIT_SHIFT             (0U)
/*! FIXBIT - JTAG ID fix bit.
 */
#define SYSCTL0_JTAG_ID_FIXBIT(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_FIXBIT_SHIFT)) & SYSCTL0_JTAG_ID_FIXBIT_MASK)
#define SYSCTL0_JTAG_ID_MANU_MASK                (0xFFEU)
#define SYSCTL0_JTAG_ID_MANU_SHIFT               (1U)
/*! MANU - JTAG ID Manufacturer
 */
#define SYSCTL0_JTAG_ID_MANU(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_MANU_SHIFT)) & SYSCTL0_JTAG_ID_MANU_MASK)
#define SYSCTL0_JTAG_ID_PRODUCT_ID_MASK          (0xFFFF000U)
#define SYSCTL0_JTAG_ID_PRODUCT_ID_SHIFT         (12U)
/*! PRODUCT_ID - JTAG ID Product ID as defined in the Product ID register
 */
#define SYSCTL0_JTAG_ID_PRODUCT_ID(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_PRODUCT_ID_SHIFT)) & SYSCTL0_JTAG_ID_PRODUCT_ID_MASK)
#define SYSCTL0_JTAG_ID_CHIPREV_MASK             (0xF0000000U)
#define SYSCTL0_JTAG_ID_CHIPREV_SHIFT            (28U)
/*! CHIPREV - JTAG ID 4-Bit Chip Silicon Revision
 */
#define SYSCTL0_JTAG_ID_CHIPREV(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_JTAG_ID_CHIPREV_SHIFT)) & SYSCTL0_JTAG_ID_CHIPREV_MASK)
/*! @} */

/*! @name NSGPIO_PSYNC - Non-secure GPIO PSYNC */
/*! @{ */
#define SYSCTL0_NSGPIO_PSYNC_PSYNC_MASK          (0x1U)
#define SYSCTL0_NSGPIO_PSYNC_PSYNC_SHIFT         (0U)
/*! PSYNC - Synchronization Stage Setting:
 */
#define SYSCTL0_NSGPIO_PSYNC_PSYNC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_NSGPIO_PSYNC_PSYNC_SHIFT)) & SYSCTL0_NSGPIO_PSYNC_PSYNC_MASK)
/*! @} */

/*! @name SGPIO_PSYNC - Secure GPIO PSYNC */
/*! @{ */
#define SYSCTL0_SGPIO_PSYNC_PSYNC_MASK           (0x1U)
#define SYSCTL0_SGPIO_PSYNC_PSYNC_SHIFT          (0U)
/*! PSYNC - Synchronization Stage Setting:
 *  0b0..2-Stage Sync
 *  0b1..1-Stage Sync
 */
#define SYSCTL0_SGPIO_PSYNC_PSYNC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SGPIO_PSYNC_PSYNC_SHIFT)) & SYSCTL0_SGPIO_PSYNC_PSYNC_MASK)
/*! @} */

/*! @name AUTOCLKGATEOVERRIDE0 - Auto clock gate override 0 */
/*! @{ */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_MASK (0x1U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_SHIFT (0U)
/*! AHB2APB0 - AHB2APB0
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB0_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_MASK (0x2U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_SHIFT (1U)
/*! AHB2APB1 - AHB2APB1
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_AHB2APB1_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_MASK (0x4U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_SHIFT (2U)
/*! CRC_ENGINE - CRC_ENGINE
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_CRC_ENGINE_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_MASK (0x8U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_SHIFT (3U)
/*! CASPER - CASPER
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_CASPER_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_MASK  (0x10U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_SHIFT (4U)
/*! DMAC0 - DMAC0
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC0_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_MASK  (0x20U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_SHIFT (5U)
/*! DMAC1 - DMAC1
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE0_DMAC1_MASK)
/*! @} */

/*! @name AUTOCLKGATEOVERRIDE1 - Auto clock gate override 1 */
/*! @{ */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_MASK (0x1U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_SHIFT (0U)
/*! SRAM0_IF - SRAM0_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM0_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_MASK (0x2U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_SHIFT (1U)
/*! SRAM1_IF - SRAM1_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM1_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_MASK (0x4U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_SHIFT (2U)
/*! SRAM2_IF - SRAM2_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM2_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_MASK (0x8U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_SHIFT (3U)
/*! SRAM3_IF - SRAM3_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM3_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_MASK (0x10U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_SHIFT (4U)
/*! SRAM4_IF - SRAM4_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM4_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_MASK (0x20U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_SHIFT (5U)
/*! SRAM5_IF - SRAM5_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM5_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_MASK (0x40U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_SHIFT (6U)
/*! SRAM6_IF - SRAM6_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM6_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_MASK (0x80U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_SHIFT (7U)
/*! SRAM7_IF - SRAM7_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM7_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_MASK (0x100U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_SHIFT (8U)
/*! SRAM8_IF - SRAM8_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM8_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_MASK (0x200U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_SHIFT (9U)
/*! SRAM9_IF - SRAM9_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM9_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_MASK (0x400U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_SHIFT (10U)
/*! SRAM10_IF - SRAM10_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM10_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_MASK (0x800U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_SHIFT (11U)
/*! SRAM11_IF - SRAM11_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM11_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_MASK (0x1000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_SHIFT (12U)
/*! SRAM12_IF - SRAM12_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM12_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_MASK (0x2000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_SHIFT (13U)
/*! SRAM13_IF - SRAM13_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM13_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_MASK (0x4000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_SHIFT (14U)
/*! SRAM14_IF - SRAM14_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM14_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_MASK (0x8000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_SHIFT (15U)
/*! SRAM15_IF - SRAM15_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM15_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_MASK (0x10000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_SHIFT (16U)
/*! SRAM16_IF - SRAM16_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM16_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_MASK (0x20000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_SHIFT (17U)
/*! SRAM17_IF - SRAM17_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM17_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_MASK (0x40000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_SHIFT (18U)
/*! SRAM18_IF - SRAM18_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM18_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_MASK (0x80000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_SHIFT (19U)
/*! SRAM19_IF - SRAM19_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM19_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_MASK (0x100000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_SHIFT (20U)
/*! SRAM20_IF - SRAM20_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM20_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_MASK (0x200000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_SHIFT (21U)
/*! SRAM21_IF - SRAM21_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM21_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_MASK (0x400000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_SHIFT (22U)
/*! SRAM22_IF - SRAM22_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM22_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_MASK (0x800000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_SHIFT (23U)
/*! SRAM23_IF - SRAM23_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM23_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_MASK (0x1000000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_SHIFT (24U)
/*! SRAM24_IF - SRAM24_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM24_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_MASK (0x2000000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_SHIFT (25U)
/*! SRAM25_IF - SRAM25_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM25_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_MASK (0x4000000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_SHIFT (26U)
/*! SRAM26_IF - SRAM26_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM26_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_MASK (0x8000000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_SHIFT (27U)
/*! SRAM27_IF - SRAM27_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM27_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_MASK (0x10000000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_SHIFT (28U)
/*! SRAM28_IF - SRAM28_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM28_IF_MASK)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_MASK (0x20000000U)
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_SHIFT (29U)
/*! SRAM29_IF - SRAM29_IF
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_SHIFT)) & SYSCTL0_AUTOCLKGATEOVERRIDE1_SRAM29_IF_MASK)
/*! @} */

/*! @name CLKGATEOVERRIDE0 - Clock gate override 0 */
/*! @{ */
#define SYSCTL0_CLKGATEOVERRIDE0_SDIO0_MASK      (0x1U)
#define SYSCTL0_CLKGATEOVERRIDE0_SDIO0_SHIFT     (0U)
/*! SDIO0 - SDIO0
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_SDIO0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_SDIO0_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_SDIO0_MASK)
#define SYSCTL0_CLKGATEOVERRIDE0_SDIO1_MASK      (0x2U)
#define SYSCTL0_CLKGATEOVERRIDE0_SDIO1_SHIFT     (1U)
/*! SDIO1 - SDIO1
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_SDIO1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_SDIO1_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_SDIO1_MASK)
#define SYSCTL0_CLKGATEOVERRIDE0_USBPHY_MASK     (0x4U)
#define SYSCTL0_CLKGATEOVERRIDE0_USBPHY_SHIFT    (2U)
/*! USBPHY - USBPHY
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_USBPHY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_USBPHY_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_USBPHY_MASK)
#define SYSCTL0_CLKGATEOVERRIDE0_ADC_MASK        (0x8U)
#define SYSCTL0_CLKGATEOVERRIDE0_ADC_SHIFT       (3U)
/*! ADC - ADC
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_ADC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_ADC_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_ADC_MASK)
#define SYSCTL0_CLKGATEOVERRIDE0_MU_MASK         (0x10U)
#define SYSCTL0_CLKGATEOVERRIDE0_MU_SHIFT        (4U)
/*! MU - MU
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_MU(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_MU_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_MU_MASK)
#define SYSCTL0_CLKGATEOVERRIDE0_ACMP_MASK       (0x20U)
#define SYSCTL0_CLKGATEOVERRIDE0_ACMP_SHIFT      (5U)
/*! ACMP - ACMP
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_ACMP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_ACMP_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_ACMP_MASK)
#define SYSCTL0_CLKGATEOVERRIDE0_PMC_MASK        (0x40U)
#define SYSCTL0_CLKGATEOVERRIDE0_PMC_SHIFT       (6U)
/*! PMC - PMC
 *  0b0..Enable clock gating
 *  0b1..Continuous Clocking
 */
#define SYSCTL0_CLKGATEOVERRIDE0_PMC(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLKGATEOVERRIDE0_PMC_SHIFT)) & SYSCTL0_CLKGATEOVERRIDE0_PMC_MASK)
/*! @} */

/*! @name AHB_SRAM_ACCESS_DISABLE - AHB SRAM access disable */
/*! @{ */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK (0x1U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT (0U)
/*! SRAM00_IF - Control AHB access to SRAM partition 0
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK (0x2U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT (1U)
/*! SRAM01_IF - Control AHB access to SRAM partition 1
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK (0x4U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT (2U)
/*! SRAM02_IF - Control AHB access to SRAM partition 2
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK (0x8U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT (3U)
/*! SRAM03_IF - Control AHB access to SRAM partition 3
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK (0x10U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT (4U)
/*! SRAM04_IF - Control AHB access to SRAM partition 4
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK (0x20U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT (5U)
/*! SRAM05_IF - Control AHB access to SRAM partition 5
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK (0x40U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT (6U)
/*! SRAM06_IF - Control AHB access to SRAM partition 6
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK (0x80U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT (7U)
/*! SRAM07_IF - Control AHB access to SRAM partition 7
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK (0x100U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT (8U)
/*! SRAM08_IF - Control AHB access to SRAM partition 8
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK (0x200U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT (9U)
/*! SRAM09_IF - Control AHB access to SRAM partition 9
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK (0x400U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT (10U)
/*! SRAM010_IF - Control AHB access to SRAM partition 10
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK (0x800U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT (11U)
/*! SRAM011_IF - Control AHB access to SRAM partition 11
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK (0x1000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT (12U)
/*! SRAM012_IF - Control AHB access to SRAM partition 12
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK (0x2000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT (13U)
/*! SRAM013_IF - Control AHB access to SRAM partition 13
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK (0x4000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT (14U)
/*! SRAM014_IF - Control AHB access to SRAM partition 14
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK (0x8000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT (15U)
/*! SRAM015_IF - Control AHB access to SRAM partition 15
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK (0x10000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT (16U)
/*! SRAM016_IF - Control AHB access to SRAM partition 16
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK (0x20000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT (17U)
/*! SRAM017_IF - Control AHB access to SRAM partition 17
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK (0x40000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT (18U)
/*! SRAM018_IF - Control AHB access to SRAM partition 18
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK (0x80000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT (19U)
/*! SRAM019_IF - Control AHB access to SRAM partition 19
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK (0x100000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT (20U)
/*! SRAM020_IF - Control AHB access to SRAM partition 20
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK (0x200000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT (21U)
/*! SRAM021_IF - Control AHB access to SRAM partition 21
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK (0x400000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT (22U)
/*! SRAM022_IF - Control AHB access to SRAM partition 22
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK (0x800000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT (23U)
/*! SRAM023_IF - Control AHB access to SRAM partition 23
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK (0x1000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT (24U)
/*! SRAM024_IF - Control AHB access to SRAM partition 24
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK (0x2000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT (25U)
/*! SRAM025_IF - Control AHB access to SRAM partition 25
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK (0x4000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT (26U)
/*! SRAM026_IF - Control AHB access to SRAM partition 26
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK (0x8000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT (27U)
/*! SRAM027_IF - Control AHB access to SRAM partition 27
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK (0x10000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT (28U)
/*! SRAM028_IF - Control AHB access to SRAM partition 28
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK (0x20000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT (29U)
/*! SRAM029_IF - Control AHB access to SRAM partition 29
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK (0x40000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT (30U)
/*! SRAM030_IF - Control AHB access to SRAM partition 30
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK (0x80000000U)
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT (31U)
/*! SRAM031_IF - Control AHB access to SRAM partition 31
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT)) & SYSCTL0_AHB_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK)
/*! @} */

/*! @name AXI_SRAM_ACCESS_DISABLE - AXI SRAM access disable */
/*! @{ */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK (0x1U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT (0U)
/*! SRAM00_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM00_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK (0x2U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT (1U)
/*! SRAM01_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM01_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK (0x4U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT (2U)
/*! SRAM02_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM02_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK (0x8U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT (3U)
/*! SRAM03_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM03_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK (0x10U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT (4U)
/*! SRAM04_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM04_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK (0x20U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT (5U)
/*! SRAM05_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM05_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK (0x40U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT (6U)
/*! SRAM06_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM06_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK (0x80U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT (7U)
/*! SRAM07_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM07_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK (0x100U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT (8U)
/*! SRAM08_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM08_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK (0x200U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT (9U)
/*! SRAM09_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM09_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK (0x400U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT (10U)
/*! SRAM010_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM010_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK (0x800U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT (11U)
/*! SRAM011_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM011_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK (0x1000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT (12U)
/*! SRAM012_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM012_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK (0x2000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT (13U)
/*! SRAM013_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM013_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK (0x4000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT (14U)
/*! SRAM014_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM014_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK (0x8000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT (15U)
/*! SRAM015_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM015_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK (0x10000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT (16U)
/*! SRAM016_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM016_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK (0x20000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT (17U)
/*! SRAM017_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM017_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK (0x40000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT (18U)
/*! SRAM018_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM018_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK (0x80000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT (19U)
/*! SRAM019_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM019_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK (0x100000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT (20U)
/*! SRAM020_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM020_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK (0x200000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT (21U)
/*! SRAM021_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM021_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK (0x400000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT (22U)
/*! SRAM022_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM022_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK (0x800000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT (23U)
/*! SRAM023_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM023_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK (0x1000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT (24U)
/*! SRAM024_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM024_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK (0x2000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT (25U)
/*! SRAM025_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM025_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK (0x4000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT (26U)
/*! SRAM026_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM026_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK (0x8000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT (27U)
/*! SRAM027_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM027_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK (0x10000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT (28U)
/*! SRAM028_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM028_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK (0x20000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT (29U)
/*! SRAM029_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM029_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK (0x40000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT (30U)
/*! SRAM030_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM030_IF_MASK)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK (0x80000000U)
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT (31U)
/*! SRAM031_IF - Control AXB access to SRAM partition
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_SHIFT)) & SYSCTL0_AXI_SRAM_ACCESS_DISABLE_SRAM031_IF_MASK)
/*! @} */

/*! @name DSP_SRAM_ACCESS_DISABLE - DSP SRAM access disable */
/*! @{ */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_MASK (0x1U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_SHIFT (0U)
/*! SRAM0_IF - SRAM0_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM0_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_MASK (0x2U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_SHIFT (1U)
/*! SRAM1_IF - SRAM1_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM1_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_MASK (0x4U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_SHIFT (2U)
/*! SRAM2_IF - SRAM2_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM2_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_MASK (0x8U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_SHIFT (3U)
/*! SRAM3_IF - SRAM3_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM3_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_MASK (0x10U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_SHIFT (4U)
/*! SRAM4_IF - SRAM4_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM4_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_MASK (0x20U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_SHIFT (5U)
/*! SRAM5_IF - SRAM5_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM5_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_MASK (0x40U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_SHIFT (6U)
/*! SRAM6_IF - SRAM6_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM6_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_MASK (0x80U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_SHIFT (7U)
/*! SRAM7_IF - SRAM7_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM7_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_MASK (0x100U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_SHIFT (8U)
/*! SRAM8_IF - SRAM8_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM8_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_MASK (0x200U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_SHIFT (9U)
/*! SRAM9_IF - SRAM9_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM9_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_MASK (0x400U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_SHIFT (10U)
/*! SRAM10_IF - SRAM10_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM10_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_MASK (0x800U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_SHIFT (11U)
/*! SRAM11_IF - SRAM11_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM11_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_MASK (0x1000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_SHIFT (12U)
/*! SRAM12_IF - SRAM12_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM12_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_MASK (0x2000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_SHIFT (13U)
/*! SRAM13_IF - SRAM13_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM13_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_MASK (0x4000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_SHIFT (14U)
/*! SRAM14_IF - SRAM14_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM14_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_MASK (0x8000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_SHIFT (15U)
/*! SRAM15_IF - SRAM15_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM15_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_MASK (0x10000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_SHIFT (16U)
/*! SRAM16_IF - SRAM16_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM16_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_MASK (0x20000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_SHIFT (17U)
/*! SRAM17_IF - SRAM17_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM17_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_MASK (0x40000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_SHIFT (18U)
/*! SRAM18_IF - SRAM18_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM18_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_MASK (0x80000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_SHIFT (19U)
/*! SRAM19_IF - SRAM19_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM19_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_MASK (0x100000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_SHIFT (20U)
/*! SRAM20_IF - SRAM20_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM20_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_MASK (0x200000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_SHIFT (21U)
/*! SRAM21_IF - SRAM21_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM21_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_MASK (0x400000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_SHIFT (22U)
/*! SRAM22_IF - SRAM22_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM22_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_MASK (0x800000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_SHIFT (23U)
/*! SRAM23_IF - SRAM23_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM23_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_MASK (0x1000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_SHIFT (24U)
/*! SRAM24_IF - SRAM24_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM24_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_MASK (0x2000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_SHIFT (25U)
/*! SRAM25_IF - SRAM25_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM25_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_MASK (0x4000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_SHIFT (26U)
/*! SRAM26_IF - SRAM26_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM26_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_MASK (0x8000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_SHIFT (27U)
/*! SRAM27_IF - SRAM27_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM27_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_MASK (0x10000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_SHIFT (28U)
/*! SRAM28_IF - SRAM28_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM28_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_MASK (0x20000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_SHIFT (29U)
/*! SRAM29_IF - SRAM29_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM29_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_MASK (0x40000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_SHIFT (30U)
/*! SRAM30_IF - SRAM30_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM30_IF_MASK)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_MASK (0x80000000U)
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_SHIFT (31U)
/*! SRAM31_IF - SRAM31_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_SHIFT)) & SYSCTL0_DSP_SRAM_ACCESS_DISABLE_SRAM31_IF_MASK)
/*! @} */

/*! @name AUTO_SRAM_DISABLE - AUTO SRAM disable */
/*! @{ */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM0_IF_MASK  (0x1U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM0_IF_SHIFT (0U)
/*! SRAM0_IF - SRAM0_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM0_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM0_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM0_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM1_IF_MASK  (0x2U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM1_IF_SHIFT (1U)
/*! SRAM1_IF - SRAM1_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM1_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM1_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM1_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM2_IF_MASK  (0x4U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM2_IF_SHIFT (2U)
/*! SRAM2_IF - SRAM2_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM2_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM2_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM2_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM3_IF_MASK  (0x8U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM3_IF_SHIFT (3U)
/*! SRAM3_IF - SRAM3_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM3_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM3_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM3_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM4_IF_MASK  (0x10U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM4_IF_SHIFT (4U)
/*! SRAM4_IF - SRAM4_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM4_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM4_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM4_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM5_IF_MASK  (0x20U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM5_IF_SHIFT (5U)
/*! SRAM5_IF - SRAM5_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM5_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM5_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM5_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM6_IF_MASK  (0x40U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM6_IF_SHIFT (6U)
/*! SRAM6_IF - SRAM6_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM6_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM6_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM6_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM7_IF_MASK  (0x80U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM7_IF_SHIFT (7U)
/*! SRAM7_IF - SRAM7_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM7_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM7_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM7_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM8_IF_MASK  (0x100U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM8_IF_SHIFT (8U)
/*! SRAM8_IF - SRAM8_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM8_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM8_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM8_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM9_IF_MASK  (0x200U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM9_IF_SHIFT (9U)
/*! SRAM9_IF - SRAM9_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM9_IF(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM9_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM9_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM10_IF_MASK (0x400U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM10_IF_SHIFT (10U)
/*! SRAM10_IF - SRAM10_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM10_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM10_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM10_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM11_IF_MASK (0x800U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM11_IF_SHIFT (11U)
/*! SRAM11_IF - SRAM11_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM11_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM11_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM11_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM12_IF_MASK (0x1000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM12_IF_SHIFT (12U)
/*! SRAM12_IF - SRAM12_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM12_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM12_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM12_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM13_IF_MASK (0x2000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM13_IF_SHIFT (13U)
/*! SRAM13_IF - SRAM13_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM13_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM13_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM13_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM14_IF_MASK (0x4000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM14_IF_SHIFT (14U)
/*! SRAM14_IF - SRAM14_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM14_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM14_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM14_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM15_IF_MASK (0x8000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM15_IF_SHIFT (15U)
/*! SRAM15_IF - SRAM15_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM15_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM15_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM15_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM16_IF_MASK (0x10000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM16_IF_SHIFT (16U)
/*! SRAM16_IF - SRAM16_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM16_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM16_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM16_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM17_IF_MASK (0x20000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM17_IF_SHIFT (17U)
/*! SRAM17_IF - SRAM17_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM17_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM17_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM17_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM18_IF_MASK (0x40000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM18_IF_SHIFT (18U)
/*! SRAM18_IF - SRAM18_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM18_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM18_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM18_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM19_IF_MASK (0x80000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM19_IF_SHIFT (19U)
/*! SRAM19_IF - SRAM19_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM19_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM19_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM19_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM20_IF_MASK (0x100000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM20_IF_SHIFT (20U)
/*! SRAM20_IF - SRAM20_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM20_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM20_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM20_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM21_IF_MASK (0x200000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM21_IF_SHIFT (21U)
/*! SRAM21_IF - SRAM21_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM21_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM21_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM21_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM22_IF_MASK (0x400000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM22_IF_SHIFT (22U)
/*! SRAM22_IF - SRAM22_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM22_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM22_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM22_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM23_IF_MASK (0x800000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM23_IF_SHIFT (23U)
/*! SRAM23_IF - SRAM23_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM23_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM23_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM23_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM24_IF_MASK (0x1000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM24_IF_SHIFT (24U)
/*! SRAM24_IF - SRAM24_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM24_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM24_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM24_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM25_IF_MASK (0x2000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM25_IF_SHIFT (25U)
/*! SRAM25_IF - SRAM25_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM25_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM25_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM25_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM26_IF_MASK (0x4000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM26_IF_SHIFT (26U)
/*! SRAM26_IF - SRAM26_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM26_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM26_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM26_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM27_IF_MASK (0x8000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM27_IF_SHIFT (27U)
/*! SRAM27_IF - SRAM27_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM27_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM27_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM27_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM28_IF_MASK (0x10000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM28_IF_SHIFT (28U)
/*! SRAM28_IF - SRAM28_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM28_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM28_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM28_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM29_IF_MASK (0x20000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM29_IF_SHIFT (29U)
/*! SRAM29_IF - SRAM29_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM29_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM29_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM29_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM30_IF_MASK (0x40000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM30_IF_SHIFT (30U)
/*! SRAM30_IF - SRAM30_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM30_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM30_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM30_IF_MASK)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM31_IF_MASK (0x80000000U)
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM31_IF_SHIFT (31U)
/*! SRAM31_IF - SRAM31_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_DISABLE_SRAM31_IF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_DISABLE_SRAM31_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_DISABLE_SRAM31_IF_MASK)
/*! @} */

/*! @name AUTO_SRAM_STDBY_DISABLE - AUTO SRAM Standby disable */
/*! @{ */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM0_IF_MASK (0x1U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM0_IF_SHIFT (0U)
/*! SRAM0_IF - SRAM0_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM0_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM0_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM0_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM1_IF_MASK (0x2U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM1_IF_SHIFT (1U)
/*! SRAM1_IF - SRAM1_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM1_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM1_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM1_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM2_IF_MASK (0x4U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM2_IF_SHIFT (2U)
/*! SRAM2_IF - SRAM2_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM2_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM2_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM2_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM3_IF_MASK (0x8U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM3_IF_SHIFT (3U)
/*! SRAM3_IF - SRAM3_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM3_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM3_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM3_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM4_IF_MASK (0x10U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM4_IF_SHIFT (4U)
/*! SRAM4_IF - SRAM4_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM4_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM4_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM4_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM5_IF_MASK (0x20U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM5_IF_SHIFT (5U)
/*! SRAM5_IF - SRAM5_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM5_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM5_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM5_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM6_IF_MASK (0x40U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM6_IF_SHIFT (6U)
/*! SRAM6_IF - SRAM6_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM6_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM6_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM6_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM7_IF_MASK (0x80U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM7_IF_SHIFT (7U)
/*! SRAM7_IF - SRAM7_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM7_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM7_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM7_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM8_IF_MASK (0x100U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM8_IF_SHIFT (8U)
/*! SRAM8_IF - SRAM8_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM8_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM8_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM8_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM9_IF_MASK (0x200U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM9_IF_SHIFT (9U)
/*! SRAM9_IF - SRAM9_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM9_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM9_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM9_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM10_IF_MASK (0x400U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM10_IF_SHIFT (10U)
/*! SRAM10_IF - SRAM10_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM10_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM10_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM10_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM11_IF_MASK (0x800U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM11_IF_SHIFT (11U)
/*! SRAM11_IF - SRAM11_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM11_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM11_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM11_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM12_IF_MASK (0x1000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM12_IF_SHIFT (12U)
/*! SRAM12_IF - SRAM12_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM12_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM12_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM12_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM13_IF_MASK (0x2000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM13_IF_SHIFT (13U)
/*! SRAM13_IF - SRAM13_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM13_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM13_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM13_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM14_IF_MASK (0x4000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM14_IF_SHIFT (14U)
/*! SRAM14_IF - SRAM14_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM14_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM14_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM14_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM15_IF_MASK (0x8000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM15_IF_SHIFT (15U)
/*! SRAM15_IF - SRAM15_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM15_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM15_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM15_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM16_IF_MASK (0x10000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM16_IF_SHIFT (16U)
/*! SRAM16_IF - SRAM16_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM16_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM16_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM16_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM17_IF_MASK (0x20000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM17_IF_SHIFT (17U)
/*! SRAM17_IF - SRAM17_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM17_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM17_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM17_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM18_IF_MASK (0x40000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM18_IF_SHIFT (18U)
/*! SRAM18_IF - SRAM18_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM18_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM18_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM18_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM19_IF_MASK (0x80000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM19_IF_SHIFT (19U)
/*! SRAM19_IF - SRAM19_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM19_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM19_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM19_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM20_IF_MASK (0x100000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM20_IF_SHIFT (20U)
/*! SRAM20_IF - SRAM20_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM20_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM20_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM20_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM21_IF_MASK (0x200000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM21_IF_SHIFT (21U)
/*! SRAM21_IF - SRAM21_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM21_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM21_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM21_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM22_IF_MASK (0x400000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM22_IF_SHIFT (22U)
/*! SRAM22_IF - SRAM22_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM22_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM22_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM22_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM23_IF_MASK (0x800000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM23_IF_SHIFT (23U)
/*! SRAM23_IF - SRAM23_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM23_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM23_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM23_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM24_IF_MASK (0x1000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM24_IF_SHIFT (24U)
/*! SRAM24_IF - SRAM24_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM24_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM24_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM24_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM25_IF_MASK (0x2000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM25_IF_SHIFT (25U)
/*! SRAM25_IF - SRAM25_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM25_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM25_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM25_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM26_IF_MASK (0x4000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM26_IF_SHIFT (26U)
/*! SRAM26_IF - SRAM26_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM26_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM26_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM26_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM27_IF_MASK (0x8000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM27_IF_SHIFT (27U)
/*! SRAM27_IF - SRAM27_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM27_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM27_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM27_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM28_IF_MASK (0x10000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM28_IF_SHIFT (28U)
/*! SRAM28_IF - SRAM28_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM28_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM28_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM28_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM29_IF_MASK (0x20000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM29_IF_SHIFT (29U)
/*! SRAM29_IF - SRAM29_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM29_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM29_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM29_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM30_IF_MASK (0x40000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM30_IF_SHIFT (30U)
/*! SRAM30_IF - SRAM30_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM30_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM30_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM30_IF_MASK)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM31_IF_MASK (0x80000000U)
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM31_IF_SHIFT (31U)
/*! SRAM31_IF - SRAM31_IF
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM31_IF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM31_IF_SHIFT)) & SYSCTL0_AUTO_SRAM_STDBY_DISABLE_SRAM31_IF_MASK)
/*! @} */

/*! @name PQ_MEM_CTRL - Power-Quad Memory Control */
/*! @{ */
#define SYSCTL0_PQ_MEM_CTRL_SRAM_IG_MASK         (0x1U)
#define SYSCTL0_PQ_MEM_CTRL_SRAM_IG_SHIFT        (0U)
/*! SRAM_IG - SRAM IG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_PQ_MEM_CTRL_SRAM_IG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PQ_MEM_CTRL_SRAM_IG_SHIFT)) & SYSCTL0_PQ_MEM_CTRL_SRAM_IG_MASK)
#define SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_MASK      (0x2U)
#define SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_SHIFT     (1U)
/*! SRAM_STDBY - SRAM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_SHIFT)) & SYSCTL0_PQ_MEM_CTRL_SRAM_STDBY_MASK)
/*! @} */

/*! @name FLEXSPI0_MEM_CTRL - FlexSPI0 Memory Control */
/*! @{ */
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_MASK   (0x1U)
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_SHIFT  (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_MASK   (0x2U)
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_SHIFT  (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_MASK (0x4U)
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_SHIFT (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_FLEXSPI0_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name USBHS_MEM_CTRL - USBHS Memory Control */
/*! @{ */
#define SYSCTL0_USBHS_MEM_CTRL_MEM_IG_MASK       (0x1U)
#define SYSCTL0_USBHS_MEM_CTRL_MEM_IG_SHIFT      (0U)
/*! MEM_IG - MEM IG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USBHS_MEM_CTRL_MEM_IG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBHS_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_USBHS_MEM_CTRL_MEM_IG_MASK)
#define SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_MASK    (0x2U)
#define SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_SHIFT   (1U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_USBHS_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name USDHC0_MEM_CTRL - USDHC0 Memory Control */
/*! @{ */
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_MASK     (0x1U)
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_SHIFT    (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_USDHC0_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_MASK     (0x2U)
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_SHIFT    (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_USDHC0_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_MASK   (0x4U)
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_SHIFT  (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_USDHC0_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name USDHC1_MEM_CTRL - USDHC1 Memory Control */
/*! @{ */
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_MASK     (0x1U)
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_SHIFT    (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_USDHC1_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_MASK     (0x2U)
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_SHIFT    (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_USDHC1_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_MASK   (0x4U)
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_SHIFT  (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_USDHC1_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name CASPER_MEM_CTRL - CASPER Memory Control */
/*! @{ */
#define SYSCTL0_CASPER_MEM_CTRL_MEM_IG_MASK      (0x1U)
#define SYSCTL0_CASPER_MEM_CTRL_MEM_IG_SHIFT     (0U)
/*! MEM_IG - Auto IG Control Disable
 *  0b0..IG is controlled by auto clock gating signal.
 *  0b1..IG Is forced low.
 */
#define SYSCTL0_CASPER_MEM_CTRL_MEM_IG(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CASPER_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_CASPER_MEM_CTRL_MEM_IG_MASK)
#define SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_MASK   (0x2U)
#define SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_SHIFT  (1U)
/*! MEM_STDBY - Auto STDBY Control Disable
 *  0b0..STDBY is controlled by auto clock gating signal.
 *  0b1..STDBY Is forced low.
 */
#define SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_CASPER_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name ROM_MEM_CTRL - ROM Memory Control */
/*! @{ */
#define SYSCTL0_ROM_MEM_CTRL_MEM_IG_MASK         (0x1U)
#define SYSCTL0_ROM_MEM_CTRL_MEM_IG_SHIFT        (0U)
/*! MEM_IG - MEM IG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_ROM_MEM_CTRL_MEM_IG(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_ROM_MEM_CTRL_MEM_IG_MASK)
#define SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_MASK      (0x2U)
#define SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_SHIFT     (1U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_ROM_MEM_CTRL_MEM_STDBY(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_ROM_MEM_CTRL_MEM_STDBY_MASK)
#define SYSCTL0_ROM_MEM_CTRL_MEM_LS_MASK         (0x4U)
#define SYSCTL0_ROM_MEM_CTRL_MEM_LS_SHIFT        (2U)
/*! MEM_LS - MEM LS
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_ROM_MEM_CTRL_MEM_LS(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_ROM_MEM_CTRL_MEM_LS_SHIFT)) & SYSCTL0_ROM_MEM_CTRL_MEM_LS_MASK)
/*! @} */

/*! @name FLEXSPI1_MEM_CTRL - FlexSPI1 Memory Control */
/*! @{ */
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_MASK   (0x1U)
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_SHIFT  (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_MASK   (0x2U)
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_SHIFT  (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_MASK (0x4U)
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_SHIFT (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_FLEXSPI1_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name GPU_MEM_CTRL - GPU Memory Control */
/*! @{ */
#define SYSCTL0_GPU_MEM_CTRL_MEM_RIG_MASK        (0x1U)
#define SYSCTL0_GPU_MEM_CTRL_MEM_RIG_SHIFT       (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_GPU_MEM_CTRL_MEM_RIG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_GPU_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_GPU_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_GPU_MEM_CTRL_MEM_WIG_MASK        (0x2U)
#define SYSCTL0_GPU_MEM_CTRL_MEM_WIG_SHIFT       (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_GPU_MEM_CTRL_MEM_WIG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_GPU_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_GPU_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_MASK      (0x4U)
#define SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_SHIFT     (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_GPU_MEM_CTRL_MEM_STDBY(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_GPU_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name MIPI_MEM_CTRL - MIPI Memory Control */
/*! @{ */
#define SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_MASK       (0x1U)
#define SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_SHIFT      (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_MIPI_MEM_CTRL_MEM_RIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_MIPI_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_MASK       (0x2U)
#define SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_SHIFT      (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_MIPI_MEM_CTRL_MEM_WIG(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_MIPI_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_MASK     (0x4U)
#define SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_SHIFT    (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_MIPI_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name DCN_MEM_CTRL - LCDIF Memory Control */
/*! @{ */
#define SYSCTL0_DCN_MEM_CTRL_MEM_RIG_MASK        (0x1U)
#define SYSCTL0_DCN_MEM_CTRL_MEM_RIG_SHIFT       (0U)
/*! MEM_RIG - MEM RIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DCN_MEM_CTRL_MEM_RIG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DCN_MEM_CTRL_MEM_RIG_SHIFT)) & SYSCTL0_DCN_MEM_CTRL_MEM_RIG_MASK)
#define SYSCTL0_DCN_MEM_CTRL_MEM_WIG_MASK        (0x2U)
#define SYSCTL0_DCN_MEM_CTRL_MEM_WIG_SHIFT       (1U)
/*! MEM_WIG - MEM WIG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DCN_MEM_CTRL_MEM_WIG(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DCN_MEM_CTRL_MEM_WIG_SHIFT)) & SYSCTL0_DCN_MEM_CTRL_MEM_WIG_MASK)
#define SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_MASK      (0x4U)
#define SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_SHIFT     (2U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_DCN_MEM_CTRL_MEM_STDBY(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_DCN_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name SMARTDMA_MEM_CTRL - SMARTDMA Memory Control */
/*! @{ */
#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_MASK    (0x1U)
#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_SHIFT   (0U)
/*! MEM_IG - MEM IG
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_SHIFT)) & SYSCTL0_SMARTDMA_MEM_CTRL_MEM_IG_MASK)
#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_MASK (0x2U)
#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_SHIFT (1U)
/*! MEM_STDBY - MEM STDBY
 *  0b0..Enable
 *  0b1..Disable
 */
#define SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_SHIFT)) & SYSCTL0_SMARTDMA_MEM_CTRL_MEM_STDBY_MASK)
/*! @} */

/*! @name OQSPI_BOOTROM_SCRATCHN - OQSPI BOOTROM Scratch */
/*! @{ */
#define SYSCTL0_OQSPI_BOOTROM_SCRATCHN_SCRATCHN_MASK (0xFFFFFFFFU)
#define SYSCTL0_OQSPI_BOOTROM_SCRATCHN_SCRATCHN_SHIFT (0U)
/*! SCRATCHN - SCRATCH
 */
#define SYSCTL0_OQSPI_BOOTROM_SCRATCHN_SCRATCHN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_OQSPI_BOOTROM_SCRATCHN_SCRATCHN_SHIFT)) & SYSCTL0_OQSPI_BOOTROM_SCRATCHN_SCRATCHN_MASK)
/*! @} */

/*! @name CLOUSTON_PORRST_DR0 - CLOUSTON PORRST DR0 */
/*! @{ */
#define SYSCTL0_CLOUSTON_PORRST_DR0_CLOUSTON_PORRST_DR0_MASK (0xFFFFFFFFU)
#define SYSCTL0_CLOUSTON_PORRST_DR0_CLOUSTON_PORRST_DR0_SHIFT (0U)
/*! CLOUSTON_PORRST_DR0 - CLOUSTON PORRST DR0
 */
#define SYSCTL0_CLOUSTON_PORRST_DR0_CLOUSTON_PORRST_DR0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLOUSTON_PORRST_DR0_CLOUSTON_PORRST_DR0_SHIFT)) & SYSCTL0_CLOUSTON_PORRST_DR0_CLOUSTON_PORRST_DR0_MASK)
/*! @} */

/*! @name CLOUSTON_PORRST_DR1 - CLOUSTON PORRST DR1 */
/*! @{ */
#define SYSCTL0_CLOUSTON_PORRST_DR1_CLOUSTON_PORRST_DR1_MASK (0xFFFFFFFFU)
#define SYSCTL0_CLOUSTON_PORRST_DR1_CLOUSTON_PORRST_DR1_SHIFT (0U)
/*! CLOUSTON_PORRST_DR1 - CLOUSTON PORRST DR1
 */
#define SYSCTL0_CLOUSTON_PORRST_DR1_CLOUSTON_PORRST_DR1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLOUSTON_PORRST_DR1_CLOUSTON_PORRST_DR1_SHIFT)) & SYSCTL0_CLOUSTON_PORRST_DR1_CLOUSTON_PORRST_DR1_MASK)
/*! @} */

/*! @name CLOUSTON_ALLRST_DR0 - CLOUSTON ALLRST DR0 */
/*! @{ */
#define SYSCTL0_CLOUSTON_ALLRST_DR0_CLOUSTON_ALLRST_DR0_MASK (0xFFFFFFFFU)
#define SYSCTL0_CLOUSTON_ALLRST_DR0_CLOUSTON_ALLRST_DR0_SHIFT (0U)
/*! CLOUSTON_ALLRST_DR0 - CLOUSTON_ALLRST_DR0
 */
#define SYSCTL0_CLOUSTON_ALLRST_DR0_CLOUSTON_ALLRST_DR0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLOUSTON_ALLRST_DR0_CLOUSTON_ALLRST_DR0_SHIFT)) & SYSCTL0_CLOUSTON_ALLRST_DR0_CLOUSTON_ALLRST_DR0_MASK)
/*! @} */

/*! @name CLOUSTON_ALLRST_DR1 - CLOUSTON ALLRST DR1 */
/*! @{ */
#define SYSCTL0_CLOUSTON_ALLRST_DR1_CLOUSTON_ALLRST_DR1_MASK (0xFFFFFFFFU)
#define SYSCTL0_CLOUSTON_ALLRST_DR1_CLOUSTON_ALLRST_DR1_SHIFT (0U)
/*! CLOUSTON_ALLRST_DR1 - CLOUSTON_ALLRST_DR1
 */
#define SYSCTL0_CLOUSTON_ALLRST_DR1_CLOUSTON_ALLRST_DR1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CLOUSTON_ALLRST_DR1_CLOUSTON_ALLRST_DR1_SHIFT)) & SYSCTL0_CLOUSTON_ALLRST_DR1_CLOUSTON_ALLRST_DR1_MASK)
/*! @} */

/*! @name SCRATCHN - Scratch */
/*! @{ */
#define SYSCTL0_SCRATCHN_SCRATCH_MASK            (0xFFFFFFFFU)
#define SYSCTL0_SCRATCHN_SCRATCH_SHIFT           (0U)
/*! SCRATCH - Scratch
 */
#define SYSCTL0_SCRATCHN_SCRATCH(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SCRATCHN_SCRATCH_SHIFT)) & SYSCTL0_SCRATCHN_SCRATCH_MASK)
/*! @} */

/*! @name MIPI_DSI_CTRL - MIPI DSI Control */
/*! @{ */
#define SYSCTL0_MIPI_DSI_CTRL_DSI_SD_MASK        (0x1U)
#define SYSCTL0_MIPI_DSI_CTRL_DSI_SD_SHIFT       (0U)
/*! DSI_SD - DSI Shutdown Control.
 *  0b0..Shutdown command not to be sent to the Type-4 display (default).
 *  0b1..Shutdown command to be sent to the Type-4 display
 */
#define SYSCTL0_MIPI_DSI_CTRL_DSI_SD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_CTRL_DSI_SD_SHIFT)) & SYSCTL0_MIPI_DSI_CTRL_DSI_SD_MASK)
#define SYSCTL0_MIPI_DSI_CTRL_DSI_CM_MASK        (0x2U)
#define SYSCTL0_MIPI_DSI_CTRL_DSI_CM_SHIFT       (1U)
/*! DSI_CM - DSI Color Mode Control.
 *  0b0..Normal mode (full color) (default)
 *  0b1..Low color mode (8-bit)
 */
#define SYSCTL0_MIPI_DSI_CTRL_DSI_CM(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_CTRL_DSI_CM_SHIFT)) & SYSCTL0_MIPI_DSI_CTRL_DSI_CM_MASK)
#define SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_MASK (0x4U)
#define SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_SHIFT (2U)
/*! DSI_TX_ACTIVE - DSI TX ACTIVE
 */
#define SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_SHIFT)) & SYSCTL0_MIPI_DSI_CTRL_DSI_TX_ACTIVE_MASK)
/*! @} */

/*! @name USB0CLKCTRL - USB Clock Control */
/*! @{ */
#define SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_MASK   (0x1U)
#define SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT  (0U)
/*! AP_FS_DEV_CLK - USB0 Device need clock signal control
 *  0b0..Under hardware control
 *  0b1..Forced high
 */
#define SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
#define SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_MASK  (0x2U)
#define SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
/*! POL_FS_DEV_CLK - USB0 Device need clock polarity for triggering the USB0 wake-up interrupt
 *  0b0..Falling edge of device need_clock triggers wake-up
 *  0b1..Rising edge of device need_clock triggers wake-up
 */
#define SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
#define SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_MASK  (0x4U)
#define SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
/*! AP_FS_HOST_CLK - USB0 Host need clock signal control
 *  0b0..Under hardware control
 *  0b1..Forced high
 */
#define SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
#define SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
#define SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
/*! POL_FS_HOST_CLK - USB0 HOST need clock polarity for triggering the USB0 wake-up interrupt
 *  0b0..Falling edge of host need_clock triggers wake-up
 *  0b1..Rising edge of host need_clock triggers wake-up
 */
#define SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCTL0_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
#define SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
#define SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode
 *  0b0..Forces USB0 PHY to wake-up
 *  0b1..Normal USB0 PHY behavior
 */
#define SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCTL0_USB0CLKCTRL_HS_DEV_WAKEUP_N_MASK)
/*! @} */

/*! @name USB0CLKSTAT - USB Clock Status */
/*! @{ */
#define SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_MASK  (0x1U)
#define SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status
 *  0b0..Low
 *  0b1..High
 */
#define SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCTL0_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
#define SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
#define SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
/*! HOST_NEED_CLKST - USB0 Device Host USB0_NEEDCLK signal status
 *  0b0..Low
 *  0b1..High
 */
#define SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
/*! @} */

/*! @name USBPHYPLL0LOCKTIMEDIV2 - USB PHY PLL0 lock time division */
/*! @{ */
#define SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK (0xFFFFU)
#define SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT (0U)
/*! LOCKTIMEDIV2 - USBPHYPLL0 Lock Time
 */
#define SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_SHIFT)) & SYSCTL0_USBPHYPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK)
/*! @} */

/*! @name PDSLEEPCFG0 - Sleep configuration 0 */
/*! @{ */
#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK (0x1U)
#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_SHIFT (0U)
/*! MAINCLK_SHUTOFF - Main clock shut off
 *  0b0..Clocks enabled
 *  0b1..Clocks disabled
 */
#define SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDSLEEPCFG0_MAINCLK_SHUTOFF_MASK)
#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK      (0x2U)
#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT     (1U)
/*! PMIC_MODE0 - PMIC_MODE0 device pin
 *  0b0..Set mode to 0
 *  0b1..Set mode to 1
 */
#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK)
#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK      (0x4U)
#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_SHIFT     (2U)
/*! PMIC_MODE1 - PMIC_MODE1 device pin
 *  0b0..Set mode to 0
 *  0b1..Set mode to 1
 */
#define SYSCTL0_PDSLEEPCFG0_PMIC_MODE1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK)
#define SYSCTL0_PDSLEEPCFG0_DEEP_PD_MASK         (0x8U)
#define SYSCTL0_PDSLEEPCFG0_DEEP_PD_SHIFT        (3U)
/*! DEEP_PD - Deep power-down mode
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_DEEP_PD(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_DEEP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_DEEP_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_MASK   (0x10U)
#define SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_SHIFT  (4U)
/*! VDDCOREREG_LP - Vddcore regulator mode
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_VDDCOREREG_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_PMCREF_LP_MASK       (0x40U)
#define SYSCTL0_PDSLEEPCFG0_PMCREF_LP_SHIFT      (6U)
/*! PMCREF_LP - Internal PMC references LP mode
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDSLEEPCFG0_PMCREF_LP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMCREF_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMCREF_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_MASK       (0x80U)
#define SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_SHIFT      (7U)
/*! HVD1V8_PD - HVD
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_HVD1V8_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HVD1V8_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_PORCORE_LP_MASK      (0x100U)
#define SYSCTL0_PDSLEEPCFG0_PORCORE_LP_SHIFT     (8U)
/*! PORCORE_LP - LVD
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDSLEEPCFG0_PORCORE_LP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PORCORE_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PORCORE_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_MASK      (0x200U)
#define SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_SHIFT     (9U)
/*! LVDCORE_LP - LVD
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDSLEEPCFG0_LVDCORE_LP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_LVDCORE_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_MASK      (0x400U)
#define SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_SHIFT     (10U)
/*! HVDCORE_PD - HVD
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_HVDCORE_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HVDCORE_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK          (0x800U)
#define SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT         (11U)
/*! RBB_PD - Reverse body-bias
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_RBB_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK          (0x1000U)
#define SYSCTL0_PDSLEEPCFG0_FBB_PD_SHIFT         (12U)
/*! FBB_PD - Forward body-bias
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_FBB_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_FBB_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_MASK      (0x2000U)
#define SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_SHIFT     (13U)
/*! SYSXTAL_PD - Main crystal oscillator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_SYSXTAL_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_LPOSC_PD_MASK        (0x4000U)
#define SYSCTL0_PDSLEEPCFG0_LPOSC_PD_SHIFT       (14U)
/*! LPOSC_PD - 1 MHz Low-Power oscillator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_LPOSC_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_LPOSC_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_LPOSC_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK      (0x8000U)
#define SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_SHIFT     (15U)
/*! RBBSRAM_PD - RBBSRAM
 *  0b0..Enables SRAM Reverse Body Bias
 *  0b1..Disables SRAM Reverse Body Bias
 */
#define SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_RBBSRAM_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_FFRO_PD_MASK         (0x10000U)
#define SYSCTL0_PDSLEEPCFG0_FFRO_PD_SHIFT        (16U)
/*! FFRO_PD - FFRO 48/60 MHz internal oscillator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_FFRO_PD(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_FFRO_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_FFRO_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_MASK    (0x20000U)
#define SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_SHIFT   (17U)
/*! SYSPLLLDO_PD - System PLL internal regulator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_SYSPLLLDO_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_MASK    (0x40000U)
#define SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_SHIFT   (18U)
/*! SYSPLLANA_PD - System PLL analog functions
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_SYSPLLANA_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_MASK    (0x80000U)
#define SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_SHIFT   (19U)
/*! AUDPLLLDO_PD - Audio PLL internal regulator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_AUDPLLLDO_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_MASK    (0x100000U)
#define SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_SHIFT   (20U)
/*! AUDPLLANA_PD - Audio PLL analog functions
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_AUDPLLANA_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_ADC_PD_MASK          (0x200000U)
#define SYSCTL0_PDSLEEPCFG0_ADC_PD_SHIFT         (21U)
/*! ADC_PD - ADC analog functions
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_ADC_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ADC_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ADC_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_ADC_LP_MASK          (0x400000U)
#define SYSCTL0_PDSLEEPCFG0_ADC_LP_SHIFT         (22U)
/*! ADC_LP - ADC low power mode
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_ADC_LP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ADC_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ADC_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_MASK  (0x800000U)
#define SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_SHIFT (23U)
/*! ADC_TEMPSNS_PD - ADC temperature sensor
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ADC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_MASK  (0x1000000U)
#define SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_SHIFT (24U)
/*! PMC_TEMPSNS_PD - PMC temperature sensor
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_PMC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_ACMP_PD_MASK         (0x2000000U)
#define SYSCTL0_PDSLEEPCFG0_ACMP_PD_SHIFT        (25U)
/*! ACMP_PD - Analog comparator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG0_ACMP_PD(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_ACMP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_ACMP_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
/*! HSPAD_FSPI0_VDET_LP - High speed pad voltage detect sleep mode
 *  0b0..High speed pad vdet in normal mode
 *  0b1..High speed pad vdet in sleep mode
 */
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_VDET_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_SHIFT (27U)
/*! HSPAD_FSPI0_REF_PD - High speed pad sleep mode
 *  0b0..High speed pad refs in normal mode
 *  0b1..High speed pad refs in sleep mode
 */
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI0_REF_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_MASK (0x10000000U)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_SHIFT (28U)
/*! HSPAD_SDIO0_VDET_LP - High Speed Pad VDET
 *  0b0..Normal mode
 *  0b1..Sleep mode
 */
#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_VDET_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_MASK (0x20000000U)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_SHIFT (29U)
/*! HSPAD_SDIO0_REF_PD - High Speed Pad VREF
 *  0b0..Enabled
 *  0b1..Disabled
 */
#define SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_SDIO0_REF_PD_MASK)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
/*! HSPAD_FSPI1_VDET_LP - Hi speed pad voltage detect sleep mode
 *  0b0..High speed pad vdet in normal mode
 *  0b1..High speed pad vdet in normal mode
 */
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_VDET_LP_MASK)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_SHIFT (31U)
/*! HSPAD_FSPI1_REF_PD - Hi speed pad sleep mode
 *  0b0..High speed pad refs in normal mode
 *  0b1..High speed pad refs in sleep mode
 */
#define SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG0_HSPAD_FSPI1_REF_PD_MASK)
/*! @} */

/*! @name PDSLEEPCFG1 - Sleep configuration 1 */
/*! @{ */
#define SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_MASK     (0x2U)
#define SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_SHIFT    (1U)
/*! PQ_SRAM_PPD - Periphery power for PowerQuad RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_PQ_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_MASK (0x4U)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_SHIFT (2U)
/*! FLEXSPI0_SRAM_APD - Array power for FLEXSPI0 RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_MASK (0x8U)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_SHIFT (3U)
/*! FLEXSPI0_SRAM_PPD - Periphery power for FLEXSPI0 RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI0_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_SHIFT (4U)
/*! FLEXSPI1_SRAM_APD - Array power for FLEXSPI1 RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_MASK (0x20U)
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_SHIFT (5U)
/*! FLEXSPI1_SRAM_PPD - Periphery power for FLEXSPI1 RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_FLEXSPI1_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_MASK  (0x40U)
#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_SHIFT (6U)
/*! USBHS_SRAM_APD - Array power for USB RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_MASK  (0x80U)
#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_SHIFT (7U)
/*! USBHS_SRAM_PPD - Periphery power for USB RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USBHS_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_MASK (0x100U)
#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_SHIFT (8U)
/*! USDHC0_SRAM_APD - Array power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_MASK (0x200U)
#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_SHIFT (9U)
/*! USDHC0_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC0_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_MASK (0x400U)
#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_SHIFT (10U)
/*! USDHC1_SRAM_APD - Array power for Casper RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_MASK (0x800U)
#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_SHIFT (11U)
/*! USDHC1_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_USDHC1_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_MASK (0x2000U)
#define SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_SHIFT (13U)
/*! CASPER_SRAM_PPD - Periphery power for Casper RAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_CASPER_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_MASK    (0x4000U)
#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_SHIFT   (14U)
/*! GPU_SRAM_APD - Array Power for GPU SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_GPU_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_MASK    (0x8000U)
#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_SHIFT   (15U)
/*! GPU_SRAM_PPD - Periphery Power for GPU SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_GPU_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_MASK (0x10000U)
#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_SHIFT (16U)
/*! SMARTDMA_SRAM_APD - Array Power for SMARTDMA SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_MASK (0x20000U)
#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_SHIFT (17U)
/*! SMARTDMA_SRAM_PPD - Periphery Power for SMARTDMA SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_SMARTDMA_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_MASK (0x40000U)
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_SHIFT (18U)
/*! MIPIDSI_SRAM_APD - Array Power for MIPIDSI SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_MASK (0x80000U)
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_SHIFT (19U)
/*! MIPIDSI_SRAM_PPD - Periphery Power for MIPIDSI SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_MIPIDSI_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_MASK  (0x100000U)
#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_SHIFT (20U)
/*! LCDIF_SRAM_APD - Array Power for LCDIF SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_APD_MASK)
#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_MASK  (0x200000U)
#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_SHIFT (21U)
/*! LCDIF_SRAM_PPD - Periphery Power for LCDIF SRAM
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_LCDIF_SRAM_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG1_DSP_PD_MASK          (0x2000000U)
#define SYSCTL0_PDSLEEPCFG1_DSP_PD_SHIFT         (25U)
/*! DSP_PD - DSP
 *  0b0..DSP not power gated
 *  0b1..DSP power gated
 */
#define SYSCTL0_PDSLEEPCFG1_DSP_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_DSP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_DSP_PD_MASK)
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_MASK      (0x4000000U)
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_SHIFT     (26U)
/*! MIPIDSI_PD - MIPIDSI
 *  0b0..MIPI DSI not power gated
 *  0b1..MIPI DSI power gated
 */
#define SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_MIPIDSI_PD_MASK)
#define SYSCTL0_PDSLEEPCFG1_OTP_PD_MASK          (0x8000000U)
#define SYSCTL0_PDSLEEPCFG1_OTP_PD_SHIFT         (27U)
/*! OTP_PD - OTP
 *  0b0..Powered
 *  0b1..Not Powered
 */
#define SYSCTL0_PDSLEEPCFG1_OTP_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_OTP_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_OTP_PD_MASK)
#define SYSCTL0_PDSLEEPCFG1_ROM_PD_MASK          (0x10000000U)
#define SYSCTL0_PDSLEEPCFG1_ROM_PD_SHIFT         (28U)
/*! ROM_PD - ROM
 *  0b0..ROM Powered
 *  0b1..ROM not Powered
 */
#define SYSCTL0_PDSLEEPCFG1_ROM_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_ROM_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_ROM_PD_MASK)
#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
/*! HSPAD_SDIO1_VDET_LP - High speed pad SDIO1 voltage detect sleep mode
 *  0b0..Normal mode
 *  0b1..Sleep mode
 */
#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_VDET_LP_MASK)
#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_SHIFT (30U)
/*! HSPAD_SDIO1_REF_PD - High speed pad SDIO1 sleep mode
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDSLEEPCFG1_HSPAD_SDIO1_REF_PD_MASK)
#define SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_MASK      (0x80000000U)
#define SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_SHIFT     (31U)
/*! SRAM_SLEEP - SRAM sleep mode
 *  0b0..RAM Normal mode
 *  0b1..RAM Sleep mode. Needed when vddcore can be < 0.850V to ensure contents retained. Memories not accessible in this mode.
 */
#define SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDSLEEPCFG1_SRAM_SLEEP_MASK)
/*! @} */

/*! @name PDSLEEPCFG2 - Sleep configuration 2 */
/*! @{ */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK    (0x1U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_SHIFT   (0U)
/*! SRAM_IF0_APD - Array power for RAM interface 0
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF0_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK    (0x2U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_SHIFT   (1U)
/*! SRAM_IF1_APD - Array power for RAM interface 1
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF1_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK    (0x4U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_SHIFT   (2U)
/*! SRAM_IF2_APD - Array power for RAM interface 2
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF2_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK    (0x8U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_SHIFT   (3U)
/*! SRAM_IF3_APD - Array power for RAM interface 3
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF3_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK    (0x10U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_SHIFT   (4U)
/*! SRAM_IF4_APD - Array power for RAM interface 4
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF4_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK    (0x20U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_SHIFT   (5U)
/*! SRAM_IF5_APD - Array power for RAM interface 5
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF5_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK    (0x40U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_SHIFT   (6U)
/*! SRAM_IF6_APD - Array power for RAM interface 6
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF6_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK    (0x80U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_SHIFT   (7U)
/*! SRAM_IF7_APD - Array power for RAM interface 7
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF7_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK    (0x100U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_SHIFT   (8U)
/*! SRAM_IF8_APD - Array power for RAM interface 8
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF8_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK    (0x200U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_SHIFT   (9U)
/*! SRAM_IF9_APD - Array power for RAM interface 9
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF9_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_MASK   (0x400U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_SHIFT  (10U)
/*! SRAM_IF10_APD - Array power for RAM interface 10
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF10_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_MASK   (0x800U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_SHIFT  (11U)
/*! SRAM_IF11_APD - Array power for RAM interface 11
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF11_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_MASK   (0x1000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_SHIFT  (12U)
/*! SRAM_IF12_APD - Array power for RAM interface 12
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF12_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_MASK   (0x2000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_SHIFT  (13U)
/*! SRAM_IF13_APD - Array power for RAM interface 13
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF13_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_MASK   (0x4000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_SHIFT  (14U)
/*! SRAM_IF14_APD - Array power for RAM interface 14
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF14_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_MASK   (0x8000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_SHIFT  (15U)
/*! SRAM_IF15_APD - Array power for RAM interface 15
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF15_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_MASK   (0x10000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_SHIFT  (16U)
/*! SRAM_IF16_APD - Array power for RAM interface 16
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF16_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_MASK   (0x20000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_SHIFT  (17U)
/*! SRAM_IF17_APD - Array power for RAM interface 17
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF17_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_MASK   (0x40000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_SHIFT  (18U)
/*! SRAM_IF18_APD - Array power for RAM interface 18
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF18_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_MASK   (0x80000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_SHIFT  (19U)
/*! SRAM_IF19_APD - Array power for RAM interface 19
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF19_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_MASK   (0x100000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_SHIFT  (20U)
/*! SRAM_IF20_APD - Array power for RAM interface 20
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF20_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_MASK   (0x200000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_SHIFT  (21U)
/*! SRAM_IF21_APD - Array power for RAM interface 21
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF21_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_MASK   (0x400000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_SHIFT  (22U)
/*! SRAM_IF22_APD - Array power for RAM interface 22
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF22_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_MASK   (0x800000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_SHIFT  (23U)
/*! SRAM_IF23_APD - Array power for RAM interface 23
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF23_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_MASK   (0x1000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_SHIFT  (24U)
/*! SRAM_IF24_APD - Array power for RAM interface 24
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF24_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_MASK   (0x2000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_SHIFT  (25U)
/*! SRAM_IF25_APD - Array power for RAM interface 25
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF25_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_MASK   (0x4000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_SHIFT  (26U)
/*! SRAM_IF26_APD - Array power for RAM interface 26
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF26_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_MASK   (0x8000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_SHIFT  (27U)
/*! SRAM_IF27_APD - Array power for RAM interface 27
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF27_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_MASK   (0x10000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_SHIFT  (28U)
/*! SRAM_IF28_APD - Array power for RAM interface 28
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF28_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_MASK   (0x20000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_SHIFT  (29U)
/*! SRAM_IF29_APD - Array power for RAM interface 29
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF29_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_MASK   (0x40000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_SHIFT  (30U)
/*! SRAM_IF30_APD - Array power for RAM interface 30
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF30_APD_MASK)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_MASK   (0x80000000U)
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_SHIFT  (31U)
/*! SRAM_IF31_APD - Array power for RAM interface 31
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDSLEEPCFG2_SRAM_IF31_APD_MASK)
/*! @} */

/*! @name PDSLEEPCFG3 - Sleep configuration 3 */
/*! @{ */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_MASK    (0x1U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_SHIFT   (0U)
/*! SRAM_IF0_PPD - Periphery power for RAM interface 0
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF0_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_MASK    (0x2U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_SHIFT   (1U)
/*! SRAM_IF1_PPD - Periphery power for RAM interface 1
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF1_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_MASK    (0x4U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_SHIFT   (2U)
/*! SRAM_IF2_PPD - Periphery power for RAM interface 2
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF2_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_MASK    (0x8U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_SHIFT   (3U)
/*! SRAM_IF3_PPD - Periphery power for RAM interface 3
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF3_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_MASK    (0x10U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_SHIFT   (4U)
/*! SRAM_IF4_PPD - Periphery power for RAM interface 4
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF4_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_MASK    (0x20U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_SHIFT   (5U)
/*! SRAM_IF5_PPD - Periphery power for RAM interface 5
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF5_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_MASK    (0x40U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_SHIFT   (6U)
/*! SRAM_IF6_PPD - Periphery power for RAM interface 6
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF6_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_MASK    (0x80U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_SHIFT   (7U)
/*! SRAM_IF7_PPD - Periphery power for RAM interface 7
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF7_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_MASK    (0x100U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_SHIFT   (8U)
/*! SRAM_IF8_PPD - Periphery power for RAM interface 8
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF8_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_MASK    (0x200U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_SHIFT   (9U)
/*! SRAM_IF9_PPD - Periphery power for RAM interface 9
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF9_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_MASK   (0x400U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_SHIFT  (10U)
/*! SRAM_IF10_PPD - Periphery power for RAM interface 10
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF10_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_MASK   (0x800U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_SHIFT  (11U)
/*! SRAM_IF11_PPD - Periphery power for RAM interface 11
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF11_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_MASK   (0x1000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_SHIFT  (12U)
/*! SRAM_IF12_PPD - Periphery power for RAM interface 12
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF12_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_MASK   (0x2000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_SHIFT  (13U)
/*! SRAM_IF13_PPD - Periphery power for RAM interface 13
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF13_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_MASK   (0x4000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_SHIFT  (14U)
/*! SRAM_IF14_PPD - Periphery power for RAM interface 14
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF14_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_MASK   (0x8000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_SHIFT  (15U)
/*! SRAM_IF15_PPD - Periphery power for RAM interface 15
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF15_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_MASK   (0x10000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_SHIFT  (16U)
/*! SRAM_IF16_PPD - Periphery power for RAM interface 16
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF16_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_MASK   (0x20000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_SHIFT  (17U)
/*! SRAM_IF17_PPD - Periphery power for RAM interface 17
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF17_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_MASK   (0x40000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_SHIFT  (18U)
/*! SRAM_IF18_PPD - Periphery power for RAM interface 18
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF18_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_MASK   (0x80000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_SHIFT  (19U)
/*! SRAM_IF19_PPD - Periphery power for RAM interface 19
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF19_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_MASK   (0x100000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_SHIFT  (20U)
/*! SRAM_IF20_PPD - Periphery power for RAM interface 20
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF20_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_MASK   (0x200000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_SHIFT  (21U)
/*! SRAM_IF21_PPD - Periphery power for RAM interface 21
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF21_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_MASK   (0x400000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_SHIFT  (22U)
/*! SRAM_IF22_PPD - Periphery power for RAM interface 22
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF22_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_MASK   (0x800000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_SHIFT  (23U)
/*! SRAM_IF23_PPD - Periphery power for RAM interface 23
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF23_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_MASK   (0x1000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_SHIFT  (24U)
/*! SRAM_IF24_PPD - Periphery power for RAM interface 24
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF24_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_MASK   (0x2000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_SHIFT  (25U)
/*! SRAM_IF25_PPD - Periphery power for RAM interface 25
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF25_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_MASK   (0x4000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_SHIFT  (26U)
/*! SRAM_IF26_PPD - Periphery power for RAM interface 26
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF26_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_MASK   (0x8000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_SHIFT  (27U)
/*! SRAM_IF27_PPD - Periphery power for RAM interface 27
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF27_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_MASK   (0x10000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_SHIFT  (28U)
/*! SRAM_IF28_PPD - Periphery power for RAM interface 28
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF28_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_MASK   (0x20000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_SHIFT  (29U)
/*! SRAM_IF29_PPD - Periphery power for RAM interface 29
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF29_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_MASK   (0x40000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_SHIFT  (30U)
/*! SRAM_IF30_PPD - Periphery power for RAM interface 30
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF30_PPD_MASK)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_MASK   (0x80000000U)
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_SHIFT  (31U)
/*! SRAM_IF31_PPD - Periphery power for RAM interface 31
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDSLEEPCFG3_SRAM_IF31_PPD_MASK)
/*! @} */

/*! @name PDRUNCFG0 - Run configuration 0 */
/*! @{ */
#define SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_MASK   (0x1U)
#define SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_SHIFT  (0U)
/*! MAINCLK_SHUTOFF - Main clock shut off
 *  0b0..Clocks enabled
 *  0b1..Clocks gated
 */
#define SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDRUNCFG0_MAINCLK_SHUTOFF_MASK)
#define SYSCTL0_PDRUNCFG0_PMIC_MODE0_MASK        (0x2U)
#define SYSCTL0_PDRUNCFG0_PMIC_MODE0_SHIFT       (1U)
/*! PMIC_MODE0 - PMIC_MODE0 device pin
 *  0b0..Set mode to 0
 *  0b1..Set mode to 1
 */
#define SYSCTL0_PDRUNCFG0_PMIC_MODE0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMIC_MODE0_SHIFT)) & SYSCTL0_PDRUNCFG0_PMIC_MODE0_MASK)
#define SYSCTL0_PDRUNCFG0_PMIC_MODE1_MASK        (0x4U)
#define SYSCTL0_PDRUNCFG0_PMIC_MODE1_SHIFT       (2U)
/*! PMIC_MODE1 - PMIC_MODE1 device pin
 *  0b0..Set mode to 0
 *  0b1..Set mode to 1
 */
#define SYSCTL0_PDRUNCFG0_PMIC_MODE1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMIC_MODE1_SHIFT)) & SYSCTL0_PDRUNCFG0_PMIC_MODE1_MASK)
#define SYSCTL0_PDRUNCFG0_DEEP_PD_MASK           (0x8U)
#define SYSCTL0_PDRUNCFG0_DEEP_PD_SHIFT          (3U)
/*! DEEP_PD - Deep power-down mode
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_DEEP_PD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_DEEP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_DEEP_PD_MASK)
#define SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_MASK     (0x10U)
#define SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_SHIFT    (4U)
/*! VDDCOREREG_LP - Vddcore regulator mode
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDRUNCFG0_VDDCOREREG_LP(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_VDDCOREREG_LP_MASK)
#define SYSCTL0_PDRUNCFG0_PMCREF_LP_MASK         (0x40U)
#define SYSCTL0_PDRUNCFG0_PMCREF_LP_SHIFT        (6U)
/*! PMCREF_LP - Internal PMC references LP mode
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDRUNCFG0_PMCREF_LP(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMCREF_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_PMCREF_LP_MASK)
#define SYSCTL0_PDRUNCFG0_HVD1V8_PD_MASK         (0x80U)
#define SYSCTL0_PDRUNCFG0_HVD1V8_PD_SHIFT        (7U)
/*! HVD1V8_PD - HVD
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_HVD1V8_PD(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HVD1V8_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HVD1V8_PD_MASK)
#define SYSCTL0_PDRUNCFG0_PORCORE_LP_MASK        (0x100U)
#define SYSCTL0_PDRUNCFG0_PORCORE_LP_SHIFT       (8U)
/*! PORCORE_LP - LVD
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDRUNCFG0_PORCORE_LP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PORCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_PORCORE_LP_MASK)
#define SYSCTL0_PDRUNCFG0_LVDCORE_LP_MASK        (0x200U)
#define SYSCTL0_PDRUNCFG0_LVDCORE_LP_SHIFT       (9U)
/*! LVDCORE_LP - LVD
 *  0b0..HP mode
 *  0b1..LP mode
 */
#define SYSCTL0_PDRUNCFG0_LVDCORE_LP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_LVDCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_LVDCORE_LP_MASK)
#define SYSCTL0_PDRUNCFG0_HVDCORE_PD_MASK        (0x400U)
#define SYSCTL0_PDRUNCFG0_HVDCORE_PD_SHIFT       (10U)
/*! HVDCORE_PD - HVD
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_HVDCORE_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HVDCORE_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HVDCORE_PD_MASK)
#define SYSCTL0_PDRUNCFG0_RBB_PD_MASK            (0x800U)
#define SYSCTL0_PDRUNCFG0_RBB_PD_SHIFT           (11U)
/*! RBB_PD - Reverse body-bias
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_RBB_PD(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_RBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_RBB_PD_MASK)
#define SYSCTL0_PDRUNCFG0_FBB_PD_MASK            (0x1000U)
#define SYSCTL0_PDRUNCFG0_FBB_PD_SHIFT           (12U)
/*! FBB_PD - Forward body-bias
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_FBB_PD(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_FBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_FBB_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SYSXTAL_PD_MASK        (0x2000U)
#define SYSCTL0_PDRUNCFG0_SYSXTAL_PD_SHIFT       (13U)
/*! SYSXTAL_PD - Main crystal oscillator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_SYSXTAL_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SYSXTAL_PD_MASK)
#define SYSCTL0_PDRUNCFG0_LPOSC_PD_MASK          (0x4000U)
#define SYSCTL0_PDRUNCFG0_LPOSC_PD_SHIFT         (14U)
/*! LPOSC_PD - 1 MHz Low-Power oscillator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_LPOSC_PD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_LPOSC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_LPOSC_PD_MASK)
#define SYSCTL0_PDRUNCFG0_RBBSRAM_PD_MASK        (0x8000U)
#define SYSCTL0_PDRUNCFG0_RBBSRAM_PD_SHIFT       (15U)
/*! RBBSRAM_PD - Reverse body-bias SRAM
 *  0b0..Enables SRAM Reverse Body Bias
 *  0b1..Disables SRAM Reverse Body Bias
 */
#define SYSCTL0_PDRUNCFG0_RBBSRAM_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_RBBSRAM_PD_MASK)
#define SYSCTL0_PDRUNCFG0_FFRO_PD_MASK           (0x10000U)
#define SYSCTL0_PDRUNCFG0_FFRO_PD_SHIFT          (16U)
/*! FFRO_PD - FFRO 48/60 MHz internal oscillator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_FFRO_PD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_FFRO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_FFRO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK      (0x20000U)
#define SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_SHIFT     (17U)
/*! SYSPLLLDO_PD - System PLL internal regulator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK      (0x40000U)
#define SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_SHIFT     (18U)
/*! SYSPLLANA_PD - System PLL analog functions
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_SYSPLLANA_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK)
#define SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK      (0x80000U)
#define SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_SHIFT     (19U)
/*! AUDPLLLDO_PD - Audio PLL internal regulator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK      (0x100000U)
#define SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_SHIFT     (20U)
/*! AUDPLLANA_PD - Audio PLL analog functions
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_AUDPLLANA_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK)
#define SYSCTL0_PDRUNCFG0_ADC_PD_MASK            (0x200000U)
#define SYSCTL0_PDRUNCFG0_ADC_PD_SHIFT           (21U)
/*! ADC_PD - ADC analog functions
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_ADC_PD(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ADC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_ADC_PD_MASK)
#define SYSCTL0_PDRUNCFG0_ADC_LP_MASK            (0x400000U)
#define SYSCTL0_PDRUNCFG0_ADC_LP_SHIFT           (22U)
/*! ADC_LP - ADC low power mode
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_ADC_LP(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ADC_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_ADC_LP_MASK)
#define SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_MASK    (0x800000U)
#define SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_SHIFT   (23U)
/*! ADC_TEMPSNS_PD - ADC temperature sensor
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_ADC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_MASK    (0x1000000U)
#define SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_SHIFT   (24U)
/*! PMC_TEMPSNS_PD - PMC temperature sensor
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_PMC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDRUNCFG0_ACMP_PD_MASK           (0x2000000U)
#define SYSCTL0_PDRUNCFG0_ACMP_PD_SHIFT          (25U)
/*! ACMP_PD - Analog comparator
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG0_ACMP_PD(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_ACMP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_ACMP_PD_MASK)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
/*! HSPAD_FSPI0_VDET_LP - Hi-speed pad voltage detect sleep mode
 *  0b0..High speed pad vdet in normal mode
 *  0b1..High speed pad vdet in sleep mode
 */
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_SHIFT (27U)
/*! HSPAD_FSPI0_REF_PD - Hi-speed pad sleep mode
 *  0b0..High speed pad refs in normal mode
 *  0b1..High speed pad refs in sleep mode
 */
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI0_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_MASK (0x10000000U)
#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_SHIFT (28U)
/*! HSPAD_SDIO0_VDET_LP - High Speed Pad VDET
 *  0b0..Normal mode
 *  0b1..Sleep mode
 */
#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_SHIFT (29U)
/*! HSPAD_SDIO0_REF_PD - High Speed Pad VREF
 *  0b0..Enabled
 *  0b1..Disabled
 */
#define SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_SDIO0_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
/*! HSPAD_FSPI1_VDET_LP - Hi speed pad voltage detect sleep mode
 *  0b0..High speed pad vdet in normal mode
 *  0b1..High speed pad vdet in normal mode
 */
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_SHIFT (31U)
/*! HSPAD_FSPI1_REF_PD - Hi speed pad sleep mode
 *  0b0..High speed pad refs in normal mode
 *  0b1..High speed pad refs in sleep mode
 */
#define SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_HSPAD_FSPI1_REF_PD_MASK)
/*! @} */

/*! @name PDRUNCFG1 - Run configuration 1 */
/*! @{ */
#define SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_MASK       (0x2U)
#define SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_SHIFT      (1U)
/*! PQ_SRAM_PPD - Power Quad SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_PQ_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_MASK (0x4U)
#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_SHIFT (2U)
/*! FLEXSPI0_SRAM_APD - FLEXSPI0 SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_MASK (0x8U)
#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_SHIFT (3U)
/*! FLEXSPI0_SRAM_PPD - FLEXSPI0 SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI0_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK (0x10U)
#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT (4U)
/*! FLEXSPI1_SRAM_APD - FLEXSPI1 SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_MASK (0x20U)
#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_SHIFT (5U)
/*! FLEXSPI1_SRAM_PPD - FLEXSPI1 SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_FLEXSPI1_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_MASK    (0x40U)
#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_SHIFT   (6U)
/*! USBHS_SRAM_APD - USBHS SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_USBHS_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_MASK    (0x80U)
#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_SHIFT   (7U)
/*! USBHS_SRAM_PPD - USBHS SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_USBHS_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_MASK   (0x100U)
#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_SHIFT  (8U)
/*! USDHC0_SRAM_APD - USDHC0 SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC0_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_MASK   (0x200U)
#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_SHIFT  (9U)
/*! USDHC0_SRAM_PPD - USDHC0 SRAM_ Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC0_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_MASK   (0x400U)
#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_SHIFT  (10U)
/*! USDHC1_SRAM_APD - USDHC1 SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC1_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_MASK   (0x800U)
#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_SHIFT  (11U)
/*! USDHC1_SRAM_PPD - USDHC1 SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_USDHC1_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_MASK   (0x2000U)
#define SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_SHIFT  (13U)
/*! CASPER_SRAM_PPD - CASPER SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CASPER_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_MASK      (0x4000U)
#define SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_SHIFT     (14U)
/*! GPU_SRAM_APD - GPU Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_GPU_SRAM_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_GPU_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_MASK      (0x8000U)
#define SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_SHIFT     (15U)
/*! GPU_SRAM_PPD - GPU Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_GPU_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_SHIFT (16U)
/*! SMARTDMA_SRAM_APD - SMARTDMA SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_SHIFT (17U)
/*! SMARTDMA_SRAM_PPD - SMARTDMA SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SMARTDMA_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_MASK  (0x40000U)
#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_SHIFT (18U)
/*! MIPIDSI_SRAM_APD - MIPIDSI SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_MASK  (0x80000U)
#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_SHIFT (19U)
/*! MIPIDSI_SRAM_PPD - MIPIDSI SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_MIPIDSI_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_MASK    (0x100000U)
#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_SHIFT   (20U)
/*! LCDIF_SRAM_APD - LCDIF SRAM Array Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_LCDIF_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_MASK    (0x200000U)
#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_SHIFT   (21U)
/*! LCDIF_SRAM_PPD - LCDIF SRAM Periphery Power
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_LCDIF_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_DSP_PD_MASK            (0x2000000U)
#define SYSCTL0_PDRUNCFG1_DSP_PD_SHIFT           (25U)
/*! DSP_PD - DSP
 *  0b0..DSP not power gated
 *  0b1..DSP power gated
 */
#define SYSCTL0_PDRUNCFG1_DSP_PD(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_DSP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_DSP_PD_MASK)
#define SYSCTL0_PDRUNCFG1_MIPIDSI_PD_MASK        (0x4000000U)
#define SYSCTL0_PDRUNCFG1_MIPIDSI_PD_SHIFT       (26U)
/*! MIPIDSI_PD - MIPIDSI
 *  0b0..MIPI DSI not power gated
 *  0b1..MIPI DSI power gated
 */
#define SYSCTL0_PDRUNCFG1_MIPIDSI_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_MIPIDSI_PD_MASK)
#define SYSCTL0_PDRUNCFG1_OTP_PD_MASK            (0x8000000U)
#define SYSCTL0_PDRUNCFG1_OTP_PD_SHIFT           (27U)
/*! OTP_PD - OTP
 *  0b0..Powered
 *  0b1..Not Powered
 */
#define SYSCTL0_PDRUNCFG1_OTP_PD(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_OTP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_OTP_PD_MASK)
#define SYSCTL0_PDRUNCFG1_ROM_PD_MASK            (0x10000000U)
#define SYSCTL0_PDRUNCFG1_ROM_PD_SHIFT           (28U)
/*! ROM_PD - Array periphery power for ROM
 *  0b0..ROM Powered
 *  0b1..ROM not Powered
 */
#define SYSCTL0_PDRUNCFG1_ROM_PD(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_ROM_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_ROM_PD_MASK)
#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
/*! HSPAD_SDIO1_VDET_LP - High speed pad SDIO1 voltage detect sleep mode
 *  0b0..Normal mode
 *  0b1..Sleep mode
 */
#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_SHIFT (30U)
/*! HSPAD_SDIO1_REF_PD - High speed pad SDIO1 sleep mode
 *  0b0..Enabled
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_HSPAD_SDIO1_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG1_SRAM_SLEEP_MASK        (0x80000000U)
#define SYSCTL0_PDRUNCFG1_SRAM_SLEEP_SHIFT       (31U)
/*! SRAM_SLEEP - SRAM sleep mode
 *  0b0..RAM Normal mode
 *  0b1..RAM Sleep mode. Needed when vddcore can be < 0.850V to ensure contents retained. Memories not accessible in this mode.
 */
#define SYSCTL0_PDRUNCFG1_SRAM_SLEEP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_SRAM_SLEEP_MASK)
/*! @} */

/*! @name PDRUNCFG2 - Run configuration 2 */
/*! @{ */
#define SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_MASK      (0x1U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_SHIFT     (0U)
/*! SRAM_IF0_APD - Array Power for RAM interface 0
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF0_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF0_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_MASK      (0x2U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_SHIFT     (1U)
/*! SRAM_IF1_APD - Array Power for RAM interface 1
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF1_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF1_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_MASK      (0x4U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_SHIFT     (2U)
/*! SRAM_IF2_APD - Array Power for RAM interface 2
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF2_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF2_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_MASK      (0x8U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_SHIFT     (3U)
/*! SRAM_IF3_APD - Array Power for RAM interface 3
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF3_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF3_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_MASK      (0x10U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_SHIFT     (4U)
/*! SRAM_IF4_APD - Array Power for RAM interface 4
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF4_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF4_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_MASK      (0x20U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_SHIFT     (5U)
/*! SRAM_IF5_APD - Array Power for RAM interface 5
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF5_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF5_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_MASK      (0x40U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_SHIFT     (6U)
/*! SRAM_IF6_APD - Array Power for RAM interface 6
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF6_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF6_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_MASK      (0x80U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_SHIFT     (7U)
/*! SRAM_IF7_APD - Array Power for RAM interface 7
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF7_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF7_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_MASK      (0x100U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_SHIFT     (8U)
/*! SRAM_IF8_APD - Array Power for RAM interface 8
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF8_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF8_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_MASK      (0x200U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_SHIFT     (9U)
/*! SRAM_IF9_APD - Array Power for RAM interface 9
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF9_APD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF9_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_MASK     (0x400U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_SHIFT    (10U)
/*! SRAM_IF10_APD - Array Power for RAM interface 10
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF10_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF10_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_MASK     (0x800U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_SHIFT    (11U)
/*! SRAM_IF11_APD - Array Power for RAM interface 11
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF11_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF11_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_MASK     (0x1000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_SHIFT    (12U)
/*! SRAM_IF12_APD - Array Power for RAM interface 12
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF12_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF12_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_MASK     (0x2000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_SHIFT    (13U)
/*! SRAM_IF13_APD - Array Power for RAM interface 13
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF13_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF13_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_MASK     (0x4000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_SHIFT    (14U)
/*! SRAM_IF14_APD - Array Power for RAM interface 14
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF14_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF14_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_MASK     (0x8000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_SHIFT    (15U)
/*! SRAM_IF15_APD - Array Power for RAM interface 15
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF15_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF15_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_MASK     (0x10000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_SHIFT    (16U)
/*! SRAM_IF16_APD - Array Power for RAM interface 16
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF16_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF16_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_MASK     (0x20000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_SHIFT    (17U)
/*! SRAM_IF17_APD - Array Power for RAM interface 17
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF17_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF17_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_MASK     (0x40000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_SHIFT    (18U)
/*! SRAM_IF18_APD - Array Power for RAM interface 18
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF18_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF18_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_MASK     (0x80000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_SHIFT    (19U)
/*! SRAM_IF19_APD - Array Power for RAM interface 19
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF19_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF19_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_MASK     (0x100000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_SHIFT    (20U)
/*! SRAM_IF20_APD - Array Power for RAM interface 20
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF20_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF20_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_MASK     (0x200000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_SHIFT    (21U)
/*! SRAM_IF21_APD - Array Power for RAM interface 21
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF21_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF21_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_MASK     (0x400000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_SHIFT    (22U)
/*! SRAM_IF22_APD - Array Power for RAM interface 22
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF22_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF22_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_MASK     (0x800000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_SHIFT    (23U)
/*! SRAM_IF23_APD - Array Power for RAM interface 23
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF23_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF23_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_MASK     (0x1000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_SHIFT    (24U)
/*! SRAM_IF24_APD - Array Power for RAM interface 24
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF24_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF24_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_MASK     (0x2000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_SHIFT    (25U)
/*! SRAM_IF25_APD - Array Power for RAM interface 25
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF25_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF25_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_MASK     (0x4000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_SHIFT    (26U)
/*! SRAM_IF26_APD - Array Power for RAM interface 26
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF26_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF26_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_MASK     (0x8000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_SHIFT    (27U)
/*! SRAM_IF27_APD - Array Power for RAM interface 27
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF27_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF27_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_MASK     (0x10000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_SHIFT    (28U)
/*! SRAM_IF28_APD - Array Power for RAM interface 28
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF28_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF28_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_MASK     (0x20000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_SHIFT    (29U)
/*! SRAM_IF29_APD - Array Power for RAM interface 29
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF29_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF29_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_MASK     (0x40000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_SHIFT    (30U)
/*! SRAM_IF30_APD - Array Power for RAM interface 30
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF30_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF30_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_MASK     (0x80000000U)
#define SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_SHIFT    (31U)
/*! SRAM_IF31_APD - Array Power for RAM interface 31
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG2_SRAM_IF31_APD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SRAM_IF31_APD_MASK)
/*! @} */

/*! @name PDRUNCFG3 - Run configuration 3 */
/*! @{ */
#define SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_MASK      (0x1U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_SHIFT     (0U)
/*! SRAM_IF0_PPD - Periphery power for RAM interface 0.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF0_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_MASK      (0x2U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_SHIFT     (1U)
/*! SRAM_IF1_PPD - Periphery power for RAM interface 1.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF1_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_MASK      (0x4U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_SHIFT     (2U)
/*! SRAM_IF2_PPD - Periphery power for RAM interface 2.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF2_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_MASK      (0x8U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_SHIFT     (3U)
/*! SRAM_IF3_PPD - Periphery power for RAM interface 3.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF3_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_MASK      (0x10U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_SHIFT     (4U)
/*! SRAM_IF4_PPD - Periphery power for RAM interface 4.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF4_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_MASK      (0x20U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_SHIFT     (5U)
/*! SRAM_IF5_PPD - Periphery power for RAM interface 5.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF5_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_MASK      (0x40U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_SHIFT     (6U)
/*! SRAM_IF6_PPD - Periphery power for RAM interface 6.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF6_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_MASK      (0x80U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_SHIFT     (7U)
/*! SRAM_IF7_PPD - Periphery power for RAM interface 7.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF7_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_MASK      (0x100U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_SHIFT     (8U)
/*! SRAM_IF8_PPD - Periphery power for RAM interface 8.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF8_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_MASK      (0x200U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_SHIFT     (9U)
/*! SRAM_IF9_PPD - Periphery power for RAM interface 9.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF9_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_MASK     (0x400U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_SHIFT    (10U)
/*! SRAM_IF10_PPD - Periphery power for RAM interface 10.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF10_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_MASK     (0x800U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_SHIFT    (11U)
/*! SRAM_IF11_PPD - Periphery power for RAM interface 11.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF11_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_MASK     (0x1000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_SHIFT    (12U)
/*! SRAM_IF12_PPD - Periphery power for RAM interface 12.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF12_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_MASK     (0x2000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_SHIFT    (13U)
/*! SRAM_IF13_PPD - Periphery power for RAM interface 13.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF13_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_MASK     (0x4000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_SHIFT    (14U)
/*! SRAM_IF14_PPD - Periphery power for RAM interface 14.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF14_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_MASK     (0x8000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_SHIFT    (15U)
/*! SRAM_IF15_PPD - Periphery power for RAM interface 15.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF15_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_MASK     (0x10000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_SHIFT    (16U)
/*! SRAM_IF16_PPD - Periphery power for RAM interface 16.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF16_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_MASK     (0x20000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_SHIFT    (17U)
/*! SRAM_IF17_PPD - Periphery power for RAM interface 17.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF17_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_MASK     (0x40000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_SHIFT    (18U)
/*! SRAM_IF18_PPD - Periphery power for RAM interface 18.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF18_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_MASK     (0x80000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_SHIFT    (19U)
/*! SRAM_IF19_PPD - Periphery power for RAM interface 19.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF19_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_MASK     (0x100000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_SHIFT    (20U)
/*! SRAM_IF20_PPD - Periphery power for RAM interface 20.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF20_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_MASK     (0x200000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_SHIFT    (21U)
/*! SRAM_IF21_PPD - Periphery power for RAM interface 21.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF21_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_MASK     (0x400000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_SHIFT    (22U)
/*! SRAM_IF22_PPD - Periphery power for RAM interface 22.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF22_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_MASK     (0x800000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_SHIFT    (23U)
/*! SRAM_IF23_PPD - Periphery power for RAM interface 23.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF23_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_MASK     (0x1000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_SHIFT    (24U)
/*! SRAM_IF24_PPD - Periphery power for RAM interface 24.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF24_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_MASK     (0x2000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_SHIFT    (25U)
/*! SRAM_IF25_PPD - Periphery power for RAM interface 25.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF25_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_MASK     (0x4000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_SHIFT    (26U)
/*! SRAM_IF26_PPD - Periphery power for RAM interface 26.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF26_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_MASK     (0x8000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_SHIFT    (27U)
/*! SRAM_IF27_PPD - Periphery power for RAM interface 27.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF27_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_MASK     (0x10000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_SHIFT    (28U)
/*! SRAM_IF28_PPD - Periphery power for RAM interface 28.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF28_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_MASK     (0x20000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_SHIFT    (29U)
/*! SRAM_IF29_PPD - Periphery power for RAM interface 29.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF29_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_MASK     (0x40000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_SHIFT    (30U)
/*! SRAM_IF30_PPD - Periphery power for RAM interface 30.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF30_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_MASK     (0x80000000U)
#define SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_SHIFT    (31U)
/*! SRAM_IF31_PPD - Periphery power for RAM interface 31.
 *  0b0..Enable
 *  0b1..Powerdown
 */
#define SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SRAM_IF31_PPD_MASK)
/*! @} */

/*! @name PDRUNCFG0_SET - Run configuration 0 set */
/*! @{ */
#define SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_MASK (0x1U)
#define SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_SHIFT (0U)
/*! MAINCLK_SHUTOFF - Main clock shut off
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_MAINCLK_SHUTOFF_MASK)
#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_MASK    (0x2U)
#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_SHIFT   (1U)
/*! PMIC_MODE0 - PMIC_MODE0 pin
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMIC_MODE0_MASK)
#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_MASK    (0x4U)
#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_SHIFT   (2U)
/*! PMIC_MODE1 - PMIC_MODE1 pin
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMIC_MODE1_MASK)
#define SYSCTL0_PDRUNCFG0_SET_DEEP_PD_MASK       (0x8U)
#define SYSCTL0_PDRUNCFG0_SET_DEEP_PD_SHIFT      (3U)
/*! DEEP_PD - Deep power-down mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_DEEP_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_DEEP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_DEEP_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_MASK (0x10U)
#define SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_SHIFT (4U)
/*! VDDCOREREG_LP - Vddcore regulator mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_VDDCOREREG_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_MASK     (0x40U)
#define SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_SHIFT    (6U)
/*! PMCREF_LP - Internal PMC references LP mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_PMCREF_LP(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMCREF_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_MASK     (0x80U)
#define SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_SHIFT    (7U)
/*! HVD1V8_PD - HVD
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HVD1V8_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_MASK    (0x100U)
#define SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_SHIFT   (8U)
/*! PORCORE_LP - Internal PMC references LP mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_PORCORE_LP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PORCORE_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_MASK    (0x200U)
#define SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_SHIFT   (9U)
/*! LVDCORE_LP - LVD
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_LVDCORE_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_MASK    (0x400U)
#define SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_SHIFT   (10U)
/*! HVDCORE_PD - HVD
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HVDCORE_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_RBB_PD_MASK        (0x800U)
#define SYSCTL0_PDRUNCFG0_SET_RBB_PD_SHIFT       (11U)
/*! RBB_PD - Reverse body-bias
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_RBB_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_RBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_RBB_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_FBB_PD_MASK        (0x1000U)
#define SYSCTL0_PDRUNCFG0_SET_FBB_PD_SHIFT       (12U)
/*! FBB_PD - Forward body-bias
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_FBB_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_FBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_FBB_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_MASK    (0x2000U)
#define SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_SHIFT   (13U)
/*! SYSXTAL_PD - Main crystal oscillator
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_SYSXTAL_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK      (0x4000U)
#define SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_SHIFT     (14U)
/*! LPOSC_PD - 1 MHz Low-Power oscillator
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_LPOSC_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_LPOSC_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_MASK    (0x8000U)
#define SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_SHIFT   (15U)
/*! RBBSRAM_PD - Reverse body-bias SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_RBBSRAM_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK       (0x10000U)
#define SYSCTL0_PDRUNCFG0_SET_FFRO_PD_SHIFT      (16U)
/*! FFRO_PD - FFRO 48/60 MHz internal oscillator
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_FFRO_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_FFRO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_FFRO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_MASK  (0x20000U)
#define SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_SHIFT (17U)
/*! SYSPLLLDO_PD - System PLL internal regulator
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_SYSPLLLDO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_MASK  (0x40000U)
#define SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_SHIFT (18U)
/*! SYSPLLANA_PD - System PLL analog functions
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_SYSPLLANA_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_MASK  (0x80000U)
#define SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_SHIFT (19U)
/*! AUDPLLLDO_PD - Audio PLL internal regulator
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_AUDPLLLDO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_MASK  (0x100000U)
#define SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_SHIFT (20U)
/*! AUDPLLANA_PD - Audio PLL analog functions
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_AUDPLLANA_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_ADC_PD_MASK        (0x200000U)
#define SYSCTL0_PDRUNCFG0_SET_ADC_PD_SHIFT       (21U)
/*! ADC_PD - ADC analog functions
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_ADC_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ADC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ADC_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_ADC_LP_MASK        (0x400000U)
#define SYSCTL0_PDRUNCFG0_SET_ADC_LP_SHIFT       (22U)
/*! ADC_LP - ADC low power mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_ADC_LP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ADC_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ADC_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_MASK (0x800000U)
#define SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_SHIFT (23U)
/*! ADC_TEMPSNS_PD - ADC temperature sensor
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ADC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_MASK (0x1000000U)
#define SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_SHIFT (24U)
/*! PMC_TEMPSNS_PD - PMC temperature sensor
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_PMC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_ACMP_PD_MASK       (0x2000000U)
#define SYSCTL0_PDRUNCFG0_SET_ACMP_PD_SHIFT      (25U)
/*! ACMP_PD - Analog comparator
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_ACMP_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_ACMP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_ACMP_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
/*! HSPAD_FSPI0_VDET_LP - High speed pad voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_SHIFT (27U)
/*! HSPAD_FSPI0_REF_PD - High speed pad FSPI0 voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI0_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_MASK  (0x10000000U)
#define SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_SHIFT (28U)
/*! HSPADVDET_LP - High speed pad FSPI0 voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPADVDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_MASK   (0x20000000U)
#define SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_SHIFT  (29U)
/*! HSPADREF_PD - High speed pad sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPADREF_PD_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
/*! HSPAD_FSPI1_VDET_LP - High speed pad FSPI1 voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_SHIFT (31U)
/*! HSPAD_FSPI1_REF_PD - High speed pad FSPI1 sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_SET_HSPAD_FSPI1_REF_PD_MASK)
/*! @} */

/*! @name PDRUNCFG1_SET - Run configuration 1 set */
/*! @{ */
#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_MASK   (0x1U)
#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_SHIFT  (0U)
/*! PQ_SRAM_APD - Array power for PowerQuad RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_MASK   (0x2U)
#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_SHIFT  (1U)
/*! PQ_SRAM_PPD - Periphery power for PowerQuad RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_PQ_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_MASK (0x4U)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_SHIFT (2U)
/*! FLEXSPI0_SRAM_APD - Array power for FLEXSPI0
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_MASK (0x8U)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_SHIFT (3U)
/*! FLEXSPI0_SRAM_PPD - Periphery power for FLEXSPI0
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI0_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_MASK (0x10U)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_SHIFT (4U)
/*! FLEXSPI1_SRAM_APD - Array power for FLEXSPI1
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK (0x20U)
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT (5U)
/*! FLEXSPI1_SRAM_PPD - Periphery power for FLEXSPI1
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_FLEXSPI1_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_MASK (0x40U)
#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_SHIFT (6U)
/*! USBHS_SRAM_APD - Array power for USB RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_MASK (0x80U)
#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_SHIFT (7U)
/*! USBHS_SRAM_PPD - Periphery power for USB RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USBHS_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_MASK (0x100U)
#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_SHIFT (8U)
/*! USDHC0_SRAM_APD - Array power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_MASK (0x200U)
#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_SHIFT (9U)
/*! USDHC0_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC0_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_MASK (0x400U)
#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_SHIFT (10U)
/*! USDHC1_SRAM_APD - Array power for uSDHC1 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_MASK (0x800U)
#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_SHIFT (11U)
/*! USDHC1_SRAM_PPD - Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_USDHC1_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_MASK (0x2000U)
#define SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_SHIFT (13U)
/*! CASPER_SRAM_PPD - Periphery power for Casper RAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_CASPER_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK  (0x4000U)
#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT (14U)
/*! GPU_SRAM_APD - Array power for GPU SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK  (0x8000U)
#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT (15U)
/*! GPU_SRAM_PPD - Periphery power for GPU SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_GPU_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_SHIFT (16U)
/*! SMARTDMA_SRAM_APD - Array power for SMARTDMA SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_SHIFT (17U)
/*! SMARTDMA_SRAM_PPD - Periphery power for SMARTDMA SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_SMARTDMA_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_MASK (0x40000U)
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_SHIFT (18U)
/*! MIPIDSI_SRAM_APD - Array power for MIPIDSI SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_MASK (0x80000U)
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_SHIFT (19U)
/*! MIPIDSI_SRAM_PPD - Periphery power for MIPIDSI SRAM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_MIPIDSI_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_MASK (0x100000U)
#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_SHIFT (20U)
/*! LCDIF_SRAM_APD - Array power for LCDIF
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_MASK (0x200000U)
#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_SHIFT (21U)
/*! LCDIF_SRAM_PPD - Periphery power for LCDIF
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_LCDIF_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_DSP_PD_MASK        (0x2000000U)
#define SYSCTL0_PDRUNCFG1_SET_DSP_PD_SHIFT       (25U)
/*! DSP_PD - Array and periphery power for DSP
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_DSP_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_DSP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_DSP_PD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_MASK    (0x4000000U)
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_SHIFT   (26U)
/*! MIPIDSI_PD - Array and periphery power for MIPIDSI
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_MIPIDSI_PD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_OTP_PD_MASK        (0x8000000U)
#define SYSCTL0_PDRUNCFG1_SET_OTP_PD_SHIFT       (27U)
/*! OTP_PD - Array and periphery power for OTP
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_OTP_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_OTP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_OTP_PD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_ROM_PD_MASK        (0x10000000U)
#define SYSCTL0_PDRUNCFG1_SET_ROM_PD_SHIFT       (28U)
/*! ROM_PD - Array and periphery power for ROM
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_ROM_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_ROM_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_ROM_PD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
/*! HSPAD_SDIO1_VDET_LP - High speed pad voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_SHIFT (30U)
/*! HSPAD_SDIO1_REF_PD - High speed pad sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_HSPAD_SDIO1_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_MASK    (0x80000000U)
#define SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_SHIFT   (31U)
/*! SRAM_SLEEP - SRAM sleep mode
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_SET_SRAM_SLEEP_MASK)
/*! @} */

/*! @name PDRUNCFG2_SET - Run configuration 2 set */
/*! @{ */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_MASK  (0x1U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_SHIFT (0U)
/*! SRAM_IF0_APD - Array power for SRAM interface 0.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF0_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_MASK  (0x2U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_SHIFT (1U)
/*! SRAM_IF1_APD - Array power for SRAM interface 1.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF1_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_MASK  (0x4U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_SHIFT (2U)
/*! SRAM_IF2_APD - Array power for SRAM interface 2.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF2_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_MASK  (0x8U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_SHIFT (3U)
/*! SRAM_IF3_APD - Array power for SRAM interface 3.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF3_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_MASK  (0x10U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_SHIFT (4U)
/*! SRAM_IF4_APD - Array power for SRAM interface 4.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF4_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_MASK  (0x20U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_SHIFT (5U)
/*! SRAM_IF5_APD - Array power for SRAM interface 5.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF5_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_MASK  (0x40U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_SHIFT (6U)
/*! SRAM_IF6_APD - Array power for SRAM interface 6.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF6_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_MASK  (0x80U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_SHIFT (7U)
/*! SRAM_IF7_APD - Array power for SRAM interface 7.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF7_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_MASK  (0x100U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_SHIFT (8U)
/*! SRAM_IF8_APD - Array power for SRAM interface 8.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF8_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_MASK  (0x200U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_SHIFT (9U)
/*! SRAM_IF9_APD - Array power for SRAM interface 9.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF9_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_MASK (0x400U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_SHIFT (10U)
/*! SRAM_IF10_APD - Array power for SRAM interface 10.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF10_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_MASK (0x800U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_SHIFT (11U)
/*! SRAM_IF11_APD - Array power for SRAM interface 11.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF11_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_MASK (0x1000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_SHIFT (12U)
/*! SRAM_IF12_APD - Array power for SRAM interface 12.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF12_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_MASK (0x2000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_SHIFT (13U)
/*! SRAM_IF13_APD - Array power for SRAM interface 13.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF13_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_MASK (0x4000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_SHIFT (14U)
/*! SRAM_IF14_APD - Array power for SRAM interface 14.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF14_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_MASK (0x8000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_SHIFT (15U)
/*! SRAM_IF15_APD - Array power for SRAM interface 15.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF15_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_SHIFT (16U)
/*! SRAM_IF16_APD - Array power for SRAM interface 16.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF16_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_SHIFT (17U)
/*! SRAM_IF17_APD - Array power for SRAM interface 17.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF17_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_MASK (0x40000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_SHIFT (18U)
/*! SRAM_IF18_APD - Array power for SRAM interface 18.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF18_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_MASK (0x80000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_SHIFT (19U)
/*! SRAM_IF19_APD - Array power for SRAM interface 19.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF19_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_MASK (0x100000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_SHIFT (20U)
/*! SRAM_IF20_APD - Array power for SRAM interface 20.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF20_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_MASK (0x200000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_SHIFT (21U)
/*! SRAM_IF21_APD - Array power for SRAM interface 21.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF21_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_MASK (0x400000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_SHIFT (22U)
/*! SRAM_IF22_APD - Array power for SRAM interface 22.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF22_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_MASK (0x800000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_SHIFT (23U)
/*! SRAM_IF23_APD - Array power for SRAM interface 23.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF23_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_MASK (0x1000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_SHIFT (24U)
/*! SRAM_IF24_APD - Array power for SRAM interface 24.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF24_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_MASK (0x2000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_SHIFT (25U)
/*! SRAM_IF25_APD - Array power for SRAM interface 25.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF25_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_SHIFT (26U)
/*! SRAM_IF26_APD - Array power for SRAM interface 26.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF26_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_SHIFT (27U)
/*! SRAM_IF27_APD - Array power for SRAM interface 27.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF27_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_MASK (0x10000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_SHIFT (28U)
/*! SRAM_IF28_APD - Array power for SRAM interface 28.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF28_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_SHIFT (29U)
/*! SRAM_IF29_APD - Array power for SRAM interface 29.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF29_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_SHIFT (30U)
/*! SRAM_IF30_APD - Array power for SRAM interface 30.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF30_APD_MASK)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_SHIFT (31U)
/*! SRAM_IF31_APD - Array power for SRAM interface 31.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_SET_SRAM_IF31_APD_MASK)
/*! @} */

/*! @name PDRUNCFG3_SET - Run configuration 3 set */
/*! @{ */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_MASK  (0x1U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_SHIFT (0U)
/*! SRAM_IF0_PPD - Periphery power for RAM interface 0.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF0_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_MASK  (0x2U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_SHIFT (1U)
/*! SRAM_IF1_PPD - Periphery power for RAM interface 1.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF1_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_MASK  (0x4U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_SHIFT (2U)
/*! SRAM_IF2_PPD - Periphery power for RAM interface 2.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF2_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_MASK  (0x8U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_SHIFT (3U)
/*! SRAM_IF3_PPD - Periphery power for RAM interface 3.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF3_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_MASK  (0x10U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_SHIFT (4U)
/*! SRAM_IF4_PPD - Periphery power for RAM interface 4.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF4_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_MASK  (0x20U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_SHIFT (5U)
/*! SRAM_IF5_PPD - Periphery power for RAM interface 5.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF5_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_MASK  (0x40U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_SHIFT (6U)
/*! SRAM_IF6_PPD - Periphery power for RAM interface 6.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF6_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_MASK  (0x80U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_SHIFT (7U)
/*! SRAM_IF7_PPD - Periphery power for RAM interface 7.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF7_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_MASK  (0x100U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_SHIFT (8U)
/*! SRAM_IF8_PPD - Periphery power for RAM interface 8.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF8_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_MASK  (0x200U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_SHIFT (9U)
/*! SRAM_IF9_PPD - Periphery power for RAM interface 9.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF9_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_MASK (0x400U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_SHIFT (10U)
/*! SRAM_IF10_PPD - Periphery power for RAM interface 10.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF10_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_MASK (0x800U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_SHIFT (11U)
/*! SRAM_IF11_PPD - Periphery power for RAM interface 11.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF11_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_MASK (0x1000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_SHIFT (12U)
/*! SRAM_IF12_PPD - Periphery power for RAM interface 12.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF12_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_MASK (0x2000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_SHIFT (13U)
/*! SRAM_IF13_PPD - Periphery power for RAM interface 13.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF13_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_MASK (0x4000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_SHIFT (14U)
/*! SRAM_IF14_PPD - Periphery power for RAM interface 14.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF14_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_MASK (0x8000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_SHIFT (15U)
/*! SRAM_IF15_PPD - Periphery power for RAM interface 15.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF15_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_SHIFT (16U)
/*! SRAM_IF16_PPD - Periphery power for RAM interface 16.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF16_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_SHIFT (17U)
/*! SRAM_IF17_PPD - Periphery power for RAM interface 17.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF17_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_MASK (0x40000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_SHIFT (18U)
/*! SRAM_IF18_PPD - Periphery power for RAM interface 18.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF18_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_MASK (0x80000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_SHIFT (19U)
/*! SRAM_IF19_PPD - Periphery power for RAM interface 19.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF19_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_MASK (0x100000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_SHIFT (20U)
/*! SRAM_IF20_PPD - Periphery power for RAM interface 20.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF20_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_MASK (0x200000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_SHIFT (21U)
/*! SRAM_IF21_PPD - Periphery power for RAM interface 21.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF21_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_MASK (0x400000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_SHIFT (22U)
/*! SRAM_IF22_PPD - Periphery power for RAM interface 22.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF22_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_MASK (0x800000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_SHIFT (23U)
/*! SRAM_IF23_PPD - Periphery power for RAM interface 23.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF23_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_MASK (0x1000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_SHIFT (24U)
/*! SRAM_IF24_PPD - Periphery power for RAM interface 24.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF24_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_MASK (0x2000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_SHIFT (25U)
/*! SRAM_IF25_PPD - Periphery power for RAM interface 25.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF25_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_SHIFT (26U)
/*! SRAM_IF26_PPD - Periphery power for RAM interface 26.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF26_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_SHIFT (27U)
/*! SRAM_IF27_PPD - Periphery power for RAM interface 27.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF27_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_MASK (0x10000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_SHIFT (28U)
/*! SRAM_IF28_PPD - Periphery power for RAM interface 28.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF28_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_SHIFT (29U)
/*! SRAM_IF29_PPD - Periphery power for RAM interface 29.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF29_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_SHIFT (30U)
/*! SRAM_IF30_PPD - Periphery power for RAM interface 30.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF30_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_SHIFT (31U)
/*! SRAM_IF31_PPD - Periphery power for RAM interface 31.
 *  0b0..No effect
 *  0b1..Sets the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_SET_SRAM_IF31_PPD_MASK)
/*! @} */

/*! @name PDRUNCFG0_CLR - Run configuration 0 clear */
/*! @{ */
#define SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_MASK (0x1U)
#define SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_SHIFT (0U)
/*! MAINCLK_SHUTOFF - Main clock shut off
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_MAINCLK_SHUTOFF_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_MASK    (0x2U)
#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_SHIFT   (1U)
/*! PMIC_MODE0 - PMIC_MODE0 device pin
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE0_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_MASK    (0x4U)
#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_SHIFT   (2U)
/*! PMIC_MODE1 - PMIC_MODE1 device pin
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMIC_MODE1_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_MASK       (0x8U)
#define SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_SHIFT      (3U)
/*! DEEP_PD - Deep power-down mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_DEEP_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_DEEP_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_MASK (0x10U)
#define SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_SHIFT (4U)
/*! VDDCOREREG_LP - Vddcore regulator mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_VDDCOREREG_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_MASK     (0x40U)
#define SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_SHIFT    (6U)
/*! PMCREF_LP - Internal PMC references LP mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMCREF_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_MASK     (0x80U)
#define SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_SHIFT    (7U)
/*! HVD1V8_PD - HVD
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HVD1V8_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_MASK    (0x100U)
#define SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_SHIFT   (8U)
/*! PORCORE_LP - LVD
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PORCORE_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_MASK    (0x200U)
#define SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_SHIFT   (9U)
/*! LVDCORE_LP - LVD
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_LVDCORE_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_MASK    (0x400U)
#define SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_SHIFT   (10U)
/*! HVDCORE_PD - HVD
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HVDCORE_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_RBB_PD_MASK        (0x800U)
#define SYSCTL0_PDRUNCFG0_CLR_RBB_PD_SHIFT       (11U)
/*! RBB_PD - Reverse body-bias
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_RBB_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_RBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_RBB_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_FBB_PD_MASK        (0x1000U)
#define SYSCTL0_PDRUNCFG0_CLR_FBB_PD_SHIFT       (12U)
/*! FBB_PD - Forward body-bias
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_FBB_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_FBB_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_FBB_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_MASK    (0x2000U)
#define SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_SHIFT   (13U)
/*! SYSXTAL_PD - Main crystal oscillator
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_SYSXTAL_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK      (0x4000U)
#define SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_SHIFT     (14U)
/*! LPOSC_PD - 1 MHz Low-Power oscillator
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_MASK    (0x8000U)
#define SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_SHIFT   (15U)
/*! RBBSRAM_PD - Reverse body-bias SRAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_RBBSRAM_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK       (0x10000U)
#define SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_SHIFT      (16U)
/*! FFRO_PD - SFRO 16 MHz internal oscillator
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_FFRO_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_MASK  (0x20000U)
#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_SHIFT (17U)
/*! SYSPLLLDO_PD - System PLL internal regulator
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_SYSPLLLDO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_MASK  (0x40000U)
#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_SHIFT (18U)
/*! SYSPLLANA_PD - System PLL analog functions
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_SYSPLLANA_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_MASK  (0x80000U)
#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_SHIFT (19U)
/*! AUDPLLLDO_PD - Audio PLL internal regulator
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_AUDPLLLDO_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_MASK  (0x100000U)
#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_SHIFT (20U)
/*! AUDPLLANA_PD - Audio PLL analog functions
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_AUDPLLANA_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_ADC_PD_MASK        (0x200000U)
#define SYSCTL0_PDRUNCFG0_CLR_ADC_PD_SHIFT       (21U)
/*! ADC_PD - ADC analog functions
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_ADC_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ADC_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ADC_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_ADC_LP_MASK        (0x400000U)
#define SYSCTL0_PDRUNCFG0_CLR_ADC_LP_SHIFT       (22U)
/*! ADC_LP - ADC low power mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_ADC_LP(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ADC_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ADC_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_MASK (0x800000U)
#define SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_SHIFT (23U)
/*! ADC_TEMPSNS_PD - ADC temperature sensor
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ADC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_MASK (0x1000000U)
#define SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_SHIFT (24U)
/*! PMC_TEMPSNS_PD - PMC temperature sensor
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_PMC_TEMPSNS_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_MASK       (0x2000000U)
#define SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_SHIFT      (25U)
/*! ACMP_PD - Analog comparator
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_ACMP_PD(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_ACMP_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_SHIFT (26U)
/*! HSPAD_FSPI0_VDET_LP - High speed pad FSPI0 voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_SHIFT (27U)
/*! HSPAD_FSPI0_REF_PD - High speed pad FSPIO0 sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI0_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_MASK  (0x10000000U)
#define SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_SHIFT (28U)
/*! HSPADVDET_LP - High speed pad voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPADVDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_MASK   (0x20000000U)
#define SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_SHIFT  (29U)
/*! HSPADREF_PD - High speed pad sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPADREF_PD_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_SHIFT (30U)
/*! HSPAD_FSPI1_VDET_LP - High speed pad FSPI1 voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_SHIFT (31U)
/*! HSPAD_FSPI1_REF_PD - High speed pad FSPIO1 sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG0 Bit
 */
#define SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG0_CLR_HSPAD_FSPI1_REF_PD_MASK)
/*! @} */

/*! @name PDRUNCFG1_CLR - Run configuration 1 clear */
/*! @{ */
#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK   (0x1U)
#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT  (0U)
/*! PQ_SRAM_APD - Array power for PowerQuad RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_MASK   (0x2U)
#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_SHIFT  (1U)
/*! PQ_SRAM_PPD - Periphery power for PowerQuad RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_PQ_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK (0x4U)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT (2U)
/*! FLEXSPI0_SRAM_APD - Array power for FlexSPI0
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_MASK (0x8U)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_SHIFT (3U)
/*! FLEXSPI0_SRAM_PPD - Periphery power for FlexSPI0
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI0_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK (0x10U)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT (4U)
/*! FLEXSPI1_SRAM_APD - Array power for FlexSPI1
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_MASK (0x20U)
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_SHIFT (5U)
/*! FLEXSPI1_SRAM_PPD - Periphery power for FlexSPI1
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_FLEXSPI1_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_MASK (0x40U)
#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_SHIFT (6U)
/*! USBHS_SRAM_APD - Array power for USB RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_MASK (0x80U)
#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_SHIFT (7U)
/*! USBHS_SRAM_PPD - Periphery power for USB RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USBHS_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_MASK (0x100U)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_SHIFT (8U)
/*! USDHC0_SRAM_APD - Array power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_MASK (0x200U)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_SHIFT (9U)
/*! USDHC0_SRAM_PPD - Periphery power for uSDHC0 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC0_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_MASK (0x400U)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_SHIFT (10U)
/*! USDHC1_SRAM_APD - Array power for uSDHC1 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_MASK (0x800U)
#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_SHIFT (11U)
/*! USDHC1_SRAM_PPD - Periphery power for uSDHC1 (SD/MMC/SDIO interface) RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_USDHC1_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_MASK (0x2000U)
#define SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_SHIFT (13U)
/*! CASPER_SRAM_PPD - Periphery power for Casper RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_CASPER_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_MASK  (0x4000U)
#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_SHIFT (14U)
/*! GPU_SRAM_APD - Array power for GPU SRAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_MASK  (0x8000U)
#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_SHIFT (15U)
/*! GPU_SRAM_PPD - Periphery power for GPU RAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_GPU_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_SHIFT (16U)
/*! SMARTDMA_SRAM_APD - Array power for SMARTDMA SRAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT (17U)
/*! SMARTDMA_SRAM_PPD - Periphery power for SMARTDMA SRAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SMARTDMA_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_MASK (0x40000U)
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_SHIFT (18U)
/*! MIPIDSI_SRAM_APD - Array power for MIPIDSI SRAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_MASK (0x80000U)
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_SHIFT (19U)
/*! MIPIDSI_SRAM_PPD - Periphery power for MIPIDSI SRAM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_MASK (0x100000U)
#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_SHIFT (20U)
/*! LCDIF_SRAM_APD - Array power for LCDIF
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_APD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_MASK (0x200000U)
#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_SHIFT (21U)
/*! LCDIF_SRAM_PPD - Periphery power for LCDIF
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_LCDIF_SRAM_PPD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_DSP_PD_MASK        (0x2000000U)
#define SYSCTL0_PDRUNCFG1_CLR_DSP_PD_SHIFT       (25U)
/*! DSP_PD - Array and periphery power for DSP
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_DSP_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_DSP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_DSP_PD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_MASK    (0x4000000U)
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_SHIFT   (26U)
/*! MIPIDSI_PD - Array and periphery power for MIPIDSI
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_MIPIDSI_PD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_OTP_PD_MASK        (0x8000000U)
#define SYSCTL0_PDRUNCFG1_CLR_OTP_PD_SHIFT       (27U)
/*! OTP_PD - Array and periphery power for OTP
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_OTP_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_OTP_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_OTP_PD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_ROM_PD_MASK        (0x10000000U)
#define SYSCTL0_PDRUNCFG1_CLR_ROM_PD_SHIFT       (28U)
/*! ROM_PD - Array and periphery power for ROM
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_ROM_PD(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_ROM_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_ROM_PD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_SHIFT (29U)
/*! HSPAD_SDIO1_VDET_LP - High speed pad voltage detect sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_VDET_LP_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_SHIFT (30U)
/*! HSPAD_SDIO1_REF_PD - High speed pad sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_HSPAD_SDIO1_REF_PD_MASK)
#define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK    (0x80000000U)
#define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT   (31U)
/*! SRAM_SLEEP - SRAM sleep mode
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG1 Bit
 */
#define SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_SHIFT)) & SYSCTL0_PDRUNCFG1_CLR_SRAM_SLEEP_MASK)
/*! @} */

/*! @name PDRUNCFG2_CLR - Run configuration 2 clear */
/*! @{ */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_MASK  (0x1U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_SHIFT (0U)
/*! SRAM_IF0_APD - Array power for RAM interface 0
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF0_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_MASK  (0x2U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_SHIFT (1U)
/*! SRAM_IF1_APD - Array power for RAM interface 1
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF1_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_MASK  (0x4U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_SHIFT (2U)
/*! SRAM_IF2_APD - Array power for RAM interface 2
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF2_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_MASK  (0x8U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_SHIFT (3U)
/*! SRAM_IF3_APD - Array power for RAM interface 3
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF3_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK  (0x10U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT (4U)
/*! SRAM_IF4_APD - Array power for RAM interface 4
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF4_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_MASK  (0x20U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_SHIFT (5U)
/*! SRAM_IF5_APD - Array power for RAM interface 5
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF5_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_MASK  (0x40U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_SHIFT (6U)
/*! SRAM_IF6_APD - Array power for RAM interface 6
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF6_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_MASK  (0x80U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_SHIFT (7U)
/*! SRAM_IF7_APD - Array power for RAM interface 7
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF7_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_MASK  (0x100U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_SHIFT (8U)
/*! SRAM_IF8_APD - Array power for RAM interface 8
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF8_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_MASK  (0x200U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_SHIFT (9U)
/*! SRAM_IF9_APD - Array power for RAM interface 9
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF9_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_MASK (0x400U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_SHIFT (10U)
/*! SRAM_IF10_APD - Array power for RAM interface 10
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF10_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_MASK (0x800U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_SHIFT (11U)
/*! SRAM_IF11_APD - Array power for RAM interface 11
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF11_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_MASK (0x1000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_SHIFT (12U)
/*! SRAM_IF12_APD - Array power for RAM interface 12
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF12_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_MASK (0x2000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_SHIFT (13U)
/*! SRAM_IF13_APD - Array power for RAM interface 13
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF13_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_MASK (0x4000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_SHIFT (14U)
/*! SRAM_IF14_APD - Array power for RAM interface 14
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF14_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_MASK (0x8000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_SHIFT (15U)
/*! SRAM_IF15_APD - Array power for RAM interface 15
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF15_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_SHIFT (16U)
/*! SRAM_IF16_APD - Array power for RAM interface 16
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF16_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_SHIFT (17U)
/*! SRAM_IF17_APD - Array power for RAM interface 17
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF17_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_MASK (0x40000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_SHIFT (18U)
/*! SRAM_IF18_APD - Array power for RAM interface 18
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF18_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_MASK (0x80000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_SHIFT (19U)
/*! SRAM_IF19_APD - Array power for RAM interface 19
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF19_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_MASK (0x100000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_SHIFT (20U)
/*! SRAM_IF20_APD - Array power for RAM interface 20
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF20_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_MASK (0x200000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_SHIFT (21U)
/*! SRAM_IF21_APD - Array power for RAM interface 21
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF21_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_MASK (0x400000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_SHIFT (22U)
/*! SRAM_IF22_APD - Array power for RAM interface 22
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF22_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_MASK (0x800000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_SHIFT (23U)
/*! SRAM_IF23_APD - Array power for RAM interface 23
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF23_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_MASK (0x1000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_SHIFT (24U)
/*! SRAM_IF24_APD - Array power for RAM interface 24
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF24_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_MASK (0x2000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_SHIFT (25U)
/*! SRAM_IF25_APD - Array power for RAM interface 25
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF25_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_SHIFT (26U)
/*! SRAM_IF26_APD - Array power for RAM interface 26
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF26_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_SHIFT (27U)
/*! SRAM_IF27_APD - Array power for RAM interface 27
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF27_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_MASK (0x10000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_SHIFT (28U)
/*! SRAM_IF28_APD - Array power for RAM interface 28
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF28_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_SHIFT (29U)
/*! SRAM_IF29_APD - Array power for RAM interface 29
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF29_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_SHIFT (30U)
/*! SRAM_IF30_APD - Array power for RAM interface 30
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF30_APD_MASK)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_SHIFT (31U)
/*! SRAM_IF31_APD - Array power for RAM interface 31
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG2 Bit
 */
#define SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_SHIFT)) & SYSCTL0_PDRUNCFG2_CLR_SRAM_IF31_APD_MASK)
/*! @} */

/*! @name PDRUNCFG3_CLR - Run configuration 3 clear */
/*! @{ */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_MASK  (0x1U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_SHIFT (0U)
/*! SRAM_IF0_PPD - Periphery power for RAM interface 0
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF0_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_MASK  (0x2U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_SHIFT (1U)
/*! SRAM_IF1_PPD - Periphery power for RAM interface 1
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF1_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_MASK  (0x4U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_SHIFT (2U)
/*! SRAM_IF2_PPD - Periphery power for RAM interface 2
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF2_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_MASK  (0x8U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_SHIFT (3U)
/*! SRAM_IF3_PPD - Periphery power for RAM interface 3
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF3_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_MASK  (0x10U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_SHIFT (4U)
/*! SRAM_IF4_PPD - Periphery power for RAM interface 4
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF4_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_MASK  (0x20U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_SHIFT (5U)
/*! SRAM_IF5_PPD - Periphery power for RAM interface 5
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF5_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_MASK  (0x40U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_SHIFT (6U)
/*! SRAM_IF6_PPD - Periphery power for RAM interface 6
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF6_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_MASK  (0x80U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_SHIFT (7U)
/*! SRAM_IF7_PPD - Periphery power for RAM interface 7
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF7_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_MASK  (0x100U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_SHIFT (8U)
/*! SRAM_IF8_PPD - Periphery power for RAM interface 8
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF8_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_MASK  (0x200U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_SHIFT (9U)
/*! SRAM_IF9_PPD - Periphery power for RAM interface 9
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF9_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_MASK (0x400U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_SHIFT (10U)
/*! SRAM_IF10_PPD - Periphery power for RAM interface 10
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF10_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_MASK (0x800U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_SHIFT (11U)
/*! SRAM_IF11_PPD - Periphery power for RAM interface 11
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF11_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_MASK (0x1000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_SHIFT (12U)
/*! SRAM_IF12_PPD - Periphery power for RAM interface 12
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF12_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_MASK (0x2000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_SHIFT (13U)
/*! SRAM_IF13_PPD - Periphery power for RAM interface 13
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF13_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_MASK (0x4000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_SHIFT (14U)
/*! SRAM_IF14_PPD - Periphery power for RAM interface 14
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF14_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_MASK (0x8000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_SHIFT (15U)
/*! SRAM_IF15_PPD - Periphery power for RAM interface 15
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF15_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_MASK (0x10000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_SHIFT (16U)
/*! SRAM_IF16_PPD - Periphery power for RAM interface 16
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF16_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_MASK (0x20000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_SHIFT (17U)
/*! SRAM_IF17_PPD - Periphery power for RAM interface 17
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF17_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_MASK (0x40000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_SHIFT (18U)
/*! SRAM_IF18_PPD - Periphery power for RAM interface 18
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF18_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_MASK (0x80000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_SHIFT (19U)
/*! SRAM_IF19_PPD - Periphery power for RAM interface 19
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF19_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_MASK (0x100000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_SHIFT (20U)
/*! SRAM_IF20_PPD - Periphery power for RAM interface 20
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF20_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_MASK (0x200000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_SHIFT (21U)
/*! SRAM_IF21_PPD - Periphery power for RAM interface 21
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF21_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_MASK (0x400000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_SHIFT (22U)
/*! SRAM_IF22_PPD - Periphery power for RAM interface 22
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF22_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_MASK (0x800000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_SHIFT (23U)
/*! SRAM_IF23_PPD - Periphery power for RAM interface 23
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF23_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_MASK (0x1000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_SHIFT (24U)
/*! SRAM_IF24_PPD - Periphery power for RAM interface 24
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF24_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_MASK (0x2000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_SHIFT (25U)
/*! SRAM_IF25_PPD - Periphery power for RAM interface 25
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF25_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_MASK (0x4000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_SHIFT (26U)
/*! SRAM_IF26_PPD - Periphery power for RAM interface 26
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF26_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_MASK (0x8000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_SHIFT (27U)
/*! SRAM_IF27_PPD - Periphery power for RAM interface 27
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF27_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_MASK (0x10000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_SHIFT (28U)
/*! SRAM_IF28_PPD - Periphery power for RAM interface 28
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF28_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_MASK (0x20000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_SHIFT (29U)
/*! SRAM_IF29_PPD - Periphery power for RAM interface 29
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF29_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_MASK (0x40000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_SHIFT (30U)
/*! SRAM_IF30_PPD - Periphery power for RAM interface 30
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF30_PPD_MASK)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_MASK (0x80000000U)
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_SHIFT (31U)
/*! SRAM_IF31_PPD - Periphery power for RAM interface 31
 *  0b0..No effect
 *  0b1..Clears the PDRUNCFG3 Bit
 */
#define SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_SHIFT)) & SYSCTL0_PDRUNCFG3_CLR_SRAM_IF31_PPD_MASK)
/*! @} */

/*! @name PDWAKECFG - PD Wake Configuration */
/*! @{ */
#define SYSCTL0_PDWAKECFG_RBBKEEPST_MASK         (0x1U)
#define SYSCTL0_PDWAKECFG_RBBKEEPST_SHIFT        (0U)
/*! RBBKEEPST - RBB mode on wakeup
 *  0b0..Use value of RBB_PD in PDRUNCFG on wakeup.
 *  0b1..Copy PDSLEEPCFG RBB_PD value to PDRUNCFG RBB_PD on wakeup to keep RBB state.
 */
#define SYSCTL0_PDWAKECFG_RBBKEEPST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_RBBKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_RBBKEEPST_MASK)
#define SYSCTL0_PDWAKECFG_FBBKEEPST_MASK         (0x2U)
#define SYSCTL0_PDWAKECFG_FBBKEEPST_SHIFT        (1U)
/*! FBBKEEPST - FBB mode on wakeup
 *  0b0..Use value of FBB_PD in PDRUNCFG on wakeup
 *  0b1..Copy PDSLEEPCFG FBB_PD value to PDRUNCFG FBB_PD on wakeup to keep FBB state
 */
#define SYSCTL0_PDWAKECFG_FBBKEEPST(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_FBBKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_FBBKEEPST_MASK)
#define SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_MASK     (0x4U)
#define SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_SHIFT    (2U)
/*! RBBSRAMKEEPST - RBB SRAM mode on wakeup
 *  0b0..Use value of RBBSRAM_PD in PDRUNCFG on wakeup
 *  0b1..Copy PDSLEEPCFG RBBSRAM_PD value to PDRUNCFG RBBSRAM_PD on wakeupto keep RBB state
 */
#define SYSCTL0_PDWAKECFG_RBBSRAMKEEPST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_RBBSRAMKEEPST_MASK)
#define SYSCTL0_PDWAKECFG_MIPIPDKEEPST_MASK      (0x8U)
#define SYSCTL0_PDWAKECFG_MIPIPDKEEPST_SHIFT     (3U)
/*! MIPIPDKEEPST - MIPI_PD value on wakeup
 *  0b0..Use value of MIPI_PD in PDRUNCFG on wakeup
 *  0b1..Copy PDSLEEPCFG MIPI_PD value to PDRUNCFG MIPI_PD on wakeupto keep MIPI state
 */
#define SYSCTL0_PDWAKECFG_MIPIPDKEEPST(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_MIPIPDKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_MIPIPDKEEPST_MASK)
#define SYSCTL0_PDWAKECFG_DSPPDKEEPST_MASK       (0x10U)
#define SYSCTL0_PDWAKECFG_DSPPDKEEPST_SHIFT      (4U)
/*! DSPPDKEEPST - DSP_PD value on wakeup
 *  0b0..Use value of DSP_PD in PDRUNCFG on wakeup
 *  0b1..Copy PDSLEEPCFG DSP_PD value to PDRUNCFG DSP_PD on wakeupto keep DSP state
 */
#define SYSCTL0_PDWAKECFG_DSPPDKEEPST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_DSPPDKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_DSPPDKEEPST_MASK)
#define SYSCTL0_PDWAKECFG_OTPPDKEEPST_MASK       (0x20U)
#define SYSCTL0_PDWAKECFG_OTPPDKEEPST_SHIFT      (5U)
/*! OTPPDKEEPST - OTP_PD value on wakeup
 *  0b0..Use value of OTP_PD in PDRUNCFG on wakeup
 *  0b1..Copy PDSLEEPCFG OTP_PD value to PDRUNCFG OTP_PD on wakeupto keep OTP state
 */
#define SYSCTL0_PDWAKECFG_OTPPDKEEPST(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_PDWAKECFG_OTPPDKEEPST_SHIFT)) & SYSCTL0_PDWAKECFG_OTPPDKEEPST_MASK)
/*! @} */

/*! @name STARTEN0 - Start Enable 0 */
/*! @{ */
#define SYSCTL0_STARTEN0_WDT0_MASK               (0x1U)
#define SYSCTL0_STARTEN0_WDT0_SHIFT              (0U)
/*! WDT0 - Watchdog timer 0 wake-up. 0x0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_WDT0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_WDT0_SHIFT)) & SYSCTL0_STARTEN0_WDT0_MASK)
#define SYSCTL0_STARTEN0_DMAC0_MASK              (0x2U)
#define SYSCTL0_STARTEN0_DMAC0_SHIFT             (1U)
/*! DMAC0 - DMA controller 0 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_DMAC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_DMAC0_SHIFT)) & SYSCTL0_STARTEN0_DMAC0_MASK)
#define SYSCTL0_STARTEN0_NSHSGPIO_INT0_MASK      (0x4U)
#define SYSCTL0_STARTEN0_NSHSGPIO_INT0_SHIFT     (2U)
/*! NSHSGPIO_INT0 - Non-secure GPIO interrupt A wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_NSHSGPIO_INT0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_NSHSGPIO_INT0_SHIFT)) & SYSCTL0_STARTEN0_NSHSGPIO_INT0_MASK)
#define SYSCTL0_STARTEN0_NSHSGPIO_INT1_MASK      (0x8U)
#define SYSCTL0_STARTEN0_NSHSGPIO_INT1_SHIFT     (3U)
/*! NSHSGPIO_INT1 - Non-secure GPIO interrupt B wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_NSHSGPIO_INT1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_NSHSGPIO_INT1_SHIFT)) & SYSCTL0_STARTEN0_NSHSGPIO_INT1_MASK)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_MASK     (0x10U)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_SHIFT    (4U)
/*! GPIO_INT0_IRQ0 - GPIO pin interrupt 0 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ0_MASK)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_MASK     (0x20U)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_SHIFT    (5U)
/*! GPIO_INT0_IRQ1 - GPIO pin interrupt 1 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ1_MASK)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_MASK     (0x40U)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_SHIFT    (6U)
/*! GPIO_INT0_IRQ2 - GPIO pin interrupt 2 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ2_MASK)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_MASK     (0x80U)
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_SHIFT    (7U)
/*! GPIO_INT0_IRQ3 - GPIO pin interrupt 3 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_GPIO_INT0_IRQ3(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_SHIFT)) & SYSCTL0_STARTEN0_GPIO_INT0_IRQ3_MASK)
#define SYSCTL0_STARTEN0_UTICK0_MASK             (0x100U)
#define SYSCTL0_STARTEN0_UTICK0_SHIFT            (8U)
/*! UTICK0 - UTICK wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_UTICK0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_UTICK0_SHIFT)) & SYSCTL0_STARTEN0_UTICK0_MASK)
#define SYSCTL0_STARTEN0_MRT0_MASK               (0x200U)
#define SYSCTL0_STARTEN0_MRT0_SHIFT              (9U)
/*! MRT0 - MRT wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_MRT0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_MRT0_SHIFT)) & SYSCTL0_STARTEN0_MRT0_MASK)
#define SYSCTL0_STARTEN0_CT32BIT0_MASK           (0x400U)
#define SYSCTL0_STARTEN0_CT32BIT0_SHIFT          (10U)
/*! CT32BIT0 - CTIMER 0 wake-up
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_CT32BIT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CT32BIT0_SHIFT)) & SYSCTL0_STARTEN0_CT32BIT0_MASK)
#define SYSCTL0_STARTEN0_CT32BIT1_MASK           (0x800U)
#define SYSCTL0_STARTEN0_CT32BIT1_SHIFT          (11U)
/*! CT32BIT1 - CTIMER 1 wake-up
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_CT32BIT1(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CT32BIT1_SHIFT)) & SYSCTL0_STARTEN0_CT32BIT1_MASK)
#define SYSCTL0_STARTEN0_SCT0_MASK               (0x1000U)
#define SYSCTL0_STARTEN0_SCT0_SHIFT              (12U)
/*! SCT0 - SCTimer/PWM wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_SCT0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SCT0_SHIFT)) & SYSCTL0_STARTEN0_SCT0_MASK)
#define SYSCTL0_STARTEN0_CT32BIT3_MASK           (0x2000U)
#define SYSCTL0_STARTEN0_CT32BIT3_SHIFT          (13U)
/*! CT32BIT3 - CTIMER 3 wake-up
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_CT32BIT3(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CT32BIT3_SHIFT)) & SYSCTL0_STARTEN0_CT32BIT3_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM0_MASK          (0x4000U)
#define SYSCTL0_STARTEN0_FLEXCOMM0_SHIFT         (14U)
/*! FLEXCOMM0 - Flexcomm 0 peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM0_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM0_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM1_MASK          (0x8000U)
#define SYSCTL0_STARTEN0_FLEXCOMM1_SHIFT         (15U)
/*! FLEXCOMM1 - Flexcomm 1 peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM1_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM1_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM2_MASK          (0x10000U)
#define SYSCTL0_STARTEN0_FLEXCOMM2_SHIFT         (16U)
/*! FLEXCOMM2 - Flexcomm 2 peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM2(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM2_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM2_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM3_MASK          (0x20000U)
#define SYSCTL0_STARTEN0_FLEXCOMM3_SHIFT         (17U)
/*! FLEXCOMM3 - Flexcomm 3 peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM3(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM3_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM3_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM4_MASK          (0x40000U)
#define SYSCTL0_STARTEN0_FLEXCOMM4_SHIFT         (18U)
/*! FLEXCOMM4 - Flexcomm 4 peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM4(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM4_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM4_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM5_MASK          (0x80000U)
#define SYSCTL0_STARTEN0_FLEXCOMM5_SHIFT         (19U)
/*! FLEXCOMM5 - Flexcomm 5 peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM5(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM5_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM5_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM14_MASK         (0x100000U)
#define SYSCTL0_STARTEN0_FLEXCOMM14_SHIFT        (20U)
/*! FLEXCOMM14 - Flexcomm 14 (High Speed SPI) peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM14(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM14_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM14_MASK)
#define SYSCTL0_STARTEN0_FLEXCOMM15_MASK         (0x200000U)
#define SYSCTL0_STARTEN0_FLEXCOMM15_SHIFT        (21U)
/*! FLEXCOMM15 - Flexcomm 15 (PMIC I2C) peripheral interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_FLEXCOMM15(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_FLEXCOMM15_SHIFT)) & SYSCTL0_STARTEN0_FLEXCOMM15_MASK)
#define SYSCTL0_STARTEN0_ADC0_MASK               (0x400000U)
#define SYSCTL0_STARTEN0_ADC0_SHIFT              (22U)
/*! ADC0 - ADC wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_ADC0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_ADC0_SHIFT)) & SYSCTL0_STARTEN0_ADC0_MASK)
#define SYSCTL0_STARTEN0_ACMP_MASK               (0x1000000U)
#define SYSCTL0_STARTEN0_ACMP_SHIFT              (24U)
/*! ACMP - ACMP wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_ACMP(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_ACMP_SHIFT)) & SYSCTL0_STARTEN0_ACMP_MASK)
#define SYSCTL0_STARTEN0_DMIC0_MASK              (0x2000000U)
#define SYSCTL0_STARTEN0_DMIC0_SHIFT             (25U)
/*! DMIC0 - DMIC wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_DMIC0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_DMIC0_SHIFT)) & SYSCTL0_STARTEN0_DMIC0_MASK)
#define SYSCTL0_STARTEN0_HYPERVISOR_MASK         (0x8000000U)
#define SYSCTL0_STARTEN0_HYPERVISOR_SHIFT        (27U)
/*! HYPERVISOR - Hypervisor interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_HYPERVISOR(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_HYPERVISOR_SHIFT)) & SYSCTL0_STARTEN0_HYPERVISOR_MASK)
#define SYSCTL0_STARTEN0_SECUREVIOLATION_MASK    (0x10000000U)
#define SYSCTL0_STARTEN0_SECUREVIOLATION_SHIFT   (28U)
/*! SECUREVIOLATION - Secure Violation wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_SECUREVIOLATION(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SECUREVIOLATION_SHIFT)) & SYSCTL0_STARTEN0_SECUREVIOLATION_MASK)
#define SYSCTL0_STARTEN0_HWVAD0_MASK             (0x20000000U)
#define SYSCTL0_STARTEN0_HWVAD0_SHIFT            (29U)
/*! HWVAD0 - Hardware VAD wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_HWVAD0(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_HWVAD0_SHIFT)) & SYSCTL0_STARTEN0_HWVAD0_MASK)
#define SYSCTL0_STARTEN0_PMC_MASK                (0x40000000U)
#define SYSCTL0_STARTEN0_PMC_SHIFT               (30U)
/*! PMC - PMC wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_PMC(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_PMC_SHIFT)) & SYSCTL0_STARTEN0_PMC_MASK)
#define SYSCTL0_STARTEN0_RNG_MASK                (0x80000000U)
#define SYSCTL0_STARTEN0_RNG_SHIFT               (31U)
/*! RNG - RNG wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN0_RNG(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_RNG_SHIFT)) & SYSCTL0_STARTEN0_RNG_MASK)
/*! @} */

/*! @name STARTEN1 - Start Enable 1 */
/*! @{ */
#define SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_MASK   (0x1U)
#define SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_SHIFT  (0U)
/*! RTC_LITE0_WAKEUP - RTC wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_SHIFT)) & SYSCTL0_STARTEN1_RTC_LITE0_WAKEUP_MASK)
#define SYSCTL0_STARTEN1_MU_MASK                 (0x4U)
#define SYSCTL0_STARTEN1_MU_SHIFT                (2U)
/*! MU - Message Unit wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_MU(x)                   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_MU_SHIFT)) & SYSCTL0_STARTEN1_MU_MASK)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_MASK     (0x8U)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_SHIFT    (3U)
/*! GPIO_INT0_IRQ4 - GPIO pin interrupt 4 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ4(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ4_MASK)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_MASK     (0x10U)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_SHIFT    (4U)
/*! GPIO_INT0_IRQ5 - GPIO pin interrupt 5 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ5(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ5_MASK)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_MASK     (0x20U)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_SHIFT    (5U)
/*! GPIO_INT0_IRQ6 - GPIO pin interrupt 6 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ6(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ6_MASK)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_MASK     (0x40U)
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_SHIFT    (6U)
/*! GPIO_INT0_IRQ7 - GPIO pin interrupt 7 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_GPIO_INT0_IRQ7(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_SHIFT)) & SYSCTL0_STARTEN1_GPIO_INT0_IRQ7_MASK)
#define SYSCTL0_STARTEN1_CT32BIT2_MASK           (0x80U)
#define SYSCTL0_STARTEN1_CT32BIT2_SHIFT          (7U)
/*! CT32BIT2 - CTIMER 2 wake-up
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_CT32BIT2(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CT32BIT2_SHIFT)) & SYSCTL0_STARTEN1_CT32BIT2_MASK)
#define SYSCTL0_STARTEN1_CT32BIT4_MASK           (0x100U)
#define SYSCTL0_STARTEN1_CT32BIT4_SHIFT          (8U)
/*! CT32BIT4 - CTIMER 4 wake-up
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_CT32BIT4(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CT32BIT4_SHIFT)) & SYSCTL0_STARTEN1_CT32BIT4_MASK)
#define SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_MASK  (0x200U)
#define SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_SHIFT (9U)
/*! OS_EVENT_TIMER_WU - OS Event Timer wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_SHIFT)) & SYSCTL0_STARTEN1_OS_EVENT_TIMER_WU_MASK)
#define SYSCTL0_STARTEN1_FLEXSPI_MASK            (0x400U)
#define SYSCTL0_STARTEN1_FLEXSPI_SHIFT           (10U)
/*! FLEXSPI - Quad/octal SPI wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_FLEXSPI(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXSPI_SHIFT)) & SYSCTL0_STARTEN1_FLEXSPI_MASK)
#define SYSCTL0_STARTEN1_FLEXCOMM6_MASK          (0x800U)
#define SYSCTL0_STARTEN1_FLEXCOMM6_SHIFT         (11U)
/*! FLEXCOMM6 - FLEXCOMM 6 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_FLEXCOMM6(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM6_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM6_MASK)
#define SYSCTL0_STARTEN1_FLEXCOMM7_MASK          (0x1000U)
#define SYSCTL0_STARTEN1_FLEXCOMM7_SHIFT         (12U)
/*! FLEXCOMM7 - FLEXCOMM 7 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_FLEXCOMM7(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_FLEXCOMM7_SHIFT)) & SYSCTL0_STARTEN1_FLEXCOMM7_MASK)
#define SYSCTL0_STARTEN1_SDIO0_MASK              (0x2000U)
#define SYSCTL0_STARTEN1_SDIO0_SHIFT             (13U)
/*! SDIO0 - SDIO0 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_SDIO0(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SDIO0_SHIFT)) & SYSCTL0_STARTEN1_SDIO0_MASK)
#define SYSCTL0_STARTEN1_SDIO1_MASK              (0x4000U)
#define SYSCTL0_STARTEN1_SDIO1_SHIFT             (14U)
/*! SDIO1 - SDIO0 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_SDIO1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SDIO1_SHIFT)) & SYSCTL0_STARTEN1_SDIO1_MASK)
#define SYSCTL0_STARTEN1_SHSGPIO_INT0_MASK       (0x8000U)
#define SYSCTL0_STARTEN1_SHSGPIO_INT0_SHIFT      (15U)
/*! SHSGPIO_INT0 - Secure GPIO interrupt A wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_SHSGPIO_INT0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SHSGPIO_INT0_SHIFT)) & SYSCTL0_STARTEN1_SHSGPIO_INT0_MASK)
#define SYSCTL0_STARTEN1_SHSGPIO_INT1_MASK       (0x10000U)
#define SYSCTL0_STARTEN1_SHSGPIO_INT1_SHIFT      (16U)
/*! SHSGPIO_INT1 - Secure GPIO interrupt B wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_SHSGPIO_INT1(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SHSGPIO_INT1_SHIFT)) & SYSCTL0_STARTEN1_SHSGPIO_INT1_MASK)
#define SYSCTL0_STARTEN1_I3C0_MASK               (0x20000U)
#define SYSCTL0_STARTEN1_I3C0_SHIFT              (17U)
/*! I3C0 - I3C wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_I3C0(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_I3C0_SHIFT)) & SYSCTL0_STARTEN1_I3C0_MASK)
#define SYSCTL0_STARTEN1_USB0_IRQ_MASK           (0x40000U)
#define SYSCTL0_STARTEN1_USB0_IRQ_SHIFT          (18U)
/*! USB0_IRQ - USB device/host interrupt wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_USB0_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_USB0_IRQ_SHIFT)) & SYSCTL0_STARTEN1_USB0_IRQ_MASK)
#define SYSCTL0_STARTEN1_USB0_NEEDCLK_MASK       (0x80000U)
#define SYSCTL0_STARTEN1_USB0_NEEDCLK_SHIFT      (19U)
/*! USB0_NEEDCLK - USB activity wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_USB0_NEEDCLK(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_USB0_NEEDCLK_SHIFT)) & SYSCTL0_STARTEN1_USB0_NEEDCLK_MASK)
#define SYSCTL0_STARTEN1_DMAC1_MASK              (0x400000U)
#define SYSCTL0_STARTEN1_DMAC1_SHIFT             (22U)
/*! DMAC1 - DMA controller 1 wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_DMAC1(x)                (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_DMAC1_SHIFT)) & SYSCTL0_STARTEN1_DMAC1_MASK)
#define SYSCTL0_STARTEN1_PUF_MASK                (0x800000U)
#define SYSCTL0_STARTEN1_PUF_SHIFT               (23U)
/*! PUF - PUF wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_PUF(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_PUF_SHIFT)) & SYSCTL0_STARTEN1_PUF_MASK)
#define SYSCTL0_STARTEN1_POWERQUAD_MASK          (0x1000000U)
#define SYSCTL0_STARTEN1_POWERQUAD_SHIFT         (24U)
/*! POWERQUAD - POWERQUAD co-processor wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_POWERQUAD(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_POWERQUAD_SHIFT)) & SYSCTL0_STARTEN1_POWERQUAD_MASK)
#define SYSCTL0_STARTEN1_CASPER_MASK             (0x2000000U)
#define SYSCTL0_STARTEN1_CASPER_SHIFT            (25U)
/*! CASPER - CASPER co-processor wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_CASPER(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CASPER_SHIFT)) & SYSCTL0_STARTEN1_CASPER_MASK)
#define SYSCTL0_STARTEN1_PMIC_MASK               (0x4000000U)
#define SYSCTL0_STARTEN1_PMIC_SHIFT              (26U)
/*! PMIC - Wake-up from on-chip PMC or off-chip PMIC.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_PMIC(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_PMIC_SHIFT)) & SYSCTL0_STARTEN1_PMIC_MASK)
#define SYSCTL0_STARTEN1_SHA_MASK                (0x8000000U)
#define SYSCTL0_STARTEN1_SHA_SHIFT               (27U)
/*! SHA - Hash-AES wake-up.
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define SYSCTL0_STARTEN1_SHA(x)                  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SHA_SHIFT)) & SYSCTL0_STARTEN1_SHA_MASK)
/*! @} */

/*! @name STARTEN0_SET - Start Enable 0 Set */
/*! @{ */
#define SYSCTL0_STARTEN0_SET_WDT0_MASK           (0x1U)
#define SYSCTL0_STARTEN0_SET_WDT0_SHIFT          (0U)
/*! WDT0 - Watchdog timer 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_WDT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_WDT0_SHIFT)) & SYSCTL0_STARTEN0_SET_WDT0_MASK)
#define SYSCTL0_STARTEN0_SET_DMAC0_MASK          (0x2U)
#define SYSCTL0_STARTEN0_SET_DMAC0_SHIFT         (1U)
/*! DMAC0 - DMA controller 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_DMAC0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_DMAC0_SHIFT)) & SYSCTL0_STARTEN0_SET_DMAC0_MASK)
#define SYSCTL0_STARTEN0_SET_NSHSGPIO_INT0_MASK  (0x4U)
#define SYSCTL0_STARTEN0_SET_NSHSGPIO_INT0_SHIFT (2U)
/*! NSHSGPIO_INT0 - Non-secure GPIO interrupt A wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_NSHSGPIO_INT0(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_NSHSGPIO_INT0_SHIFT)) & SYSCTL0_STARTEN0_SET_NSHSGPIO_INT0_MASK)
#define SYSCTL0_STARTEN0_SET_NSHSGPIO_INT1_MASK  (0x8U)
#define SYSCTL0_STARTEN0_SET_NSHSGPIO_INT1_SHIFT (3U)
/*! NSHSGPIO_INT1 - Non-secure GPIO interrupt B wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_NSHSGPIO_INT1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_NSHSGPIO_INT1_SHIFT)) & SYSCTL0_STARTEN0_SET_NSHSGPIO_INT1_MASK)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_MASK (0x10U)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_SHIFT (4U)
/*! GPIO_INT0_IRQ0 - GPIO pin interrupt 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ0_MASK)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_MASK (0x20U)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_SHIFT (5U)
/*! GPIO_INT0_IRQ1 - GPIO pin interrupt 1 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ1_MASK)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_MASK (0x40U)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_SHIFT (6U)
/*! GPIO_INT0_IRQ2 - GPIO pin interrupt 2 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ2_MASK)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_MASK (0x80U)
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_SHIFT (7U)
/*! GPIO_INT0_IRQ3 - GPIO pin interrupt 3 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_SHIFT)) & SYSCTL0_STARTEN0_SET_GPIO_INT0_IRQ3_MASK)
#define SYSCTL0_STARTEN0_SET_UTICK0_MASK         (0x100U)
#define SYSCTL0_STARTEN0_SET_UTICK0_SHIFT        (8U)
/*! UTICK0 - UTICK wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_UTICK0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_UTICK0_SHIFT)) & SYSCTL0_STARTEN0_SET_UTICK0_MASK)
#define SYSCTL0_STARTEN0_SET_MRT0_MASK           (0x200U)
#define SYSCTL0_STARTEN0_SET_MRT0_SHIFT          (9U)
/*! MRT0 - MRT wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_MRT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_MRT0_SHIFT)) & SYSCTL0_STARTEN0_SET_MRT0_MASK)
#define SYSCTL0_STARTEN0_SET_CT32BIT0_MASK       (0x400U)
#define SYSCTL0_STARTEN0_SET_CT32BIT0_SHIFT      (10U)
/*! CT32BIT0 - CTIMER 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_CT32BIT0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_CT32BIT0_SHIFT)) & SYSCTL0_STARTEN0_SET_CT32BIT0_MASK)
#define SYSCTL0_STARTEN0_SET_CT32BIT1_MASK       (0x800U)
#define SYSCTL0_STARTEN0_SET_CT32BIT1_SHIFT      (11U)
/*! CT32BIT1 - CTIMER 1 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_CT32BIT1(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_CT32BIT1_SHIFT)) & SYSCTL0_STARTEN0_SET_CT32BIT1_MASK)
#define SYSCTL0_STARTEN0_SET_SCT0_MASK           (0x1000U)
#define SYSCTL0_STARTEN0_SET_SCT0_SHIFT          (12U)
/*! SCT0 - SCTimer/PWM wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_SCT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_SCT0_SHIFT)) & SYSCTL0_STARTEN0_SET_SCT0_MASK)
#define SYSCTL0_STARTEN0_SET_CT32BIT3_MASK       (0x2000U)
#define SYSCTL0_STARTEN0_SET_CT32BIT3_SHIFT      (13U)
/*! CT32BIT3 - CTIMER 3 wake-up
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_CT32BIT3(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_CT32BIT3_SHIFT)) & SYSCTL0_STARTEN0_SET_CT32BIT3_MASK)
#define SYSCTL0_STARTEN0_SET_FLEXCOMM14_MASK     (0x100000U)
#define SYSCTL0_STARTEN0_SET_FLEXCOMM14_SHIFT    (20U)
/*! FLEXCOMM14 - Flexcomm 14 (High Speed SPI) peripheral interrupt wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_FLEXCOMM14(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_FLEXCOMM14_SHIFT)) & SYSCTL0_STARTEN0_SET_FLEXCOMM14_MASK)
#define SYSCTL0_STARTEN0_SET_FLEXCOMM15_MASK     (0x200000U)
#define SYSCTL0_STARTEN0_SET_FLEXCOMM15_SHIFT    (21U)
/*! FLEXCOMM15 - Flexcomm 15 (PMIC I2C) peripheral interrupt wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_FLEXCOMM15(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_FLEXCOMM15_SHIFT)) & SYSCTL0_STARTEN0_SET_FLEXCOMM15_MASK)
#define SYSCTL0_STARTEN0_SET_ADC0_MASK           (0x400000U)
#define SYSCTL0_STARTEN0_SET_ADC0_SHIFT          (22U)
/*! ADC0 - ADC wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_ADC0_SHIFT)) & SYSCTL0_STARTEN0_SET_ADC0_MASK)
#define SYSCTL0_STARTEN0_SET_ACMP_MASK           (0x1000000U)
#define SYSCTL0_STARTEN0_SET_ACMP_SHIFT          (24U)
/*! ACMP - ACMP wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_ACMP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_ACMP_SHIFT)) & SYSCTL0_STARTEN0_SET_ACMP_MASK)
#define SYSCTL0_STARTEN0_SET_DMIC0_MASK          (0x2000000U)
#define SYSCTL0_STARTEN0_SET_DMIC0_SHIFT         (25U)
/*! DMIC0 - DMIC wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_DMIC0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_DMIC0_SHIFT)) & SYSCTL0_STARTEN0_SET_DMIC0_MASK)
#define SYSCTL0_STARTEN0_SET_HYPERVISOR_MASK     (0x8000000U)
#define SYSCTL0_STARTEN0_SET_HYPERVISOR_SHIFT    (27U)
/*! HYPERVISOR - Hypervisor interrupt wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_HYPERVISOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_HYPERVISOR_SHIFT)) & SYSCTL0_STARTEN0_SET_HYPERVISOR_MASK)
#define SYSCTL0_STARTEN0_SET_SECUREVIOLATION_MASK (0x10000000U)
#define SYSCTL0_STARTEN0_SET_SECUREVIOLATION_SHIFT (28U)
/*! SECUREVIOLATION - Secure Violation wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_SECUREVIOLATION(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_SECUREVIOLATION_SHIFT)) & SYSCTL0_STARTEN0_SET_SECUREVIOLATION_MASK)
#define SYSCTL0_STARTEN0_SET_HWVAD0_MASK         (0x20000000U)
#define SYSCTL0_STARTEN0_SET_HWVAD0_SHIFT        (29U)
/*! HWVAD0 - Hardware VAD wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_HWVAD0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_HWVAD0_SHIFT)) & SYSCTL0_STARTEN0_SET_HWVAD0_MASK)
#define SYSCTL0_STARTEN0_SET_PMC_MASK            (0x40000000U)
#define SYSCTL0_STARTEN0_SET_PMC_SHIFT           (30U)
/*! PMC - PMC wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_PMC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_PMC_SHIFT)) & SYSCTL0_STARTEN0_SET_PMC_MASK)
#define SYSCTL0_STARTEN0_SET_RNG_MASK            (0x80000000U)
#define SYSCTL0_STARTEN0_SET_RNG_SHIFT           (31U)
/*! RNG - RNG wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_SET_RNG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_SET_RNG_SHIFT)) & SYSCTL0_STARTEN0_SET_RNG_MASK)
/*! @} */

/*! @name STARTEN1_SET - Start Enable 1 Set */
/*! @{ */
#define SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_MASK (0x1U)
#define SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_SHIFT (0U)
/*! RTC_LITE0_WAKEUP - RTC wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_SHIFT)) & SYSCTL0_STARTEN1_SET_RTC_LITE0_WAKEUP_MASK)
#define SYSCTL0_STARTEN1_SET_MU_MASK             (0x4U)
#define SYSCTL0_STARTEN1_SET_MU_SHIFT            (2U)
/*! MU - Message Unit wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_MU(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_MU_SHIFT)) & SYSCTL0_STARTEN1_SET_MU_MASK)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_MASK (0x8U)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_SHIFT (3U)
/*! GPIO_INT0_IRQ4 - Message Unit wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ4_MASK)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_MASK (0x10U)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_SHIFT (4U)
/*! GPIO_INT0_IRQ5 - GPIO pin interrupt 5 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ5_MASK)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_MASK (0x20U)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_SHIFT (5U)
/*! GPIO_INT0_IRQ6 - GPIO pin interrupt 6 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ6_MASK)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_MASK (0x40U)
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_SHIFT (6U)
/*! GPIO_INT0_IRQ7 - GPIO pin interrupt 7 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_SHIFT)) & SYSCTL0_STARTEN1_SET_GPIO_INT0_IRQ7_MASK)
#define SYSCTL0_STARTEN1_SET_CT32BIT2_MASK       (0x80U)
#define SYSCTL0_STARTEN1_SET_CT32BIT2_SHIFT      (7U)
/*! CT32BIT2 - CTIMER 2 wake-up
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_CT32BIT2(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_CT32BIT2_SHIFT)) & SYSCTL0_STARTEN1_SET_CT32BIT2_MASK)
#define SYSCTL0_STARTEN1_SET_CT32BIT4_MASK       (0x100U)
#define SYSCTL0_STARTEN1_SET_CT32BIT4_SHIFT      (8U)
/*! CT32BIT4 - CTIMER 4 wake-up
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_CT32BIT4(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_CT32BIT4_SHIFT)) & SYSCTL0_STARTEN1_SET_CT32BIT4_MASK)
#define SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_MASK (0x200U)
#define SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_SHIFT (9U)
/*! OS_EVENT_TIMER_WU - OS Event Timer wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_SHIFT)) & SYSCTL0_STARTEN1_SET_OS_EVENT_TIMER_WU_MASK)
#define SYSCTL0_STARTEN1_SET_OSPI_MASK           (0x400U)
#define SYSCTL0_STARTEN1_SET_OSPI_SHIFT          (10U)
/*! OSPI - Quad/octal SPI wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_OSPI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_OSPI_SHIFT)) & SYSCTL0_STARTEN1_SET_OSPI_MASK)
#define SYSCTL0_STARTEN1_SET_FLEXCOMM6_MASK      (0x800U)
#define SYSCTL0_STARTEN1_SET_FLEXCOMM6_SHIFT     (11U)
/*! FLEXCOMM6 - FLEXCOMM6 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_FLEXCOMM6(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM6_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM6_MASK)
#define SYSCTL0_STARTEN1_SET_FLEXCOMM7_MASK      (0x1000U)
#define SYSCTL0_STARTEN1_SET_FLEXCOMM7_SHIFT     (12U)
/*! FLEXCOMM7 - FLEXCOMM7 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_FLEXCOMM7(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_FLEXCOMM7_SHIFT)) & SYSCTL0_STARTEN1_SET_FLEXCOMM7_MASK)
#define SYSCTL0_STARTEN1_SET_SDIO0_MASK          (0x2000U)
#define SYSCTL0_STARTEN1_SET_SDIO0_SHIFT         (13U)
/*! SDIO0 - SDIO0 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_SDIO0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SDIO0_SHIFT)) & SYSCTL0_STARTEN1_SET_SDIO0_MASK)
#define SYSCTL0_STARTEN1_SET_SDIO1_MASK          (0x4000U)
#define SYSCTL0_STARTEN1_SET_SDIO1_SHIFT         (14U)
/*! SDIO1 - SDIO01 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_SDIO1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SDIO1_SHIFT)) & SYSCTL0_STARTEN1_SET_SDIO1_MASK)
#define SYSCTL0_STARTEN1_SET_SHSGPIO_INT0_MASK   (0x8000U)
#define SYSCTL0_STARTEN1_SET_SHSGPIO_INT0_SHIFT  (15U)
/*! SHSGPIO_INT0 - Secure GPIO interrupt A wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_SHSGPIO_INT0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SHSGPIO_INT0_SHIFT)) & SYSCTL0_STARTEN1_SET_SHSGPIO_INT0_MASK)
#define SYSCTL0_STARTEN1_SET_SHSGPIO_INT1_MASK   (0x10000U)
#define SYSCTL0_STARTEN1_SET_SHSGPIO_INT1_SHIFT  (16U)
/*! SHSGPIO_INT1 - Secure GPIO interrupt B wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_SHSGPIO_INT1(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SHSGPIO_INT1_SHIFT)) & SYSCTL0_STARTEN1_SET_SHSGPIO_INT1_MASK)
#define SYSCTL0_STARTEN1_SET_I3C0_MASK           (0x20000U)
#define SYSCTL0_STARTEN1_SET_I3C0_SHIFT          (17U)
/*! I3C0 - I3C wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_I3C0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_I3C0_SHIFT)) & SYSCTL0_STARTEN1_SET_I3C0_MASK)
#define SYSCTL0_STARTEN1_SET_USB0_IRQ_MASK       (0x40000U)
#define SYSCTL0_STARTEN1_SET_USB0_IRQ_SHIFT      (18U)
/*! USB0_IRQ - USB device/host interrupt wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_USB0_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_USB0_IRQ_SHIFT)) & SYSCTL0_STARTEN1_SET_USB0_IRQ_MASK)
#define SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_MASK   (0x80000U)
#define SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_SHIFT  (19U)
/*! USB0_NEEDCLK - USB activity wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_USB0_NEEDCLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_SHIFT)) & SYSCTL0_STARTEN1_SET_USB0_NEEDCLK_MASK)
#define SYSCTL0_STARTEN1_SET_DMAC1_MASK          (0x400000U)
#define SYSCTL0_STARTEN1_SET_DMAC1_SHIFT         (22U)
/*! DMAC1 - DMA controller 1 wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_DMAC1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_DMAC1_SHIFT)) & SYSCTL0_STARTEN1_SET_DMAC1_MASK)
#define SYSCTL0_STARTEN1_SET_PUF_MASK            (0x800000U)
#define SYSCTL0_STARTEN1_SET_PUF_SHIFT           (23U)
/*! PUF - PUF wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_PUF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_PUF_SHIFT)) & SYSCTL0_STARTEN1_SET_PUF_MASK)
#define SYSCTL0_STARTEN1_SET_POWERQUAD_MASK      (0x1000000U)
#define SYSCTL0_STARTEN1_SET_POWERQUAD_SHIFT     (24U)
/*! POWERQUAD - POWERQUAD co-processor wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_POWERQUAD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_POWERQUAD_SHIFT)) & SYSCTL0_STARTEN1_SET_POWERQUAD_MASK)
#define SYSCTL0_STARTEN1_SET_CASPER_MASK         (0x2000000U)
#define SYSCTL0_STARTEN1_SET_CASPER_SHIFT        (25U)
/*! CASPER - CASPER co-processor wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_CASPER(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_CASPER_SHIFT)) & SYSCTL0_STARTEN1_SET_CASPER_MASK)
#define SYSCTL0_STARTEN1_SET_PMIC_MASK           (0x4000000U)
#define SYSCTL0_STARTEN1_SET_PMIC_SHIFT          (26U)
/*! PMIC - Wake-up from on-chip PMC or off-chip PMIC.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_PMIC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_PMIC_SHIFT)) & SYSCTL0_STARTEN1_SET_PMIC_MASK)
#define SYSCTL0_STARTEN1_SET_SHA_MASK            (0x8000000U)
#define SYSCTL0_STARTEN1_SET_SHA_SHIFT           (27U)
/*! SHA - Hash-AES wake-up.
 *  0b0..No Effect
 *  0b1..Sets the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_SET_SHA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_SET_SHA_SHIFT)) & SYSCTL0_STARTEN1_SET_SHA_MASK)
/*! @} */

/*! @name STARTEN0_CLR - Start Enable 0 clear */
/*! @{ */
#define SYSCTL0_STARTEN0_CLR_WDT0_MASK           (0x1U)
#define SYSCTL0_STARTEN0_CLR_WDT0_SHIFT          (0U)
/*! WDT0 - Watchdog timer 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_WDT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_WDT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_WDT0_MASK)
#define SYSCTL0_STARTEN0_CLR_DMAC0_MASK          (0x2U)
#define SYSCTL0_STARTEN0_CLR_DMAC0_SHIFT         (1U)
/*! DMAC0 - DMA controller 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_DMAC0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_DMAC0_SHIFT)) & SYSCTL0_STARTEN0_CLR_DMAC0_MASK)
#define SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT0_MASK  (0x4U)
#define SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT0_SHIFT (2U)
/*! NSHSGPIO_INT0 - Non-secure GPIO interrupt A wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT0(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT0_MASK)
#define SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT1_MASK  (0x8U)
#define SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT1_SHIFT (3U)
/*! NSHSGPIO_INT1 - Non-secure GPIO interrupt B wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT1(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT1_SHIFT)) & SYSCTL0_STARTEN0_CLR_NSHSGPIO_INT1_MASK)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_MASK (0x10U)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_SHIFT (4U)
/*! GPIO_INT0_IRQ0 - GPIO pin interrupt 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ0_MASK)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_MASK (0x20U)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_SHIFT (5U)
/*! GPIO_INT0_IRQ1 - GPIO pin interrupt 1 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ1_MASK)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_MASK (0x40U)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_SHIFT (6U)
/*! GPIO_INT0_IRQ2 - GPIO pin interrupt 2 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ2_MASK)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_MASK (0x80U)
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_SHIFT (7U)
/*! GPIO_INT0_IRQ3 - GPIO pin interrupt 3 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_SHIFT)) & SYSCTL0_STARTEN0_CLR_GPIO_INT0_IRQ3_MASK)
#define SYSCTL0_STARTEN0_CLR_UTICK0_MASK         (0x100U)
#define SYSCTL0_STARTEN0_CLR_UTICK0_SHIFT        (8U)
/*! UTICK0 - UTICK wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_UTICK0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_UTICK0_SHIFT)) & SYSCTL0_STARTEN0_CLR_UTICK0_MASK)
#define SYSCTL0_STARTEN0_CLR_MRT0_MASK           (0x200U)
#define SYSCTL0_STARTEN0_CLR_MRT0_SHIFT          (9U)
/*! MRT0 - MRT wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_MRT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_MRT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_MRT0_MASK)
#define SYSCTL0_STARTEN0_CLR_CT32BIT0_MASK       (0x400U)
#define SYSCTL0_STARTEN0_CLR_CT32BIT0_SHIFT      (10U)
/*! CT32BIT0 - CTIMER 0 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_CT32BIT0(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_CT32BIT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_CT32BIT0_MASK)
#define SYSCTL0_STARTEN0_CLR_CT32BIT1_MASK       (0x800U)
#define SYSCTL0_STARTEN0_CLR_CT32BIT1_SHIFT      (11U)
/*! CT32BIT1 - CTIMER 1 wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_CT32BIT1(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_CT32BIT1_SHIFT)) & SYSCTL0_STARTEN0_CLR_CT32BIT1_MASK)
#define SYSCTL0_STARTEN0_CLR_SCT0_MASK           (0x1000U)
#define SYSCTL0_STARTEN0_CLR_SCT0_SHIFT          (12U)
/*! SCT0 - SCTimer/PWM wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_SCT0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_SCT0_SHIFT)) & SYSCTL0_STARTEN0_CLR_SCT0_MASK)
#define SYSCTL0_STARTEN0_CLR_CT32BIT3_MASK       (0x2000U)
#define SYSCTL0_STARTEN0_CLR_CT32BIT3_SHIFT      (13U)
/*! CT32BIT3 - CTIMER 3 wake-up
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_CT32BIT3(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_CT32BIT3_SHIFT)) & SYSCTL0_STARTEN0_CLR_CT32BIT3_MASK)
#define SYSCTL0_STARTEN0_CLR_FLEXCOMM14_MASK     (0x100000U)
#define SYSCTL0_STARTEN0_CLR_FLEXCOMM14_SHIFT    (20U)
/*! FLEXCOMM14 - Flexcomm 14 (High Speed SPI) peripheral interrupt wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_FLEXCOMM14(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_FLEXCOMM14_SHIFT)) & SYSCTL0_STARTEN0_CLR_FLEXCOMM14_MASK)
#define SYSCTL0_STARTEN0_CLR_FLEXCOMM15_MASK     (0x200000U)
#define SYSCTL0_STARTEN0_CLR_FLEXCOMM15_SHIFT    (21U)
/*! FLEXCOMM15 - Flexcomm 15 (PMIC I2C) peripheral interrupt wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_FLEXCOMM15(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_FLEXCOMM15_SHIFT)) & SYSCTL0_STARTEN0_CLR_FLEXCOMM15_MASK)
#define SYSCTL0_STARTEN0_CLR_ADC0_MASK           (0x400000U)
#define SYSCTL0_STARTEN0_CLR_ADC0_SHIFT          (22U)
/*! ADC0 - ADC wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_ADC0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_ADC0_SHIFT)) & SYSCTL0_STARTEN0_CLR_ADC0_MASK)
#define SYSCTL0_STARTEN0_CLR_ACMP_MASK           (0x1000000U)
#define SYSCTL0_STARTEN0_CLR_ACMP_SHIFT          (24U)
/*! ACMP - ACMP wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_ACMP(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_ACMP_SHIFT)) & SYSCTL0_STARTEN0_CLR_ACMP_MASK)
#define SYSCTL0_STARTEN0_CLR_DMIC0_MASK          (0x2000000U)
#define SYSCTL0_STARTEN0_CLR_DMIC0_SHIFT         (25U)
/*! DMIC0 - DMIC wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_DMIC0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_DMIC0_SHIFT)) & SYSCTL0_STARTEN0_CLR_DMIC0_MASK)
#define SYSCTL0_STARTEN0_CLR_HYPERVISOR_MASK     (0x8000000U)
#define SYSCTL0_STARTEN0_CLR_HYPERVISOR_SHIFT    (27U)
/*! HYPERVISOR - Hypervisor interrupt wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_HYPERVISOR(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_HYPERVISOR_SHIFT)) & SYSCTL0_STARTEN0_CLR_HYPERVISOR_MASK)
#define SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_MASK (0x10000000U)
#define SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_SHIFT (28U)
/*! SECUREVIOLATION - Secure Violation wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_SECUREVIOLATION(x)  (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_SHIFT)) & SYSCTL0_STARTEN0_CLR_SECUREVIOLATION_MASK)
#define SYSCTL0_STARTEN0_CLR_HWVAD0_MASK         (0x20000000U)
#define SYSCTL0_STARTEN0_CLR_HWVAD0_SHIFT        (29U)
/*! HWVAD0 - Hardware VAD wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_HWVAD0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_HWVAD0_SHIFT)) & SYSCTL0_STARTEN0_CLR_HWVAD0_MASK)
#define SYSCTL0_STARTEN0_CLR_PMC_MASK            (0x40000000U)
#define SYSCTL0_STARTEN0_CLR_PMC_SHIFT           (30U)
/*! PMC - PMC wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_PMC(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_PMC_SHIFT)) & SYSCTL0_STARTEN0_CLR_PMC_MASK)
#define SYSCTL0_STARTEN0_CLR_RNG_MASK            (0x80000000U)
#define SYSCTL0_STARTEN0_CLR_RNG_SHIFT           (31U)
/*! RNG - RNG wake-up.
 *  0b0..No effect
 *  0b1..Sets the STARTEN0 Bit
 */
#define SYSCTL0_STARTEN0_CLR_RNG(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN0_CLR_RNG_SHIFT)) & SYSCTL0_STARTEN0_CLR_RNG_MASK)
/*! @} */

/*! @name STARTEN1_CLR - Start Enable 1 clear */
/*! @{ */
#define SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_MASK (0x1U)
#define SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_SHIFT (0U)
/*! RTC_LITE0_WAKEUP - RTC wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_SHIFT)) & SYSCTL0_STARTEN1_CLR_RTC_LITE0_WAKEUP_MASK)
#define SYSCTL0_STARTEN1_CLR_MU_MASK             (0x4U)
#define SYSCTL0_STARTEN1_CLR_MU_SHIFT            (2U)
/*! MU - Message Unit wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_MU(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_MU_SHIFT)) & SYSCTL0_STARTEN1_CLR_MU_MASK)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_MASK (0x8U)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_SHIFT (3U)
/*! GPIO_INT0_IRQ4 - Message Unit wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ4_MASK)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_MASK (0x10U)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_SHIFT (4U)
/*! GPIO_INT0_IRQ5 - GPIO pin interrupt 5 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ5_MASK)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_MASK (0x20U)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_SHIFT (5U)
/*! GPIO_INT0_IRQ6 - GPIO pin interrupt 6 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ6_MASK)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_MASK (0x40U)
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_SHIFT (6U)
/*! GPIO_INT0_IRQ7 - GPIO pin interrupt 7 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_SHIFT)) & SYSCTL0_STARTEN1_CLR_GPIO_INT0_IRQ7_MASK)
#define SYSCTL0_STARTEN1_CLR_CT32BIT2_MASK       (0x80U)
#define SYSCTL0_STARTEN1_CLR_CT32BIT2_SHIFT      (7U)
/*! CT32BIT2 - CTIMER 2 wake-up
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_CT32BIT2(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_CT32BIT2_SHIFT)) & SYSCTL0_STARTEN1_CLR_CT32BIT2_MASK)
#define SYSCTL0_STARTEN1_CLR_CT32BIT4_MASK       (0x100U)
#define SYSCTL0_STARTEN1_CLR_CT32BIT4_SHIFT      (8U)
/*! CT32BIT4 - CTIMER 4 wake-up
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_CT32BIT4(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_CT32BIT4_SHIFT)) & SYSCTL0_STARTEN1_CLR_CT32BIT4_MASK)
#define SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_MASK (0x200U)
#define SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_SHIFT (9U)
/*! OS_EVENT_TIMER_WU - OS Event Timer wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_SHIFT)) & SYSCTL0_STARTEN1_CLR_OS_EVENT_TIMER_WU_MASK)
#define SYSCTL0_STARTEN1_CLR_OSPI_MASK           (0x400U)
#define SYSCTL0_STARTEN1_CLR_OSPI_SHIFT          (10U)
/*! OSPI - Quad/octal SPI wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_OSPI(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_OSPI_SHIFT)) & SYSCTL0_STARTEN1_CLR_OSPI_MASK)
#define SYSCTL0_STARTEN1_CLR_FLEXCOMM6_MASK      (0x800U)
#define SYSCTL0_STARTEN1_CLR_FLEXCOMM6_SHIFT     (11U)
/*! FLEXCOMM6 - FLEXCOMM6 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_FLEXCOMM6(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM6_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM6_MASK)
#define SYSCTL0_STARTEN1_CLR_FLEXCOMM7_MASK      (0x1000U)
#define SYSCTL0_STARTEN1_CLR_FLEXCOMM7_SHIFT     (12U)
/*! FLEXCOMM7 - FLEXCOMM7 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_FLEXCOMM7(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_FLEXCOMM7_SHIFT)) & SYSCTL0_STARTEN1_CLR_FLEXCOMM7_MASK)
#define SYSCTL0_STARTEN1_CLR_SDIO0_MASK          (0x2000U)
#define SYSCTL0_STARTEN1_CLR_SDIO0_SHIFT         (13U)
/*! SDIO0 - SDIO0 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_SDIO0(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SDIO0_SHIFT)) & SYSCTL0_STARTEN1_CLR_SDIO0_MASK)
#define SYSCTL0_STARTEN1_CLR_SDIO1_MASK          (0x4000U)
#define SYSCTL0_STARTEN1_CLR_SDIO1_SHIFT         (14U)
/*! SDIO1 - SDIO01 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_SDIO1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SDIO1_SHIFT)) & SYSCTL0_STARTEN1_CLR_SDIO1_MASK)
#define SYSCTL0_STARTEN1_CLR_SHSGPIO_INT0_MASK   (0x8000U)
#define SYSCTL0_STARTEN1_CLR_SHSGPIO_INT0_SHIFT  (15U)
/*! SHSGPIO_INT0 - Secure GPIO interrupt A wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_SHSGPIO_INT0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SHSGPIO_INT0_SHIFT)) & SYSCTL0_STARTEN1_CLR_SHSGPIO_INT0_MASK)
#define SYSCTL0_STARTEN1_CLR_SHSGPIO_INT1_MASK   (0x10000U)
#define SYSCTL0_STARTEN1_CLR_SHSGPIO_INT1_SHIFT  (16U)
/*! SHSGPIO_INT1 - Secure GPIO interrupt B wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_SHSGPIO_INT1(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SHSGPIO_INT1_SHIFT)) & SYSCTL0_STARTEN1_CLR_SHSGPIO_INT1_MASK)
#define SYSCTL0_STARTEN1_CLR_I3C0_MASK           (0x20000U)
#define SYSCTL0_STARTEN1_CLR_I3C0_SHIFT          (17U)
/*! I3C0 - I3C wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_I3C0(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_I3C0_SHIFT)) & SYSCTL0_STARTEN1_CLR_I3C0_MASK)
#define SYSCTL0_STARTEN1_CLR_USB0_IRQ_MASK       (0x40000U)
#define SYSCTL0_STARTEN1_CLR_USB0_IRQ_SHIFT      (18U)
/*! USB0_IRQ - USB device/host interrupt wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_USB0_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_USB0_IRQ_SHIFT)) & SYSCTL0_STARTEN1_CLR_USB0_IRQ_MASK)
#define SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_MASK   (0x80000U)
#define SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_SHIFT  (19U)
/*! USB0_NEEDCLK - USB activity wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_SHIFT)) & SYSCTL0_STARTEN1_CLR_USB0_NEEDCLK_MASK)
#define SYSCTL0_STARTEN1_CLR_DMAC1_MASK          (0x400000U)
#define SYSCTL0_STARTEN1_CLR_DMAC1_SHIFT         (22U)
/*! DMAC1 - DMA controller 1 wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_DMAC1(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_DMAC1_SHIFT)) & SYSCTL0_STARTEN1_CLR_DMAC1_MASK)
#define SYSCTL0_STARTEN1_CLR_PUF_MASK            (0x800000U)
#define SYSCTL0_STARTEN1_CLR_PUF_SHIFT           (23U)
/*! PUF - PUF wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_PUF(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_PUF_SHIFT)) & SYSCTL0_STARTEN1_CLR_PUF_MASK)
#define SYSCTL0_STARTEN1_CLR_POWERQUAD_MASK      (0x1000000U)
#define SYSCTL0_STARTEN1_CLR_POWERQUAD_SHIFT     (24U)
/*! POWERQUAD - POWERQUAD co-processor wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_POWERQUAD(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_POWERQUAD_SHIFT)) & SYSCTL0_STARTEN1_CLR_POWERQUAD_MASK)
#define SYSCTL0_STARTEN1_CLR_CASPER_MASK         (0x2000000U)
#define SYSCTL0_STARTEN1_CLR_CASPER_SHIFT        (25U)
/*! CASPER - CASPER co-processor wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_CASPER(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_CASPER_SHIFT)) & SYSCTL0_STARTEN1_CLR_CASPER_MASK)
#define SYSCTL0_STARTEN1_CLR_PMIC_MASK           (0x4000000U)
#define SYSCTL0_STARTEN1_CLR_PMIC_SHIFT          (26U)
/*! PMIC - Wake-up from on-chip PMC or off-chip PMIC.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_PMIC(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_PMIC_SHIFT)) & SYSCTL0_STARTEN1_CLR_PMIC_MASK)
#define SYSCTL0_STARTEN1_CLR_SHA_MASK            (0x8000000U)
#define SYSCTL0_STARTEN1_CLR_SHA_SHIFT           (27U)
/*! SHA - Hash-AES wake-up.
 *  0b0..No Effect
 *  0b1..Clears the START_EN1 Bit
 */
#define SYSCTL0_STARTEN1_CLR_SHA(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_STARTEN1_CLR_SHA_SHIFT)) & SYSCTL0_STARTEN1_CLR_SHA_MASK)
/*! @} */

/*! @name HWWAKE - Hardware Wake */
/*! @{ */
#define SYSCTL0_HWWAKE_FORCEWAKE_MASK            (0x1U)
#define SYSCTL0_HWWAKE_FORCEWAKE_SHIFT           (0U)
/*! FORCEWAKE - Force peripheral clocking to stay on during deep-sleep mode.
 */
#define SYSCTL0_HWWAKE_FORCEWAKE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_FORCEWAKE_SHIFT)) & SYSCTL0_HWWAKE_FORCEWAKE_MASK)
#define SYSCTL0_HWWAKE_FCWAKE_MASK               (0x2U)
#define SYSCTL0_HWWAKE_FCWAKE_SHIFT              (1U)
/*! FCWAKE - Wake for Flexcomm Interfaces.
 */
#define SYSCTL0_HWWAKE_FCWAKE(x)                 (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_FCWAKE_SHIFT)) & SYSCTL0_HWWAKE_FCWAKE_MASK)
#define SYSCTL0_HWWAKE_DMICWAKE_MASK             (0x4U)
#define SYSCTL0_HWWAKE_DMICWAKE_SHIFT            (2U)
/*! DMICWAKE - Wake for Digital Microphone.
 */
#define SYSCTL0_HWWAKE_DMICWAKE(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMICWAKE_SHIFT)) & SYSCTL0_HWWAKE_DMICWAKE_MASK)
#define SYSCTL0_HWWAKE_DMAC0WAKE_MASK            (0x8U)
#define SYSCTL0_HWWAKE_DMAC0WAKE_SHIFT           (3U)
/*! DMAC0WAKE - Wake for DMAC0.
 */
#define SYSCTL0_HWWAKE_DMAC0WAKE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMAC0WAKE_SHIFT)) & SYSCTL0_HWWAKE_DMAC0WAKE_MASK)
#define SYSCTL0_HWWAKE_DMAC1WAKE_MASK            (0x10U)
#define SYSCTL0_HWWAKE_DMAC1WAKE_SHIFT           (4U)
/*! DMAC1WAKE - Wake for DMAC1.
 */
#define SYSCTL0_HWWAKE_DMAC1WAKE(x)              (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWWAKE_DMAC1WAKE_SHIFT)) & SYSCTL0_HWWAKE_DMAC1WAKE_MASK)
/*! @} */

/*! @name TEMPSENSORCTL - Temperature Sensor Control */
/*! @{ */
#define SYSCTL0_TEMPSENSORCTL_TSSRC_MASK         (0x1U)
#define SYSCTL0_TEMPSENSORCTL_TSSRC_SHIFT        (0U)
/*! TSSRC - Temperature Sensor Source
 *  0b0..ADC Built-in Temperature Sensor
 *  0b1..PMC Temperature Sensor
 */
#define SYSCTL0_TEMPSENSORCTL_TSSRC(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_TEMPSENSORCTL_TSSRC_SHIFT)) & SYSCTL0_TEMPSENSORCTL_TSSRC_MASK)
/*! @} */

/*! @name DSPMEMSPEEDCTL - DSP Memory Speed Control */
/*! @{ */
#define SYSCTL0_DSPMEMSPEEDCTL_DSPCAC_MASK       (0x3U)
#define SYSCTL0_DSPMEMSPEEDCTL_DSPCAC_SHIFT      (0U)
/*! DSPCAC - DSP Cache Register File Speed
 *  0b00..Default
 *  0b01..Low speed
 *  0b10..High speed
 *  0b11..Low speed
 */
#define SYSCTL0_DSPMEMSPEEDCTL_DSPCAC(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSPMEMSPEEDCTL_DSPCAC_SHIFT)) & SYSCTL0_DSPMEMSPEEDCTL_DSPCAC_MASK)
#define SYSCTL0_DSPMEMSPEEDCTL_DSPTCM_MASK       (0xCU)
#define SYSCTL0_DSPMEMSPEEDCTL_DSPTCM_SHIFT      (2U)
/*! DSPTCM - DSP TCM Speed
 *  0b00..Default
 *  0b01..Low speed
 *  0b10..High speed
 *  0b11..Low speed
 */
#define SYSCTL0_DSPMEMSPEEDCTL_DSPTCM(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DSPMEMSPEEDCTL_DSPTCM_SHIFT)) & SYSCTL0_DSPMEMSPEEDCTL_DSPTCM_MASK)
/*! @} */

/*! @name DBG_CTRL - Debug Control */
/*! @{ */
#define SYSCTL0_DBG_CTRL_MODULE_DEBUG_SEL_MASK   (0xFU)
#define SYSCTL0_DBG_CTRL_MODULE_DEBUG_SEL_SHIFT  (0U)
/*! MODULE_DEBUG_SEL - Module Debug Select
 */
#define SYSCTL0_DBG_CTRL_MODULE_DEBUG_SEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_CTRL_MODULE_DEBUG_SEL_SHIFT)) & SYSCTL0_DBG_CTRL_MODULE_DEBUG_SEL_MASK)
/*! @} */

/*! @name TESTCLK_TRIM - Test Clock Trim */
/*! @{ */
#define SYSCTL0_TESTCLK_TRIM_TESTCLK_TRIM_MASK   (0x3U)
#define SYSCTL0_TESTCLK_TRIM_TESTCLK_TRIM_SHIFT  (0U)
/*! TESTCLK_TRIM - TEST Clock Trim
 */
#define SYSCTL0_TESTCLK_TRIM_TESTCLK_TRIM(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_TESTCLK_TRIM_TESTCLK_TRIM_SHIFT)) & SYSCTL0_TESTCLK_TRIM_TESTCLK_TRIM_MASK)
/*! @} */

/*! @name FLEXSPI0PADCTL - FLEXSPI0 Pad Control */
/*! @{ */
#define SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_MASK   (0xFU)
#define SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_SHIFT  (0U)
/*! RASRCN_3_0 - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_RASRCN_3_0_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_MASK   (0xF0U)
#define SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_SHIFT  (4U)
/*! RASRCP_3_0 - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_RASRCP_3_0_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_MASK      (0x100U)
#define SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_SHIFT     (8U)
/*! FASTFRZ - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI0PADCTL_FASTFRZ(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_FASTFRZ_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_FREEZE_MASK       (0x200U)
#define SYSCTL0_FLEXSPI0PADCTL_FREEZE_SHIFT      (9U)
/*! FREEZE - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI0PADCTL_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_FREEZE_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_FREEZE_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_COMPTQ_MASK       (0x400U)
#define SYSCTL0_FLEXSPI0PADCTL_COMPTQ_SHIFT      (10U)
/*! COMPTQ - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI0PADCTL_COMPTQ(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_COMPTQ_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_COMPTQ_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_COMPEN_MASK       (0x800U)
#define SYSCTL0_FLEXSPI0PADCTL_COMPEN_SHIFT      (11U)
/*! COMPEN - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI0PADCTL_COMPEN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_COMPEN_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_NASRCN_MASK       (0xF0000U)
#define SYSCTL0_FLEXSPI0PADCTL_NASRCN_SHIFT      (16U)
/*! NASRCN - SDIO Pad Compensation Circuit Status
 */
#define SYSCTL0_FLEXSPI0PADCTL_NASRCN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_NASRCN_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_NASRCN_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_NASRCP_MASK       (0xF00000U)
#define SYSCTL0_FLEXSPI0PADCTL_NASRCP_SHIFT      (20U)
/*! NASRCP - SDIO Pad Compensation Circuit Status
 */
#define SYSCTL0_FLEXSPI0PADCTL_NASRCP(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_NASRCP_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_NASRCP_MASK)
#define SYSCTL0_FLEXSPI0PADCTL_COMPOK_MASK       (0x1000000U)
#define SYSCTL0_FLEXSPI0PADCTL_COMPOK_SHIFT      (24U)
/*! COMPOK - SDIO Pad Compensation Circuit Status
 */
#define SYSCTL0_FLEXSPI0PADCTL_COMPOK(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI0PADCTL_COMPOK_SHIFT)) & SYSCTL0_FLEXSPI0PADCTL_COMPOK_MASK)
/*! @} */

/*! @name FLEXSPI1PADCTL - FLEXSPI1 Pad Control */
/*! @{ */
#define SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_MASK   (0xFU)
#define SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_SHIFT  (0U)
/*! RASRCN_3_0 - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_RASRCN_3_0_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_MASK   (0xF0U)
#define SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_SHIFT  (4U)
/*! RASRCP_3_0 - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_RASRCP_3_0_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_MASK      (0x100U)
#define SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_SHIFT     (8U)
/*! FASTFRZ - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI1PADCTL_FASTFRZ(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_FASTFRZ_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_FREEZE_MASK       (0x200U)
#define SYSCTL0_FLEXSPI1PADCTL_FREEZE_SHIFT      (9U)
/*! FREEZE - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI1PADCTL_FREEZE(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_FREEZE_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_FREEZE_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_COMPTQ_MASK       (0x400U)
#define SYSCTL0_FLEXSPI1PADCTL_COMPTQ_SHIFT      (10U)
/*! COMPTQ - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI1PADCTL_COMPTQ(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPTQ_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPTQ_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK       (0x800U)
#define SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT      (11U)
/*! COMPEN - Drives SDIO Pad Compensation Circuit
 */
#define SYSCTL0_FLEXSPI1PADCTL_COMPEN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPEN_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPEN_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_MASK   (0xF0000U)
#define SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_SHIFT  (16U)
/*! NASRCN_3_0 - SDIO Pad Compensation Circuit Status
 */
#define SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_NASRCN_3_0_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_MASK   (0xF00000U)
#define SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_SHIFT  (20U)
/*! NASRCP_3_0 - SDIO Pad Compensation Circuit Status
 */
#define SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_NASRCP_3_0_MASK)
#define SYSCTL0_FLEXSPI1PADCTL_COMPOK_MASK       (0x1000000U)
#define SYSCTL0_FLEXSPI1PADCTL_COMPOK_SHIFT      (24U)
/*! COMPOK - SDIO Pad Compensation Circuit Status
 */
#define SYSCTL0_FLEXSPI1PADCTL_COMPOK(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_FLEXSPI1PADCTL_COMPOK_SHIFT)) & SYSCTL0_FLEXSPI1PADCTL_COMPOK_MASK)
/*! @} */

/*! @name SDIO0PADCTL - SDIO0 Pad Control */
/*! @{ */
#define SYSCTL0_SDIO0PADCTL_RASRCN_MASK          (0xFU)
#define SYSCTL0_SDIO0PADCTL_RASRCN_SHIFT         (0U)
/*! RASRCN - Drives SDIO0 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO0PADCTL_RASRCN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_RASRCN_SHIFT)) & SYSCTL0_SDIO0PADCTL_RASRCN_MASK)
#define SYSCTL0_SDIO0PADCTL_RASRCP_MASK          (0xF0U)
#define SYSCTL0_SDIO0PADCTL_RASRCP_SHIFT         (4U)
/*! RASRCP - Drives SDIO0 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO0PADCTL_RASRCP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_RASRCP_SHIFT)) & SYSCTL0_SDIO0PADCTL_RASRCP_MASK)
#define SYSCTL0_SDIO0PADCTL_FASTFRZ_MASK         (0x100U)
#define SYSCTL0_SDIO0PADCTL_FASTFRZ_SHIFT        (8U)
/*! FASTFRZ - Drives SDIO0 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO0PADCTL_FASTFRZ(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_SDIO0PADCTL_FASTFRZ_MASK)
#define SYSCTL0_SDIO0PADCTL_FREEZE_MASK          (0x200U)
#define SYSCTL0_SDIO0PADCTL_FREEZE_SHIFT         (9U)
/*! FREEZE - Drives SDIO0 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO0PADCTL_FREEZE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_FREEZE_SHIFT)) & SYSCTL0_SDIO0PADCTL_FREEZE_MASK)
#define SYSCTL0_SDIO0PADCTL_COMPTQ_MASK          (0x400U)
#define SYSCTL0_SDIO0PADCTL_COMPTQ_SHIFT         (10U)
/*! COMPTQ - Drives SDIO0 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO0PADCTL_COMPTQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_COMPTQ_SHIFT)) & SYSCTL0_SDIO0PADCTL_COMPTQ_MASK)
#define SYSCTL0_SDIO0PADCTL_COMPEN_MASK          (0x800U)
#define SYSCTL0_SDIO0PADCTL_COMPEN_SHIFT         (11U)
/*! COMPEN - Drives SDIO0 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO0PADCTL_COMPEN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_COMPEN_SHIFT)) & SYSCTL0_SDIO0PADCTL_COMPEN_MASK)
#define SYSCTL0_SDIO0PADCTL_NASRCN_MASK          (0xF0000U)
#define SYSCTL0_SDIO0PADCTL_NASRCN_SHIFT         (16U)
/*! NASRCN - SDIO0 Pad Compensation Circuit Status
 */
#define SYSCTL0_SDIO0PADCTL_NASRCN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_NASRCN_SHIFT)) & SYSCTL0_SDIO0PADCTL_NASRCN_MASK)
#define SYSCTL0_SDIO0PADCTL_NASRCP_MASK          (0xF00000U)
#define SYSCTL0_SDIO0PADCTL_NASRCP_SHIFT         (20U)
/*! NASRCP - SDIO0 Pad Compensation Circuit Status
 */
#define SYSCTL0_SDIO0PADCTL_NASRCP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_NASRCP_SHIFT)) & SYSCTL0_SDIO0PADCTL_NASRCP_MASK)
#define SYSCTL0_SDIO0PADCTL_COMPOK_MASK          (0x1000000U)
#define SYSCTL0_SDIO0PADCTL_COMPOK_SHIFT         (24U)
/*! COMPOK - SDIO0 Pad Compensation Circuit Status
 */
#define SYSCTL0_SDIO0PADCTL_COMPOK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO0PADCTL_COMPOK_SHIFT)) & SYSCTL0_SDIO0PADCTL_COMPOK_MASK)
/*! @} */

/*! @name SDIO1PADCTL - SDIO1 Pad Control */
/*! @{ */
#define SYSCTL0_SDIO1PADCTL_RASRCN_MASK          (0xFU)
#define SYSCTL0_SDIO1PADCTL_RASRCN_SHIFT         (0U)
/*! RASRCN - Drives SDIO1 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO1PADCTL_RASRCN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_RASRCN_SHIFT)) & SYSCTL0_SDIO1PADCTL_RASRCN_MASK)
#define SYSCTL0_SDIO1PADCTL_RASRCP_MASK          (0xF0U)
#define SYSCTL0_SDIO1PADCTL_RASRCP_SHIFT         (4U)
/*! RASRCP - Drives SDIO1 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO1PADCTL_RASRCP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_RASRCP_SHIFT)) & SYSCTL0_SDIO1PADCTL_RASRCP_MASK)
#define SYSCTL0_SDIO1PADCTL_FASTFRZ_MASK         (0x100U)
#define SYSCTL0_SDIO1PADCTL_FASTFRZ_SHIFT        (8U)
/*! FASTFRZ - Drives SDIO1 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO1PADCTL_FASTFRZ(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_FASTFRZ_SHIFT)) & SYSCTL0_SDIO1PADCTL_FASTFRZ_MASK)
#define SYSCTL0_SDIO1PADCTL_FREEZE_MASK          (0x200U)
#define SYSCTL0_SDIO1PADCTL_FREEZE_SHIFT         (9U)
/*! FREEZE - Drives SDIO1 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO1PADCTL_FREEZE(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_FREEZE_SHIFT)) & SYSCTL0_SDIO1PADCTL_FREEZE_MASK)
#define SYSCTL0_SDIO1PADCTL_COMPTQ_MASK          (0x400U)
#define SYSCTL0_SDIO1PADCTL_COMPTQ_SHIFT         (10U)
/*! COMPTQ - Drives SDIO1 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO1PADCTL_COMPTQ(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_COMPTQ_SHIFT)) & SYSCTL0_SDIO1PADCTL_COMPTQ_MASK)
#define SYSCTL0_SDIO1PADCTL_COMPEN_MASK          (0x800U)
#define SYSCTL0_SDIO1PADCTL_COMPEN_SHIFT         (11U)
/*! COMPEN - Drives SDIO1 Pad Compensation Circuit
 */
#define SYSCTL0_SDIO1PADCTL_COMPEN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_COMPEN_SHIFT)) & SYSCTL0_SDIO1PADCTL_COMPEN_MASK)
#define SYSCTL0_SDIO1PADCTL_NASRCN_MASK          (0xF0000U)
#define SYSCTL0_SDIO1PADCTL_NASRCN_SHIFT         (16U)
/*! NASRCN - SDIO1 Pad Compensation Circuit Status
 */
#define SYSCTL0_SDIO1PADCTL_NASRCN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_NASRCN_SHIFT)) & SYSCTL0_SDIO1PADCTL_NASRCN_MASK)
#define SYSCTL0_SDIO1PADCTL_NASRCP_MASK          (0xF00000U)
#define SYSCTL0_SDIO1PADCTL_NASRCP_SHIFT         (20U)
/*! NASRCP - SDIO1 Pad Compensation Circuit Status
 */
#define SYSCTL0_SDIO1PADCTL_NASRCP(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_NASRCP_SHIFT)) & SYSCTL0_SDIO1PADCTL_NASRCP_MASK)
#define SYSCTL0_SDIO1PADCTL_COMPOK_MASK          (0x1000000U)
#define SYSCTL0_SDIO1PADCTL_COMPOK_SHIFT         (24U)
/*! COMPOK - SDIO1 Pad Compensation Circuit Status
 */
#define SYSCTL0_SDIO1PADCTL_COMPOK(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL0_SDIO1PADCTL_COMPOK_SHIFT)) & SYSCTL0_SDIO1PADCTL_COMPOK_MASK)
/*! @} */

/*! @name DICEHWREGN - Compound Device Identifier (CDI) */
/*! @{ */
#define SYSCTL0_DICEHWREGN_DICEHWREGN_MASK       (0xFFFFFFFFU)
#define SYSCTL0_DICEHWREGN_DICEHWREGN_SHIFT      (0U)
/*! DICEHWREGN - DICE General Purpose 32-Bit Data Register
 */
#define SYSCTL0_DICEHWREGN_DICEHWREGN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DICEHWREGN_DICEHWREGN_SHIFT)) & SYSCTL0_DICEHWREGN_DICEHWREGN_MASK)
/*! @} */

/*! @name MIPI_DSI_TEST_IN1 - MIPI DSI Test IN1 */
/*! @{ */
#define SYSCTL0_MIPI_DSI_TEST_IN1_MIPI_DSI_TEST_IN1_MASK (0x3FU)
#define SYSCTL0_MIPI_DSI_TEST_IN1_MIPI_DSI_TEST_IN1_SHIFT (0U)
/*! MIPI_DSI_TEST_IN1 - MIPI-DSI Test input1 bus
 */
#define SYSCTL0_MIPI_DSI_TEST_IN1_MIPI_DSI_TEST_IN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_TEST_IN1_MIPI_DSI_TEST_IN1_SHIFT)) & SYSCTL0_MIPI_DSI_TEST_IN1_MIPI_DSI_TEST_IN1_MASK)
/*! @} */

/*! @name MIPI_DSI_TEST_IN2 - MIPI DSI Test IN2 */
/*! @{ */
#define SYSCTL0_MIPI_DSI_TEST_IN2_MIPI_DSI_TEST_IN2_MASK (0xFFFFFFFFU)
#define SYSCTL0_MIPI_DSI_TEST_IN2_MIPI_DSI_TEST_IN2_SHIFT (0U)
/*! MIPI_DSI_TEST_IN2 - MIPI-DSI Test input2 bus
 */
#define SYSCTL0_MIPI_DSI_TEST_IN2_MIPI_DSI_TEST_IN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_TEST_IN2_MIPI_DSI_TEST_IN2_SHIFT)) & SYSCTL0_MIPI_DSI_TEST_IN2_MIPI_DSI_TEST_IN2_MASK)
/*! @} */

/*! @name MIPI_DSI_TEST_OUT1 - MIPI DSI Test OUT1 */
/*! @{ */
#define SYSCTL0_MIPI_DSI_TEST_OUT1_MIPI_DSI_TEST_OUT1_MASK (0xFFFFFFFFU)
#define SYSCTL0_MIPI_DSI_TEST_OUT1_MIPI_DSI_TEST_OUT1_SHIFT (0U)
/*! MIPI_DSI_TEST_OUT1 - MIPI-DSI Test output 1 bus
 */
#define SYSCTL0_MIPI_DSI_TEST_OUT1_MIPI_DSI_TEST_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_TEST_OUT1_MIPI_DSI_TEST_OUT1_SHIFT)) & SYSCTL0_MIPI_DSI_TEST_OUT1_MIPI_DSI_TEST_OUT1_MASK)
/*! @} */

/*! @name MIPI_DSI_TEST_OUT2 - MIPI DSI Test OUT2 */
/*! @{ */
#define SYSCTL0_MIPI_DSI_TEST_OUT2_MIPI_DSI_TEST_OUT_2_MASK (0xFFFFFFFFU)
#define SYSCTL0_MIPI_DSI_TEST_OUT2_MIPI_DSI_TEST_OUT_2_SHIFT (0U)
/*! MIPI_DSI_TEST_OUT_2 - MIPI-DSI Test output 2 bus
 */
#define SYSCTL0_MIPI_DSI_TEST_OUT2_MIPI_DSI_TEST_OUT_2(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_MIPI_DSI_TEST_OUT2_MIPI_DSI_TEST_OUT_2_SHIFT)) & SYSCTL0_MIPI_DSI_TEST_OUT2_MIPI_DSI_TEST_OUT_2_MASK)
/*! @} */

/*! @name S0AES_UV - S0AES UV */
/*! @{ */
#define SYSCTL0_S0AES_UV_S0AES_UV_MASK           (0xFFFFFFFFU)
#define SYSCTL0_S0AES_UV_S0AES_UV_SHIFT          (0U)
/*! S0AES_UV - 32- Bit Unique Value
 */
#define SYSCTL0_S0AES_UV_S0AES_UV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_S0AES_UV_S0AES_UV_SHIFT)) & SYSCTL0_S0AES_UV_S0AES_UV_MASK)
/*! @} */

/*! @name S0AES_UV_WLOCK - S0AES UV WLOCK */
/*! @{ */
#define SYSCTL0_S0AES_UV_WLOCK_S0AES_UV_WLOCK_MASK (0x1U)
#define SYSCTL0_S0AES_UV_WLOCK_S0AES_UV_WLOCK_SHIFT (0U)
/*! S0AES_UV_WLOCK - S0AES_UV Register Write Lock
 */
#define SYSCTL0_S0AES_UV_WLOCK_S0AES_UV_WLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_S0AES_UV_WLOCK_S0AES_UV_WLOCK_SHIFT)) & SYSCTL0_S0AES_UV_WLOCK_S0AES_UV_WLOCK_MASK)
/*! @} */

/*! @name S1UDS_UV - S1UDS UV */
/*! @{ */
#define SYSCTL0_S1UDS_UV_S1UDS_UV_MASK           (0xFFFFFFFFU)
#define SYSCTL0_S1UDS_UV_S1UDS_UV_SHIFT          (0U)
/*! S1UDS_UV - 32- Bit Unique Value
 */
#define SYSCTL0_S1UDS_UV_S1UDS_UV(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_S1UDS_UV_S1UDS_UV_SHIFT)) & SYSCTL0_S1UDS_UV_S1UDS_UV_MASK)
/*! @} */

/*! @name S1UDS_UV_WLOCK - S1UDS UV WLOCK */
/*! @{ */
#define SYSCTL0_S1UDS_UV_WLOCK_S1UDS_UV_WLOCK_MASK (0x1U)
#define SYSCTL0_S1UDS_UV_WLOCK_S1UDS_UV_WLOCK_SHIFT (0U)
/*! S1UDS_UV_WLOCK - S1UDS_UV Register Write Lock
 */
#define SYSCTL0_S1UDS_UV_WLOCK_S1UDS_UV_WLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_S1UDS_UV_WLOCK_S1UDS_UV_WLOCK_SHIFT)) & SYSCTL0_S1UDS_UV_WLOCK_S1UDS_UV_WLOCK_MASK)
/*! @} */

/*! @name UDS_SEED - UDS SEED */
/*! @{ */
#define SYSCTL0_UDS_SEED_UDS_SEED_MASK           (0xFFFFFFFFU)
#define SYSCTL0_UDS_SEED_UDS_SEED_SHIFT          (0U)
/*! UDS_SEED - 32-Bit UDS Seed Value
 */
#define SYSCTL0_UDS_SEED_UDS_SEED(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL0_UDS_SEED_UDS_SEED_SHIFT)) & SYSCTL0_UDS_SEED_UDS_SEED_MASK)
/*! @} */

/*! @name UDS_SEED_RLOCK - UDS SEED RLOCK */
/*! @{ */
#define SYSCTL0_UDS_SEED_RLOCK_UDS_SEED_RLOCK_MASK (0x1U)
#define SYSCTL0_UDS_SEED_RLOCK_UDS_SEED_RLOCK_SHIFT (0U)
/*! UDS_SEED_RLOCK - UDS_SEED Register Read Lock
 */
#define SYSCTL0_UDS_SEED_RLOCK_UDS_SEED_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_UDS_SEED_RLOCK_UDS_SEED_RLOCK_SHIFT)) & SYSCTL0_UDS_SEED_RLOCK_UDS_SEED_RLOCK_MASK)
/*! @} */

/*! @name UUID - UUID */
/*! @{ */
#define SYSCTL0_UUID_UUIDN_MASK                  (0xFFFFFFFFU)
#define SYSCTL0_UUID_UUIDN_SHIFT                 (0U)
/*! UUIDN - UUIDn 32-Bit Data Register
 */
#define SYSCTL0_UUID_UUIDN(x)                    (((uint32_t)(((uint32_t)(x)) << SYSCTL0_UUID_UUIDN_SHIFT)) & SYSCTL0_UUID_UUIDN_MASK)
/*! @} */

/* The count of SYSCTL0_UUID */
#define SYSCTL0_UUID_COUNT                       (4U)

/*! @name UUID_WLOCK - UUID WLOCK */
/*! @{ */
#define SYSCTL0_UUID_WLOCK_UUID_WLOCK_MASK       (0x1U)
#define SYSCTL0_UUID_WLOCK_UUID_WLOCK_SHIFT      (0U)
/*! UUID_WLOCK - UUID0/1/2/3 Register Write Lock
 */
#define SYSCTL0_UUID_WLOCK_UUID_WLOCK(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_UUID_WLOCK_UUID_WLOCK_SHIFT)) & SYSCTL0_UUID_WLOCK_UUID_WLOCK_MASK)
/*! @} */

/*! @name AESKEY_SRCSEL - AES Key Source Select */
/*! @{ */
#define SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_MASK (0x3U)
#define SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_SHIFT (0U)
/*! AESKEY_SRCSEL - AES Key Source Select
 *  0b00..PUF
 *  0b01..PUF
 *  0b10..OTP
 *  0b11..PUF
 */
#define SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_SHIFT)) & SYSCTL0_AESKEY_SRCSEL_AESKEY_SRCSEL_MASK)
/*! @} */

/*! @name OTFADKEY_SRCSEL - OTFAD Key Source Select */
/*! @{ */
#define SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_MASK (0x3U)
#define SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_SHIFT (0U)
/*! OTFADKEY_SRCSEL - OTFAD Key Source Select
 *  0b00..PUF
 *  0b01..PUF
 *  0b10..OTP
 *  0b11..PUF
 */
#define SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_SHIFT)) & SYSCTL0_OTFADKEY_SRCSEL_OTFADKEY_SRCSEL_MASK)
/*! @} */

/*! @name DBG_LOCKEN - Debug Lock Enable */
/*! @{ */
#define SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_MASK       (0xFU)
#define SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_SHIFT      (0U)
/*! DBG_LOCKEN - Debug Write Lock the following registers
 */
#define SYSCTL0_DBG_LOCKEN_DBG_LOCKEN(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_SHIFT)) & SYSCTL0_DBG_LOCKEN_DBG_LOCKEN_MASK)
/*! @} */

/*! @name DBG_FEATURES - Debug Features */
/*! @{ */
#define SYSCTL0_DBG_FEATURES_DBGEN1_MASK         (0x3U)
#define SYSCTL0_DBG_FEATURES_DBGEN1_SHIFT        (0U)
/*! DBGEN1 - CM33 Debug Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_DBGEN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DBGEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DBGEN1_MASK)
#define SYSCTL0_DBG_FEATURES_NIDEN1_MASK         (0xCU)
#define SYSCTL0_DBG_FEATURES_NIDEN1_SHIFT        (2U)
/*! NIDEN1 - CM33 NID Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_NIDEN1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_NIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_NIDEN1_MASK)
#define SYSCTL0_DBG_FEATURES_SPIDEN1_MASK        (0x30U)
#define SYSCTL0_DBG_FEATURES_SPIDEN1_SHIFT       (4U)
/*! SPIDEN1 - CM33 SPID Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_SPIDEN1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_SPIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_SPIDEN1_MASK)
#define SYSCTL0_DBG_FEATURES_SPNIDEN1_MASK       (0xC0U)
#define SYSCTL0_DBG_FEATURES_SPNIDEN1_SHIFT      (6U)
/*! SPNIDEN1 - CM33 SPNIDEN Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_SPNIDEN1(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_SPNIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_SPNIDEN1_MASK)
/*! @} */

/*! @name DBG_FEATURES_DP - Debug Features Duplicate */
/*! @{ */
#define SYSCTL0_DBG_FEATURES_DP_DBGEN1_MASK      (0x3U)
#define SYSCTL0_DBG_FEATURES_DP_DBGEN1_SHIFT     (0U)
/*! DBGEN1 - CM33 Debug Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_DP_DBGEN1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_DBGEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_DBGEN1_MASK)
#define SYSCTL0_DBG_FEATURES_DP_NIDEN1_MASK      (0xCU)
#define SYSCTL0_DBG_FEATURES_DP_NIDEN1_SHIFT     (2U)
/*! NIDEN1 - CM33 NID Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_DP_NIDEN1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_NIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_NIDEN1_MASK)
#define SYSCTL0_DBG_FEATURES_DP_SPIDEN1_MASK     (0x30U)
#define SYSCTL0_DBG_FEATURES_DP_SPIDEN1_SHIFT    (4U)
/*! SPIDEN1 - CM33 SPID Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_DP_SPIDEN1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_SPIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_SPIDEN1_MASK)
#define SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_MASK    (0xC0U)
#define SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_SHIFT   (6U)
/*! SPNIDEN1 - CM33 SPNIDEN Enable Control
 *  0b10..Enabled
 *  0b01..Disabled
 *  0b00..Disabled
 *  0b11..Disabled
 */
#define SYSCTL0_DBG_FEATURES_DP_SPNIDEN1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_SHIFT)) & SYSCTL0_DBG_FEATURES_DP_SPNIDEN1_MASK)
/*! @} */

/*! @name HWUNLOCK_DISABLE - HW Unlock / Disable */
/*! @{ */
#define SYSCTL0_HWUNLOCK_DISABLE_HWUNLOCK_DISABLE_MASK (0xFU)
#define SYSCTL0_HWUNLOCK_DISABLE_HWUNLOCK_DISABLE_SHIFT (0U)
/*! HWUNLOCK_DISABLE - Hardware Unlock Disable
 */
#define SYSCTL0_HWUNLOCK_DISABLE_HWUNLOCK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_HWUNLOCK_DISABLE_HWUNLOCK_DISABLE_SHIFT)) & SYSCTL0_HWUNLOCK_DISABLE_HWUNLOCK_DISABLE_MASK)
/*! @} */

/*! @name CS_PROTTEST - Code Security for TAP Enable */
/*! @{ */
#define SYSCTL0_CS_PROTTEST_CS_PROTTEST_MASK     (0xFFFFFFFFU)
#define SYSCTL0_CS_PROTTEST_CS_PROTTEST_SHIFT    (0U)
/*! CS_PROTTEST - Controls TAP Enable
 */
#define SYSCTL0_CS_PROTTEST_CS_PROTTEST(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CS_PROTTEST_CS_PROTTEST_SHIFT)) & SYSCTL0_CS_PROTTEST_CS_PROTTEST_MASK)
/*! @} */

/*! @name CS_PROTCPU0 - Code Security for CPU0 */
/*! @{ */
#define SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_MASK     (0xFFFFFFFFU)
#define SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_SHIFT    (0U)
/*! CS_PROTCPU0 - Controls M33 AP Enable
 */
#define SYSCTL0_CS_PROTCPU0_CS_PROTCPU0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_SHIFT)) & SYSCTL0_CS_PROTCPU0_CS_PROTCPU0_MASK)
/*! @} */

/*! @name CS_PROTCPU1 - Code Security for CPU1 */
/*! @{ */
#define SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_MASK     (0xFFFFFFFFU)
#define SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_SHIFT    (0U)
/*! CS_PROTCPU1 - Controls AP Enable
 */
#define SYSCTL0_CS_PROTCPU1_CS_PROTCPU1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_SHIFT)) & SYSCTL0_CS_PROTCPU1_CS_PROTCPU1_MASK)
/*! @} */

/*! @name DBG_AUTH_SCRATCH - Debug authorization scratch */
/*! @{ */
#define SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_MASK (0xFFFFFFFFU)
#define SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_SHIFT (0U)
/*! DBG_AUTH_SCRATCH - Debug authorization scratch register for S/W.
 */
#define SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_SHIFT)) & SYSCTL0_DBG_AUTH_SCRATCH_DBG_AUTH_SCRATCH_MASK)
/*! @} */

/*! @name KEY_BLOCK - Key block */
/*! @{ */
#define SYSCTL0_KEY_BLOCK_KEY_BLOCK_MASK         (0xFFFFFFFFU)
#define SYSCTL0_KEY_BLOCK_KEY_BLOCK_SHIFT        (0U)
/*! KEY_BLOCK - PUF key and data output
 */
#define SYSCTL0_KEY_BLOCK_KEY_BLOCK(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL0_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCTL0_KEY_BLOCK_KEY_BLOCK_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group SYSCTL0_Register_Masks */


/* SYSCTL0 - Peripheral instance base addresses */
/** Peripheral SYSCTL0 base address */
#define SYSCTL0_BASE                             (0x40002000u)
/** Peripheral SYSCTL0 base pointer */
#define SYSCTL0                                  ((SYSCTL0_Type *)SYSCTL0_BASE)
/** Array initializer of SYSCTL0 peripheral base addresses */
#define SYSCTL0_BASE_ADDRS                       { SYSCTL0_BASE }
/** Array initializer of SYSCTL0 peripheral base pointers */
#define SYSCTL0_BASE_PTRS                        { SYSCTL0 }

/*!
 * @}
 */ /* end of group SYSCTL0_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- SYSCTL1 Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCTL1_Peripheral_Access_Layer SYSCTL1 Peripheral Access Layer
 * @{
 */

/** SYSCTL1 - Register Layout Typedef */
typedef struct {
  __IO uint32_t UPDATELCKOUT;                      /**< Update Clock Lockout, offset: 0x0 */
       uint8_t RESERVED_0[12];
  __IO uint32_t MCLKPINDIR;                        /**< MCLK direction control, offset: 0x10 */
       uint8_t RESERVED_1[28];
  __IO uint32_t DSPNMISRCSEL;                      /**< DSP NMI source selection, offset: 0x30 */
       uint8_t RESERVED_2[12];
  __IO uint32_t FCCTRLSEL[14];                     /**< Flexcomm control selection, array offset: 0x40, array step: 0x4 */
       uint8_t RESERVED_3[8];
  __IO uint32_t SHAREDCTRLSET[2];                  /**< Shared control set, array offset: 0x80, array step: 0x4 */
       uint8_t RESERVED_4[20];
  __O  uint32_t CONFIG_LCKOUT;                     /**< Configuration Lock-Out, offset: 0x9C */
       uint8_t RESERVED_5[96];
  __IO uint32_t PERICFGENABLE0;                    /**< Peripheral Configuration Enable 0, offset: 0x100 */
       uint8_t RESERVED_6[80];
  __IO uint32_t PERICFGENABLE1;                    /**< Peripheral Configuration Enable 1, offset: 0x154 */
  __IO uint32_t PERICFGENABLE2;                    /**< Peripheral Configuration Enable 2, offset: 0x158 */
       uint8_t RESERVED_7[164];
  __O  uint32_t RXEVPULSEGEN;                      /**< RX Event Pulse Generator, offset: 0x200 */
       uint8_t RESERVED_8[492];
  __IO uint32_t SCRATCH[2];                        /**< Scratch, array offset: 0x3F0, array step: 0x4 */
} SYSCTL1_Type;

/* ----------------------------------------------------------------------------
   -- SYSCTL1 Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SYSCTL1_Register_Masks SYSCTL1 Register Masks
 * @{
 */

/*! @name UPDATELCKOUT - Update Clock Lockout */
/*! @{ */
#define SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_MASK   (0x1U)
#define SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_SHIFT  (0U)
/*! UPDATELCKOUT - Update Clock Lockout
 *  0b0..Normal Mode
 *  0b1..Protected Mode. Cannot be written to. Currently this register does not lock anything
 */
#define SYSCTL1_UPDATELCKOUT_UPDATELCKOUT(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL1_UPDATELCKOUT_UPDATELCKOUT_MASK)
/*! @} */

/*! @name MCLKPINDIR - MCLK direction control */
/*! @{ */
#define SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK       (0x1U)
#define SYSCTL1_MCLKPINDIR_MCLKPINDIR_SHIFT      (0U)
/*! MCLKPINDIR - MCLK direction control
 *  0b0..I2S MCLK is in input direction
 *  0b1..I2S MCLK is in the output direction
 */
#define SYSCTL1_MCLKPINDIR_MCLKPINDIR(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL1_MCLKPINDIR_MCLKPINDIR_SHIFT)) & SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK)
/*! @} */

/*! @name DSPNMISRCSEL - DSP NMI source selection */
/*! @{ */
#define SYSCTL1_DSPNMISRCSEL_NMISRCSEL_MASK      (0x1FU)
#define SYSCTL1_DSPNMISRCSEL_NMISRCSEL_SHIFT     (0U)
/*! NMISRCSEL - DSP NMI source selection
 */
#define SYSCTL1_DSPNMISRCSEL_NMISRCSEL(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_DSPNMISRCSEL_NMISRCSEL_SHIFT)) & SYSCTL1_DSPNMISRCSEL_NMISRCSEL_MASK)
#define SYSCTL1_DSPNMISRCSEL_NMIEN_MASK          (0x80000000U)
#define SYSCTL1_DSPNMISRCSEL_NMIEN_SHIFT         (31U)
/*! NMIEN - NMI Enable
 *  0b0..Disable NMI Interrupt
 *  0b1..Enable NMI Interrupt
 */
#define SYSCTL1_DSPNMISRCSEL_NMIEN(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL1_DSPNMISRCSEL_NMIEN_SHIFT)) & SYSCTL1_DSPNMISRCSEL_NMIEN_MASK)
/*! @} */

/*! @name FCCTRLSEL - Flexcomm control selection */
/*! @{ */
#define SYSCTL1_FCCTRLSEL_SCKINSEL_MASK          (0x3U)
#define SYSCTL1_FCCTRLSEL_SCKINSEL_SHIFT         (0U)
/*! SCKINSEL - SCK IN Select
 *  0b00..Original FLEXCOMM I2S signals
 *  0b01..Shared Set0 I2S signals
 *  0b10..Shared Set1 I2S signals
 *  0b11..Reserved
 */
#define SYSCTL1_FCCTRLSEL_SCKINSEL(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_SCKINSEL_MASK)
#define SYSCTL1_FCCTRLSEL_WSINSEL_MASK           (0x300U)
#define SYSCTL1_FCCTRLSEL_WSINSEL_SHIFT          (8U)
/*! WSINSEL - SCK IN Select
 *  0b00..Original FLEXCOMM I2S signals
 *  0b01..Shared Set0 I2S signals
 *  0b10..Shared Set1 I2S signals
 *  0b11..Reserved
 */
#define SYSCTL1_FCCTRLSEL_WSINSEL(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_WSINSEL_MASK)
#define SYSCTL1_FCCTRLSEL_DATAINSEL_MASK         (0x30000U)
#define SYSCTL1_FCCTRLSEL_DATAINSEL_SHIFT        (16U)
/*! DATAINSEL - DATA IN Select
 *  0b00..Original FLEXCOMM I2S signals
 *  0b01..Shared Set0 I2S signals
 *  0b10..Shared Set1 I2S signals
 *  0b11..Reserved
 */
#define SYSCTL1_FCCTRLSEL_DATAINSEL(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_DATAINSEL_MASK)
#define SYSCTL1_FCCTRLSEL_DATAOUTSEL_MASK        (0x3000000U)
#define SYSCTL1_FCCTRLSEL_DATAOUTSEL_SHIFT       (24U)
/*! DATAOUTSEL - DATA OUT Select
 *  0b00..Original FLEXCOMM I2S signals
 *  0b01..Shared Set0 I2S signals
 *  0b10..Shared Set1 I2S signals
 *  0b11..Reserved
 */
#define SYSCTL1_FCCTRLSEL_DATAOUTSEL(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL1_FCCTRLSEL_DATAOUTSEL_MASK)
/*! @} */

/* The count of SYSCTL1_FCCTRLSEL */
#define SYSCTL1_FCCTRLSEL_COUNT                  (14U)

/*! @name SHAREDCTRLSET - Shared control set */
/*! @{ */
#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_MASK  (0x7U)
#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U)
/*! SHAREDSCKSEL - Shared SCK Select
 *  0b000..FLEXCOMM0
 *  0b001..FLEXCOMM1
 *  0b010..FLEXCOMM2
 *  0b011..FLEXCOMM3
 *  0b100..FLEXCOMM4
 *  0b101..FLEXCOMM5
 *  0b110..FLEXCOMM6
 *  0b111..FLEXCOMM7
 */
#define SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL_MASK)
#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_MASK   (0x70U)
#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_SHIFT  (4U)
/*! SHAREDWSSEL - Shared WS Select:
 *  0b000..FLEXCOMM0
 *  0b001..FLEXCOMM1
 *  0b010..FLEXCOMM2
 *  0b011..FLEXCOMM3
 *  0b100..FLEXCOMM4
 *  0b101..FLEXCOMM5
 *  0b110..FLEXCOMM6
 *  0b111..FLEXCOMM7
 */
#define SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL_MASK)
#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U)
#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)
/*! SHAREDDATASEL - Shared DATA Select:
 *  0b000..FLEXCOMM0
 *  0b001..FLEXCOMM1
 *  0b010..FLEXCOMM2
 *  0b011..FLEXCOMM3
 *  0b100..FLEXCOMM4
 *  0b101..FLEXCOMM5
 *  0b110..FLEXCOMM6
 *  0b111..FLEXCOMM7
 */
#define SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(x)   (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_MASK  (0x10000U)
#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U)
/*! FC0DATAOUTEN - FLEXCOMM0 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC0DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_MASK  (0x20000U)
#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U)
/*! FC1DATAOUTEN - FLEXCOMM1 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_MASK  (0x40000U)
#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U)
/*! FC2DATAOUTEN - FLEXCOMM2 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC2DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_MASK  (0x80000U)
#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U)
/*! FC3DATAOUTEN - FLEXCOMM3 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_MASK  (0x100000U)
#define SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U)
/*! FC4DATAOUTEN - FLEXCOMM4 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC4DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_MASK  (0x200000U)
#define SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U)
/*! FC5DATAOUTEN - FLEXCOMM5 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC5DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_MASK  (0x400000U)
#define SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U)
/*! FC6DATAOUTEN - FLEXCOMM6 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC6DATAOUTEN_MASK)
#define SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_MASK  (0x800000U)
#define SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U)
/*! FC7DATAOUTEN - FLEXCOMM7 DATAOUT Output Enable:
 *  0b0..Input
 *  0b1..Output
 */
#define SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN(x)    (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL1_SHAREDCTRLSET_FC7DATAOUTEN_MASK)
/*! @} */

/* The count of SYSCTL1_SHAREDCTRLSET */
#define SYSCTL1_SHAREDCTRLSET_COUNT              (2U)

/*! @name CONFIG_LCKOUT - Configuration Lock-Out */
/*! @{ */
#define SYSCTL1_CONFIG_LCKOUT_LCKOUT_MASK        (0x1U)
#define SYSCTL1_CONFIG_LCKOUT_LCKOUT_SHIFT       (0U)
/*! LCKOUT - Configuration Lock-Out
 *  0b0..Enable Write to Configuration Registers
 *  0b1..Disable Write to Configuration Registers
 */
#define SYSCTL1_CONFIG_LCKOUT_LCKOUT(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_CONFIG_LCKOUT_LCKOUT_SHIFT)) & SYSCTL1_CONFIG_LCKOUT_LCKOUT_MASK)
/*! @} */

/*! @name PERICFGENABLE0 - Peripheral Configuration Enable 0 */
/*! @{ */
#define SYSCTL1_PERICFGENABLE0_Flexcomm0_MASK    (0x100U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm0_SHIFT   (8U)
/*! Flexcomm0 - Flexcomm0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm0(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm0_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm0_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm1_MASK    (0x200U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm1_SHIFT   (9U)
/*! Flexcomm1 - Flexcomm1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm1(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm1_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm1_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm2_MASK    (0x400U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm2_SHIFT   (10U)
/*! Flexcomm2 - Flexcomm2
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm2(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm2_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm2_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm3_MASK    (0x800U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm3_SHIFT   (11U)
/*! Flexcomm3 - Flexcomm3
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm3(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm3_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm3_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm4_MASK    (0x1000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm4_SHIFT   (12U)
/*! Flexcomm4 - Flexcomm4
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm4(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm4_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm4_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm5_MASK    (0x2000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm5_SHIFT   (13U)
/*! Flexcomm5 - Flexcomm5
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm5(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm5_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm5_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm6_MASK    (0x4000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm6_SHIFT   (14U)
/*! Flexcomm6 - Flexcomm6
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm6(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm6_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm6_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm7_MASK    (0x8000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm7_SHIFT   (15U)
/*! Flexcomm7 - Flexcomm7
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm7(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm7_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm7_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm8_MASK    (0x10000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm8_SHIFT   (16U)
/*! Flexcomm8 - Flexcomm8
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm8(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm8_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm8_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm9_MASK    (0x20000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm9_SHIFT   (17U)
/*! Flexcomm9 - Flexcomm9
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm9(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm9_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm9_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm10_MASK   (0x40000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm10_SHIFT  (18U)
/*! Flexcomm10 - Flexcomm10
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm10(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm10_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm10_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm11_MASK   (0x80000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm11_SHIFT  (19U)
/*! Flexcomm11 - Flexcomm11
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm11(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm11_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm11_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm12_MASK   (0x100000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm12_SHIFT  (20U)
/*! Flexcomm12 - Flexcomm12
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm12(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm12_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm12_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm13_MASK   (0x200000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm13_SHIFT  (21U)
/*! Flexcomm13 - Flexcomm13
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm13(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm13_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm13_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm14_SPI0_MASK (0x400000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm14_SPI0_SHIFT (22U)
/*! Flexcomm14_SPI0 - Flexcomm14 SPI0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm14_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm14_SPI0_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm14_SPI0_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm15_I2C_MASK (0x800000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm15_I2C_SHIFT (23U)
/*! Flexcomm15_I2C - Flexcomm15 I2C
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm15_I2C(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm15_I2C_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm15_I2C_MASK)
#define SYSCTL1_PERICFGENABLE0_DMIC0_MASK        (0x1000000U)
#define SYSCTL1_PERICFGENABLE0_DMIC0_SHIFT       (24U)
/*! DMIC0 - DMIC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_DMIC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_DMIC0_SHIFT)) & SYSCTL1_PERICFGENABLE0_DMIC0_MASK)
#define SYSCTL1_PERICFGENABLE0_Flexcomm16_SPI1_MASK (0x2000000U)
#define SYSCTL1_PERICFGENABLE0_Flexcomm16_SPI1_SHIFT (25U)
/*! Flexcomm16_SPI1 - Flexcomm16 SPI1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_Flexcomm16_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_Flexcomm16_SPI1_SHIFT)) & SYSCTL1_PERICFGENABLE0_Flexcomm16_SPI1_MASK)
#define SYSCTL1_PERICFGENABLE0_FlexIO_MASK       (0x20000000U)
#define SYSCTL1_PERICFGENABLE0_FlexIO_SHIFT      (29U)
/*! FlexIO - FlexIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE0_FlexIO(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE0_FlexIO_SHIFT)) & SYSCTL1_PERICFGENABLE0_FlexIO_MASK)
/*! @} */

/*! @name PERICFGENABLE1 - Peripheral Configuration Enable 1 */
/*! @{ */
#define SYSCTL1_PERICFGENABLE1_HSGPIO0_MASK      (0x1U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO0_SHIFT     (0U)
/*! HSGPIO0 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO0(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO0_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO0_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO1_MASK      (0x2U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO1_SHIFT     (1U)
/*! HSGPIO1 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO1(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO1_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO1_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO2_MASK      (0x4U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO2_SHIFT     (2U)
/*! HSGPIO2 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO2(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO2_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO2_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO3_MASK      (0x8U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO3_SHIFT     (3U)
/*! HSGPIO3 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO3(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO3_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO3_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO4_MASK      (0x10U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO4_SHIFT     (4U)
/*! HSGPIO4 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO4(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO4_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO4_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO5_MASK      (0x20U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO5_SHIFT     (5U)
/*! HSGPIO5 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO5(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO5_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO5_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO6_MASK      (0x40U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO6_SHIFT     (6U)
/*! HSGPIO6 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO6(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO6_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO6_MASK)
#define SYSCTL1_PERICFGENABLE1_HSGPIO7_MASK      (0x80U)
#define SYSCTL1_PERICFGENABLE1_HSGPIO7_SHIFT     (7U)
/*! HSGPIO7 - High Speed GPIO
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_HSGPIO7(x)        (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_HSGPIO7_SHIFT)) & SYSCTL1_PERICFGENABLE1_HSGPIO7_MASK)
#define SYSCTL1_PERICFGENABLE1_CRC_MASK          (0x10000U)
#define SYSCTL1_PERICFGENABLE1_CRC_SHIFT         (16U)
/*! CRC - CRC
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_CRC(x)            (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_CRC_SHIFT)) & SYSCTL1_PERICFGENABLE1_CRC_MASK)
#define SYSCTL1_PERICFGENABLE1_DMAC0_MASK        (0x800000U)
#define SYSCTL1_PERICFGENABLE1_DMAC0_SHIFT       (23U)
/*! DMAC0 - DMAC0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_DMAC0(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_DMAC0_SHIFT)) & SYSCTL1_PERICFGENABLE1_DMAC0_MASK)
#define SYSCTL1_PERICFGENABLE1_DMAC1_MASK        (0x1000000U)
#define SYSCTL1_PERICFGENABLE1_DMAC1_SHIFT       (24U)
/*! DMAC1 - DMAC1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_DMAC1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_DMAC1_SHIFT)) & SYSCTL1_PERICFGENABLE1_DMAC1_MASK)
#define SYSCTL1_PERICFGENABLE1_MU_MASK           (0x10000000U)
#define SYSCTL1_PERICFGENABLE1_MU_SHIFT          (28U)
/*! MU - MU
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_MU(x)             (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_MU_SHIFT)) & SYSCTL1_PERICFGENABLE1_MU_MASK)
#define SYSCTL1_PERICFGENABLE1_SEMA_MASK         (0x20000000U)
#define SYSCTL1_PERICFGENABLE1_SEMA_SHIFT        (29U)
/*! SEMA - SEMA
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_SEMA(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_SEMA_SHIFT)) & SYSCTL1_PERICFGENABLE1_SEMA_MASK)
#define SYSCTL1_PERICFGENABLE1_FREQME_MASK       (0x80000000U)
#define SYSCTL1_PERICFGENABLE1_FREQME_SHIFT      (31U)
/*! FREQME - FREQME
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE1_FREQME(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE1_FREQME_SHIFT)) & SYSCTL1_PERICFGENABLE1_FREQME_MASK)
/*! @} */

/*! @name PERICFGENABLE2 - Peripheral Configuration Enable 2 */
/*! @{ */
#define SYSCTL1_PERICFGENABLE2_CT32BIT0_MASK     (0x1U)
#define SYSCTL1_PERICFGENABLE2_CT32BIT0_SHIFT    (0U)
/*! CT32BIT0 - CT32BIT0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_CT32BIT0(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_CT32BIT0_SHIFT)) & SYSCTL1_PERICFGENABLE2_CT32BIT0_MASK)
#define SYSCTL1_PERICFGENABLE2_CT32BIT1_MASK     (0x2U)
#define SYSCTL1_PERICFGENABLE2_CT32BIT1_SHIFT    (1U)
/*! CT32BIT1 - CT32BIT1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_CT32BIT1(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_CT32BIT1_SHIFT)) & SYSCTL1_PERICFGENABLE2_CT32BIT1_MASK)
#define SYSCTL1_PERICFGENABLE2_CT32BIT2_MASK     (0x4U)
#define SYSCTL1_PERICFGENABLE2_CT32BIT2_SHIFT    (2U)
/*! CT32BIT2 - CT32BIT2
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_CT32BIT2(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_CT32BIT2_SHIFT)) & SYSCTL1_PERICFGENABLE2_CT32BIT2_MASK)
#define SYSCTL1_PERICFGENABLE2_CT32BIT3_MASK     (0x8U)
#define SYSCTL1_PERICFGENABLE2_CT32BIT3_SHIFT    (3U)
/*! CT32BIT3 - CT32BIT3
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_CT32BIT3(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_CT32BIT3_SHIFT)) & SYSCTL1_PERICFGENABLE2_CT32BIT3_MASK)
#define SYSCTL1_PERICFGENABLE2_CT32BIT4_MASK     (0x10U)
#define SYSCTL1_PERICFGENABLE2_CT32BIT4_SHIFT    (4U)
/*! CT32BIT4 - CT32BIT4
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_CT32BIT4(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_CT32BIT4_SHIFT)) & SYSCTL1_PERICFGENABLE2_CT32BIT4_MASK)
#define SYSCTL1_PERICFGENABLE2_RTC_LITE_MASK     (0x80U)
#define SYSCTL1_PERICFGENABLE2_RTC_LITE_SHIFT    (7U)
/*! RTC_LITE - RTC Lite
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_RTC_LITE(x)       (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_RTC_LITE_SHIFT)) & SYSCTL1_PERICFGENABLE2_RTC_LITE_MASK)
#define SYSCTL1_PERICFGENABLE2_MRT0_MASK         (0x100U)
#define SYSCTL1_PERICFGENABLE2_MRT0_SHIFT        (8U)
/*! MRT0 - MRT0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_MRT0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_MRT0_SHIFT)) & SYSCTL1_PERICFGENABLE2_MRT0_MASK)
#define SYSCTL1_PERICFGENABLE2_WWDT1_MASK        (0x400U)
#define SYSCTL1_PERICFGENABLE2_WWDT1_SHIFT       (10U)
/*! WWDT1 - WWDT1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_WWDT1(x)          (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_WWDT1_SHIFT)) & SYSCTL1_PERICFGENABLE2_WWDT1_MASK)
#define SYSCTL1_PERICFGENABLE2_I3C0_MASK         (0x10000U)
#define SYSCTL1_PERICFGENABLE2_I3C0_SHIFT        (16U)
/*! I3C0 - I3C0
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_I3C0(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_I3C0_SHIFT)) & SYSCTL1_PERICFGENABLE2_I3C0_MASK)
#define SYSCTL1_PERICFGENABLE2_I3C1_MASK         (0x20000U)
#define SYSCTL1_PERICFGENABLE2_I3C1_SHIFT        (17U)
/*! I3C1 - I3C1
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_I3C1(x)           (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_I3C1_SHIFT)) & SYSCTL1_PERICFGENABLE2_I3C1_MASK)
#define SYSCTL1_PERICFGENABLE2_GPIO0GINT_MASK    (0x10000000U)
#define SYSCTL1_PERICFGENABLE2_GPIO0GINT_SHIFT   (28U)
/*! GPIO0GINT - GPIO0GINT
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_GPIO0GINT(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_GPIO0GINT_SHIFT)) & SYSCTL1_PERICFGENABLE2_GPIO0GINT_MASK)
#define SYSCTL1_PERICFGENABLE2_GPIO1GINT_MASK    (0x20000000U)
#define SYSCTL1_PERICFGENABLE2_GPIO1GINT_SHIFT   (29U)
/*! GPIO1GINT - GPIO1GINT
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_GPIO1GINT(x)      (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_GPIO1GINT_SHIFT)) & SYSCTL1_PERICFGENABLE2_GPIO1GINT_MASK)
#define SYSCTL1_PERICFGENABLE2_GPIOINTCTL_MASK   (0x40000000U)
#define SYSCTL1_PERICFGENABLE2_GPIOINTCTL_SHIFT  (30U)
/*! GPIOINTCTL - GPIOINTCTL
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_GPIOINTCTL(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_GPIOINTCTL_SHIFT)) & SYSCTL1_PERICFGENABLE2_GPIOINTCTL_MASK)
#define SYSCTL1_PERICFGENABLE2_PIMCTL_MASK       (0x80000000U)
#define SYSCTL1_PERICFGENABLE2_PIMCTL_SHIFT      (31U)
/*! PIMCTL - IOPCTL
 *  0b0..Disable
 *  0b1..Enable
 */
#define SYSCTL1_PERICFGENABLE2_PIMCTL(x)         (((uint32_t)(((uint32_t)(x)) << SYSCTL1_PERICFGENABLE2_PIMCTL_SHIFT)) & SYSCTL1_PERICFGENABLE2_PIMCTL_MASK)
/*! @} */

/*! @name RXEVPULSEGEN - RX Event Pulse Generator */
/*! @{ */
#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_MASK   (0x1U)
#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT  (0U)
/*! RXEVPULSEGEN - RX Event Pulse Generator
 *  0b0..No effect
 *  0b1..Pulse RXEV High for one PSCLK cycle
 */
#define SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN(x)     (((uint32_t)(((uint32_t)(x)) << SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_SHIFT)) & SYSCTL1_RXEVPULSEGEN_RXEVPULSEGEN_MASK)
/*! @} */

/*! @name SCRATCH - Scratch */
/*! @{ */
#define SYSCTL1_SCRATCH_Scratch_MASK             (0xFFFFFFFFU)
#define SYSCTL1_SCRATCH_Scratch_SHIFT            (0U)
/*! Scratch - Scratch
 */
#define SYSCTL1_SCRATCH_Scratch(x)               (((uint32_t)(((uint32_t)(x)) << SYSCTL1_SCRATCH_Scratch_SHIFT)) & SYSCTL1_SCRATCH_Scratch_MASK)
/*! @} */

/* The count of SYSCTL1_SCRATCH */
#define SYSCTL1_SCRATCH_COUNT                    (2U)


/*!
 * @}
 */ /* end of group SYSCTL1_Register_Masks */


/* SYSCTL1 - Peripheral instance base addresses */
/** Peripheral SYSCTL1 base address */
#define SYSCTL1_BASE                             (0x40022000u)
/** Peripheral SYSCTL1 base pointer */
#define SYSCTL1                                  ((SYSCTL1_Type *)SYSCTL1_BASE)
/** Array initializer of SYSCTL1 peripheral base addresses */
#define SYSCTL1_BASE_ADDRS                       { SYSCTL1_BASE }
/** Array initializer of SYSCTL1 peripheral base pointers */
#define SYSCTL1_BASE_PTRS                        { SYSCTL1 }

/*!
 * @}
 */ /* end of group SYSCTL1_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- TRNG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
 * @{
 */

/** TRNG - Register Layout Typedef */
typedef struct {
  __IO uint32_t MCTL;                              /**< Miscellaneous Control Register, offset: 0x0 */
  __IO uint32_t SCMISC;                            /**< Statistical Check Miscellaneous Register, offset: 0x4 */
  __IO uint32_t PKRRNG;                            /**< Poker Range Register, offset: 0x8 */
  union {                                          /* offset: 0xC */
    __IO uint32_t PKRMAX;                            /**< Poker Maximum Limit Register, offset: 0xC */
    __I  uint32_t PKRSQ;                             /**< Poker Square Calculation Result Register, offset: 0xC */
  };
  __IO uint32_t SDCTL;                             /**< Seed Control Register, offset: 0x10 */
  union {                                          /* offset: 0x14 */
    __IO uint32_t SBLIM;                             /**< Sparse Bit Limit Register, offset: 0x14 */
    __I  uint32_t TOTSAM;                            /**< Total Samples Register, offset: 0x14 */
  };
  __IO uint32_t FRQMIN;                            /**< Frequency Count Minimum Limit Register, offset: 0x18 */
  union {                                          /* offset: 0x1C */
    __I  uint32_t FRQCNT;                            /**< Frequency Count Register, offset: 0x1C */
    __IO uint32_t FRQMAX;                            /**< Frequency Count Maximum Limit Register, offset: 0x1C */
  };
  union {                                          /* offset: 0x20 */
    __I  uint32_t SCMC;                              /**< Statistical Check Monobit Count Register, offset: 0x20 */
    __IO uint32_t SCML;                              /**< Statistical Check Monobit Limit Register, offset: 0x20 */
  };
  union {                                          /* offset: 0x24 */
    __I  uint32_t SCR1C;                             /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
    __IO uint32_t SCR1L;                             /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
  };
  union {                                          /* offset: 0x28 */
    __I  uint32_t SCR2C;                             /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
    __IO uint32_t SCR2L;                             /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
  };
  union {                                          /* offset: 0x2C */
    __I  uint32_t SCR3C;                             /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
    __IO uint32_t SCR3L;                             /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
  };
  union {                                          /* offset: 0x30 */
    __I  uint32_t SCR4C;                             /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
    __IO uint32_t SCR4L;                             /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
  };
  union {                                          /* offset: 0x34 */
    __I  uint32_t SCR5C;                             /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
    __IO uint32_t SCR5L;                             /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
  };
  union {                                          /* offset: 0x38 */
    __I  uint32_t SCR6PC;                            /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
    __IO uint32_t SCR6PL;                            /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
  };
  __I  uint32_t STATUS;                            /**< Status Register, offset: 0x3C */
  __I  uint32_t ENT[16];                           /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
  __I  uint32_t PKRCNT10;                          /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
  __I  uint32_t PKRCNT32;                          /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
  __I  uint32_t PKRCNT54;                          /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
  __I  uint32_t PKRCNT76;                          /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
  __I  uint32_t PKRCNT98;                          /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
  __I  uint32_t PKRCNTBA;                          /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
  __I  uint32_t PKRCNTDC;                          /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
  __I  uint32_t PKRCNTFE;                          /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
  __IO uint32_t SEC_CFG;                           /**< Security Configuration Register, offset: 0xA0 */
  __IO uint32_t INT_CTRL;                          /**< Interrupt Control Register, offset: 0xA4 */
  __IO uint32_t INT_MASK;                          /**< Mask Register, offset: 0xA8 */
  __I  uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0xAC */
       uint8_t RESERVED_0[64];
  __I  uint32_t VID1;                              /**< Version ID Register (MS), offset: 0xF0 */
  __I  uint32_t VID2;                              /**< Version ID Register (LS), offset: 0xF4 */
} TRNG_Type;

/* ----------------------------------------------------------------------------
   -- TRNG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup TRNG_Register_Masks TRNG Register Masks
 * @{
 */

/*! @name MCTL - Miscellaneous Control Register */
/*! @{ */
#define TRNG_MCTL_SAMP_MODE_MASK                 (0x3U)
#define TRNG_MCTL_SAMP_MODE_SHIFT                (0U)
/*! SAMP_MODE
 *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
 *  0b01..use raw data into both Entropy shifter and Statistical Checker
 *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
 *  0b11..undefined/reserved.
 */
#define TRNG_MCTL_SAMP_MODE(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
#define TRNG_MCTL_OSC_DIV_MASK                   (0xCU)
#define TRNG_MCTL_OSC_DIV_SHIFT                  (2U)
/*! OSC_DIV
 *  0b00..use ring oscillator with no divide
 *  0b01..use ring oscillator divided-by-2
 *  0b10..use ring oscillator divided-by-4
 *  0b11..use ring oscillator divided-by-8
 */
#define TRNG_MCTL_OSC_DIV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
#define TRNG_MCTL_UNUSED4_MASK                   (0x10U)
#define TRNG_MCTL_UNUSED4_SHIFT                  (4U)
#define TRNG_MCTL_UNUSED4(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
#define TRNG_MCTL_TRNG_ACC_MASK                  (0x20U)
#define TRNG_MCTL_TRNG_ACC_SHIFT                 (5U)
#define TRNG_MCTL_TRNG_ACC(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
#define TRNG_MCTL_RST_DEF_MASK                   (0x40U)
#define TRNG_MCTL_RST_DEF_SHIFT                  (6U)
#define TRNG_MCTL_RST_DEF(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
#define TRNG_MCTL_FOR_SCLK_MASK                  (0x80U)
#define TRNG_MCTL_FOR_SCLK_SHIFT                 (7U)
#define TRNG_MCTL_FOR_SCLK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
#define TRNG_MCTL_FCT_FAIL_MASK                  (0x100U)
#define TRNG_MCTL_FCT_FAIL_SHIFT                 (8U)
#define TRNG_MCTL_FCT_FAIL(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
#define TRNG_MCTL_FCT_VAL_MASK                   (0x200U)
#define TRNG_MCTL_FCT_VAL_SHIFT                  (9U)
#define TRNG_MCTL_FCT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
#define TRNG_MCTL_ENT_VAL_MASK                   (0x400U)
#define TRNG_MCTL_ENT_VAL_SHIFT                  (10U)
#define TRNG_MCTL_ENT_VAL(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
#define TRNG_MCTL_TST_OUT_MASK                   (0x800U)
#define TRNG_MCTL_TST_OUT_SHIFT                  (11U)
#define TRNG_MCTL_TST_OUT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
#define TRNG_MCTL_ERR_MASK                       (0x1000U)
#define TRNG_MCTL_ERR_SHIFT                      (12U)
#define TRNG_MCTL_ERR(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
#define TRNG_MCTL_TSTOP_OK_MASK                  (0x2000U)
#define TRNG_MCTL_TSTOP_OK_SHIFT                 (13U)
#define TRNG_MCTL_TSTOP_OK(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
#define TRNG_MCTL_PRGM_MASK                      (0x10000U)
#define TRNG_MCTL_PRGM_SHIFT                     (16U)
#define TRNG_MCTL_PRGM(x)                        (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
/*! @} */

/*! @name SCMISC - Statistical Check Miscellaneous Register */
/*! @{ */
#define TRNG_SCMISC_LRUN_MAX_MASK                (0xFFU)
#define TRNG_SCMISC_LRUN_MAX_SHIFT               (0U)
#define TRNG_SCMISC_LRUN_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
#define TRNG_SCMISC_RTY_CT_MASK                  (0xF0000U)
#define TRNG_SCMISC_RTY_CT_SHIFT                 (16U)
#define TRNG_SCMISC_RTY_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
/*! @} */

/*! @name PKRRNG - Poker Range Register */
/*! @{ */
#define TRNG_PKRRNG_PKR_RNG_MASK                 (0xFFFFU)
#define TRNG_PKRRNG_PKR_RNG_SHIFT                (0U)
#define TRNG_PKRRNG_PKR_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
/*! @} */

/*! @name PKRMAX - Poker Maximum Limit Register */
/*! @{ */
#define TRNG_PKRMAX_PKR_MAX_MASK                 (0xFFFFFFU)
#define TRNG_PKRMAX_PKR_MAX_SHIFT                (0U)
/*! PKR_MAX - Poker Maximum Limit.
 */
#define TRNG_PKRMAX_PKR_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
/*! @} */

/*! @name PKRSQ - Poker Square Calculation Result Register */
/*! @{ */
#define TRNG_PKRSQ_PKR_SQ_MASK                   (0xFFFFFFU)
#define TRNG_PKRSQ_PKR_SQ_SHIFT                  (0U)
/*! PKR_SQ - Poker Square Calculation Result.
 */
#define TRNG_PKRSQ_PKR_SQ(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
/*! @} */

/*! @name SDCTL - Seed Control Register */
/*! @{ */
#define TRNG_SDCTL_SAMP_SIZE_MASK                (0xFFFFU)
#define TRNG_SDCTL_SAMP_SIZE_SHIFT               (0U)
#define TRNG_SDCTL_SAMP_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
#define TRNG_SDCTL_ENT_DLY_MASK                  (0xFFFF0000U)
#define TRNG_SDCTL_ENT_DLY_SHIFT                 (16U)
#define TRNG_SDCTL_ENT_DLY(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
/*! @} */

/*! @name SBLIM - Sparse Bit Limit Register */
/*! @{ */
#define TRNG_SBLIM_SB_LIM_MASK                   (0x3FFU)
#define TRNG_SBLIM_SB_LIM_SHIFT                  (0U)
#define TRNG_SBLIM_SB_LIM(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
/*! @} */

/*! @name TOTSAM - Total Samples Register */
/*! @{ */
#define TRNG_TOTSAM_TOT_SAM_MASK                 (0xFFFFFU)
#define TRNG_TOTSAM_TOT_SAM_SHIFT                (0U)
#define TRNG_TOTSAM_TOT_SAM(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
/*! @} */

/*! @name FRQMIN - Frequency Count Minimum Limit Register */
/*! @{ */
#define TRNG_FRQMIN_FRQ_MIN_MASK                 (0x3FFFFFU)
#define TRNG_FRQMIN_FRQ_MIN_SHIFT                (0U)
#define TRNG_FRQMIN_FRQ_MIN(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
/*! @} */

/*! @name FRQCNT - Frequency Count Register */
/*! @{ */
#define TRNG_FRQCNT_FRQ_CT_MASK                  (0x3FFFFFU)
#define TRNG_FRQCNT_FRQ_CT_SHIFT                 (0U)
#define TRNG_FRQCNT_FRQ_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
/*! @} */

/*! @name FRQMAX - Frequency Count Maximum Limit Register */
/*! @{ */
#define TRNG_FRQMAX_FRQ_MAX_MASK                 (0x3FFFFFU)
#define TRNG_FRQMAX_FRQ_MAX_SHIFT                (0U)
#define TRNG_FRQMAX_FRQ_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
/*! @} */

/*! @name SCMC - Statistical Check Monobit Count Register */
/*! @{ */
#define TRNG_SCMC_MONO_CT_MASK                   (0xFFFFU)
#define TRNG_SCMC_MONO_CT_SHIFT                  (0U)
#define TRNG_SCMC_MONO_CT(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
/*! @} */

/*! @name SCML - Statistical Check Monobit Limit Register */
/*! @{ */
#define TRNG_SCML_MONO_MAX_MASK                  (0xFFFFU)
#define TRNG_SCML_MONO_MAX_SHIFT                 (0U)
#define TRNG_SCML_MONO_MAX(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
#define TRNG_SCML_MONO_RNG_MASK                  (0xFFFF0000U)
#define TRNG_SCML_MONO_RNG_SHIFT                 (16U)
#define TRNG_SCML_MONO_RNG(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
/*! @} */

/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
/*! @{ */
#define TRNG_SCR1C_R1_0_CT_MASK                  (0x7FFFU)
#define TRNG_SCR1C_R1_0_CT_SHIFT                 (0U)
#define TRNG_SCR1C_R1_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
#define TRNG_SCR1C_R1_1_CT_MASK                  (0x7FFF0000U)
#define TRNG_SCR1C_R1_1_CT_SHIFT                 (16U)
#define TRNG_SCR1C_R1_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
/*! @} */

/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
/*! @{ */
#define TRNG_SCR1L_RUN1_MAX_MASK                 (0x7FFFU)
#define TRNG_SCR1L_RUN1_MAX_SHIFT                (0U)
#define TRNG_SCR1L_RUN1_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
#define TRNG_SCR1L_RUN1_RNG_MASK                 (0x7FFF0000U)
#define TRNG_SCR1L_RUN1_RNG_SHIFT                (16U)
#define TRNG_SCR1L_RUN1_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
/*! @} */

/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
/*! @{ */
#define TRNG_SCR2C_R2_0_CT_MASK                  (0x3FFFU)
#define TRNG_SCR2C_R2_0_CT_SHIFT                 (0U)
#define TRNG_SCR2C_R2_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
#define TRNG_SCR2C_R2_1_CT_MASK                  (0x3FFF0000U)
#define TRNG_SCR2C_R2_1_CT_SHIFT                 (16U)
#define TRNG_SCR2C_R2_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
/*! @} */

/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
/*! @{ */
#define TRNG_SCR2L_RUN2_MAX_MASK                 (0x3FFFU)
#define TRNG_SCR2L_RUN2_MAX_SHIFT                (0U)
#define TRNG_SCR2L_RUN2_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
#define TRNG_SCR2L_RUN2_RNG_MASK                 (0x3FFF0000U)
#define TRNG_SCR2L_RUN2_RNG_SHIFT                (16U)
#define TRNG_SCR2L_RUN2_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
/*! @} */

/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
/*! @{ */
#define TRNG_SCR3C_R3_0_CT_MASK                  (0x1FFFU)
#define TRNG_SCR3C_R3_0_CT_SHIFT                 (0U)
#define TRNG_SCR3C_R3_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
#define TRNG_SCR3C_R3_1_CT_MASK                  (0x1FFF0000U)
#define TRNG_SCR3C_R3_1_CT_SHIFT                 (16U)
#define TRNG_SCR3C_R3_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
/*! @} */

/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
/*! @{ */
#define TRNG_SCR3L_RUN3_MAX_MASK                 (0x1FFFU)
#define TRNG_SCR3L_RUN3_MAX_SHIFT                (0U)
#define TRNG_SCR3L_RUN3_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
#define TRNG_SCR3L_RUN3_RNG_MASK                 (0x1FFF0000U)
#define TRNG_SCR3L_RUN3_RNG_SHIFT                (16U)
#define TRNG_SCR3L_RUN3_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
/*! @} */

/*! @name SCR4C - Statistical Check Run Length 4 Count Register */
/*! @{ */
#define TRNG_SCR4C_R4_0_CT_MASK                  (0xFFFU)
#define TRNG_SCR4C_R4_0_CT_SHIFT                 (0U)
#define TRNG_SCR4C_R4_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
#define TRNG_SCR4C_R4_1_CT_MASK                  (0xFFF0000U)
#define TRNG_SCR4C_R4_1_CT_SHIFT                 (16U)
#define TRNG_SCR4C_R4_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
/*! @} */

/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
/*! @{ */
#define TRNG_SCR4L_RUN4_MAX_MASK                 (0xFFFU)
#define TRNG_SCR4L_RUN4_MAX_SHIFT                (0U)
#define TRNG_SCR4L_RUN4_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
#define TRNG_SCR4L_RUN4_RNG_MASK                 (0xFFF0000U)
#define TRNG_SCR4L_RUN4_RNG_SHIFT                (16U)
#define TRNG_SCR4L_RUN4_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
/*! @} */

/*! @name SCR5C - Statistical Check Run Length 5 Count Register */
/*! @{ */
#define TRNG_SCR5C_R5_0_CT_MASK                  (0x7FFU)
#define TRNG_SCR5C_R5_0_CT_SHIFT                 (0U)
#define TRNG_SCR5C_R5_0_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
#define TRNG_SCR5C_R5_1_CT_MASK                  (0x7FF0000U)
#define TRNG_SCR5C_R5_1_CT_SHIFT                 (16U)
#define TRNG_SCR5C_R5_1_CT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
/*! @} */

/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
/*! @{ */
#define TRNG_SCR5L_RUN5_MAX_MASK                 (0x7FFU)
#define TRNG_SCR5L_RUN5_MAX_SHIFT                (0U)
#define TRNG_SCR5L_RUN5_MAX(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
#define TRNG_SCR5L_RUN5_RNG_MASK                 (0x7FF0000U)
#define TRNG_SCR5L_RUN5_RNG_SHIFT                (16U)
#define TRNG_SCR5L_RUN5_RNG(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
/*! @} */

/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
/*! @{ */
#define TRNG_SCR6PC_R6P_0_CT_MASK                (0x7FFU)
#define TRNG_SCR6PC_R6P_0_CT_SHIFT               (0U)
#define TRNG_SCR6PC_R6P_0_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
#define TRNG_SCR6PC_R6P_1_CT_MASK                (0x7FF0000U)
#define TRNG_SCR6PC_R6P_1_CT_SHIFT               (16U)
#define TRNG_SCR6PC_R6P_1_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
/*! @} */

/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
/*! @{ */
#define TRNG_SCR6PL_RUN6P_MAX_MASK               (0x7FFU)
#define TRNG_SCR6PL_RUN6P_MAX_SHIFT              (0U)
#define TRNG_SCR6PL_RUN6P_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
#define TRNG_SCR6PL_RUN6P_RNG_MASK               (0x7FF0000U)
#define TRNG_SCR6PL_RUN6P_RNG_SHIFT              (16U)
#define TRNG_SCR6PL_RUN6P_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
/*! @} */

/*! @name STATUS - Status Register */
/*! @{ */
#define TRNG_STATUS_TF1BR0_MASK                  (0x1U)
#define TRNG_STATUS_TF1BR0_SHIFT                 (0U)
#define TRNG_STATUS_TF1BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
#define TRNG_STATUS_TF1BR1_MASK                  (0x2U)
#define TRNG_STATUS_TF1BR1_SHIFT                 (1U)
#define TRNG_STATUS_TF1BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
#define TRNG_STATUS_TF2BR0_MASK                  (0x4U)
#define TRNG_STATUS_TF2BR0_SHIFT                 (2U)
#define TRNG_STATUS_TF2BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
#define TRNG_STATUS_TF2BR1_MASK                  (0x8U)
#define TRNG_STATUS_TF2BR1_SHIFT                 (3U)
#define TRNG_STATUS_TF2BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
#define TRNG_STATUS_TF3BR0_MASK                  (0x10U)
#define TRNG_STATUS_TF3BR0_SHIFT                 (4U)
#define TRNG_STATUS_TF3BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
#define TRNG_STATUS_TF3BR1_MASK                  (0x20U)
#define TRNG_STATUS_TF3BR1_SHIFT                 (5U)
#define TRNG_STATUS_TF3BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
#define TRNG_STATUS_TF4BR0_MASK                  (0x40U)
#define TRNG_STATUS_TF4BR0_SHIFT                 (6U)
#define TRNG_STATUS_TF4BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
#define TRNG_STATUS_TF4BR1_MASK                  (0x80U)
#define TRNG_STATUS_TF4BR1_SHIFT                 (7U)
#define TRNG_STATUS_TF4BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
#define TRNG_STATUS_TF5BR0_MASK                  (0x100U)
#define TRNG_STATUS_TF5BR0_SHIFT                 (8U)
#define TRNG_STATUS_TF5BR0(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
#define TRNG_STATUS_TF5BR1_MASK                  (0x200U)
#define TRNG_STATUS_TF5BR1_SHIFT                 (9U)
#define TRNG_STATUS_TF5BR1(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
#define TRNG_STATUS_TF6PBR0_MASK                 (0x400U)
#define TRNG_STATUS_TF6PBR0_SHIFT                (10U)
#define TRNG_STATUS_TF6PBR0(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
#define TRNG_STATUS_TF6PBR1_MASK                 (0x800U)
#define TRNG_STATUS_TF6PBR1_SHIFT                (11U)
#define TRNG_STATUS_TF6PBR1(x)                   (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
#define TRNG_STATUS_TFSB_MASK                    (0x1000U)
#define TRNG_STATUS_TFSB_SHIFT                   (12U)
#define TRNG_STATUS_TFSB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
#define TRNG_STATUS_TFLR_MASK                    (0x2000U)
#define TRNG_STATUS_TFLR_SHIFT                   (13U)
#define TRNG_STATUS_TFLR(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
#define TRNG_STATUS_TFP_MASK                     (0x4000U)
#define TRNG_STATUS_TFP_SHIFT                    (14U)
#define TRNG_STATUS_TFP(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
#define TRNG_STATUS_TFMB_MASK                    (0x8000U)
#define TRNG_STATUS_TFMB_SHIFT                   (15U)
#define TRNG_STATUS_TFMB(x)                      (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
#define TRNG_STATUS_RETRY_CT_MASK                (0xF0000U)
#define TRNG_STATUS_RETRY_CT_SHIFT               (16U)
#define TRNG_STATUS_RETRY_CT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
/*! @} */

/*! @name ENT - Entropy Read Register */
/*! @{ */
#define TRNG_ENT_ENT_MASK                        (0xFFFFFFFFU)
#define TRNG_ENT_ENT_SHIFT                       (0U)
#define TRNG_ENT_ENT(x)                          (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
/*! @} */

/* The count of TRNG_ENT */
#define TRNG_ENT_COUNT                           (16U)

/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
/*! @{ */
#define TRNG_PKRCNT10_PKR_0_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNT10_PKR_0_CT_SHIFT             (0U)
#define TRNG_PKRCNT10_PKR_0_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
#define TRNG_PKRCNT10_PKR_1_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNT10_PKR_1_CT_SHIFT             (16U)
#define TRNG_PKRCNT10_PKR_1_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
/*! @} */

/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
/*! @{ */
#define TRNG_PKRCNT32_PKR_2_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNT32_PKR_2_CT_SHIFT             (0U)
#define TRNG_PKRCNT32_PKR_2_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
#define TRNG_PKRCNT32_PKR_3_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNT32_PKR_3_CT_SHIFT             (16U)
#define TRNG_PKRCNT32_PKR_3_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
/*! @} */

/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
/*! @{ */
#define TRNG_PKRCNT54_PKR_4_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNT54_PKR_4_CT_SHIFT             (0U)
#define TRNG_PKRCNT54_PKR_4_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
#define TRNG_PKRCNT54_PKR_5_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNT54_PKR_5_CT_SHIFT             (16U)
#define TRNG_PKRCNT54_PKR_5_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
/*! @} */

/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
/*! @{ */
#define TRNG_PKRCNT76_PKR_6_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNT76_PKR_6_CT_SHIFT             (0U)
#define TRNG_PKRCNT76_PKR_6_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
#define TRNG_PKRCNT76_PKR_7_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNT76_PKR_7_CT_SHIFT             (16U)
#define TRNG_PKRCNT76_PKR_7_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
/*! @} */

/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
/*! @{ */
#define TRNG_PKRCNT98_PKR_8_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNT98_PKR_8_CT_SHIFT             (0U)
#define TRNG_PKRCNT98_PKR_8_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
#define TRNG_PKRCNT98_PKR_9_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNT98_PKR_9_CT_SHIFT             (16U)
#define TRNG_PKRCNT98_PKR_9_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
/*! @} */

/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
/*! @{ */
#define TRNG_PKRCNTBA_PKR_A_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT             (0U)
#define TRNG_PKRCNTBA_PKR_A_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
#define TRNG_PKRCNTBA_PKR_B_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT             (16U)
#define TRNG_PKRCNTBA_PKR_B_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
/*! @} */

/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
/*! @{ */
#define TRNG_PKRCNTDC_PKR_C_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT             (0U)
#define TRNG_PKRCNTDC_PKR_C_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
#define TRNG_PKRCNTDC_PKR_D_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT             (16U)
#define TRNG_PKRCNTDC_PKR_D_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
/*! @} */

/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
/*! @{ */
#define TRNG_PKRCNTFE_PKR_E_CT_MASK              (0xFFFFU)
#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT             (0U)
#define TRNG_PKRCNTFE_PKR_E_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
#define TRNG_PKRCNTFE_PKR_F_CT_MASK              (0xFFFF0000U)
#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT             (16U)
#define TRNG_PKRCNTFE_PKR_F_CT(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
/*! @} */

/*! @name SEC_CFG - Security Configuration Register */
/*! @{ */
#define TRNG_SEC_CFG_UNUSED0_MASK                (0x1U)
#define TRNG_SEC_CFG_UNUSED0_SHIFT               (0U)
#define TRNG_SEC_CFG_UNUSED0(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
#define TRNG_SEC_CFG_NO_PRGM_MASK                (0x2U)
#define TRNG_SEC_CFG_NO_PRGM_SHIFT               (1U)
/*! NO_PRGM
 *  0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
 *  0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
 */
#define TRNG_SEC_CFG_NO_PRGM(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
#define TRNG_SEC_CFG_UNUSED2_MASK                (0x4U)
#define TRNG_SEC_CFG_UNUSED2_SHIFT               (2U)
#define TRNG_SEC_CFG_UNUSED2(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
/*! @} */

/*! @name INT_CTRL - Interrupt Control Register */
/*! @{ */
#define TRNG_INT_CTRL_HW_ERR_MASK                (0x1U)
#define TRNG_INT_CTRL_HW_ERR_SHIFT               (0U)
/*! HW_ERR
 *  0b0..Corresponding bit of INT_STATUS register cleared.
 *  0b1..Corresponding bit of INT_STATUS register active.
 */
#define TRNG_INT_CTRL_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
#define TRNG_INT_CTRL_ENT_VAL_MASK               (0x2U)
#define TRNG_INT_CTRL_ENT_VAL_SHIFT              (1U)
/*! ENT_VAL
 *  0b0..Same behavior as bit 0 of this register.
 *  0b1..Same behavior as bit 0 of this register.
 */
#define TRNG_INT_CTRL_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK           (0x4U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT          (2U)
/*! FRQ_CT_FAIL
 *  0b0..Same behavior as bit 0 of this register.
 *  0b1..Same behavior as bit 0 of this register.
 */
#define TRNG_INT_CTRL_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
#define TRNG_INT_CTRL_UNUSED_MASK                (0xFFFFFFF8U)
#define TRNG_INT_CTRL_UNUSED_SHIFT               (3U)
#define TRNG_INT_CTRL_UNUSED(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
/*! @} */

/*! @name INT_MASK - Mask Register */
/*! @{ */
#define TRNG_INT_MASK_HW_ERR_MASK                (0x1U)
#define TRNG_INT_MASK_HW_ERR_SHIFT               (0U)
/*! HW_ERR
 *  0b0..Corresponding interrupt of INT_STATUS is masked.
 *  0b1..Corresponding bit of INT_STATUS is active.
 */
#define TRNG_INT_MASK_HW_ERR(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
#define TRNG_INT_MASK_ENT_VAL_MASK               (0x2U)
#define TRNG_INT_MASK_ENT_VAL_SHIFT              (1U)
/*! ENT_VAL
 *  0b0..Same behavior as bit 0 of this register.
 *  0b1..Same behavior as bit 0 of this register.
 */
#define TRNG_INT_MASK_ENT_VAL(x)                 (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK           (0x4U)
#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT          (2U)
/*! FRQ_CT_FAIL
 *  0b0..Same behavior as bit 0 of this register.
 *  0b1..Same behavior as bit 0 of this register.
 */
#define TRNG_INT_MASK_FRQ_CT_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
/*! @} */

/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */
#define TRNG_INT_STATUS_HW_ERR_MASK              (0x1U)
#define TRNG_INT_STATUS_HW_ERR_SHIFT             (0U)
/*! HW_ERR
 *  0b0..no error
 *  0b1..error detected.
 */
#define TRNG_INT_STATUS_HW_ERR(x)                (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
#define TRNG_INT_STATUS_ENT_VAL_MASK             (0x2U)
#define TRNG_INT_STATUS_ENT_VAL_SHIFT            (1U)
/*! ENT_VAL
 *  0b0..Busy generation entropy. Any value read is invalid.
 *  0b1..TRNG can be stopped and entropy is valid if read.
 */
#define TRNG_INT_STATUS_ENT_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK         (0x4U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT        (2U)
/*! FRQ_CT_FAIL
 *  0b0..No hardware nor self test frequency errors.
 *  0b1..The frequency counter has detected a failure.
 */
#define TRNG_INT_STATUS_FRQ_CT_FAIL(x)           (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
/*! @} */

/*! @name VID1 - Version ID Register (MS) */
/*! @{ */
#define TRNG_VID1_MIN_REV_MASK                   (0xFFU)
#define TRNG_VID1_MIN_REV_SHIFT                  (0U)
/*! MIN_REV
 *  0b00000000..Minor revision number for TRNG.
 */
#define TRNG_VID1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
#define TRNG_VID1_MAJ_REV_MASK                   (0xFF00U)
#define TRNG_VID1_MAJ_REV_SHIFT                  (8U)
/*! MAJ_REV
 *  0b00000001..Major revision number for TRNG.
 */
#define TRNG_VID1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
#define TRNG_VID1_IP_ID_MASK                     (0xFFFF0000U)
#define TRNG_VID1_IP_ID_SHIFT                    (16U)
/*! IP_ID
 *  0b0000000000110000..ID for TRNG.
 */
#define TRNG_VID1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
/*! @} */

/*! @name VID2 - Version ID Register (LS) */
/*! @{ */
#define TRNG_VID2_CONFIG_OPT_MASK                (0xFFU)
#define TRNG_VID2_CONFIG_OPT_SHIFT               (0U)
/*! CONFIG_OPT
 *  0b00000000..TRNG_CONFIG_OPT for TRNG.
 */
#define TRNG_VID2_CONFIG_OPT(x)                  (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
#define TRNG_VID2_ECO_REV_MASK                   (0xFF00U)
#define TRNG_VID2_ECO_REV_SHIFT                  (8U)
/*! ECO_REV
 *  0b00000000..TRNG_ECO_REV for TRNG.
 */
#define TRNG_VID2_ECO_REV(x)                     (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
#define TRNG_VID2_INTG_OPT_MASK                  (0xFF0000U)
#define TRNG_VID2_INTG_OPT_SHIFT                 (16U)
/*! INTG_OPT
 *  0b00000000..INTG_OPT for TRNG.
 */
#define TRNG_VID2_INTG_OPT(x)                    (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
#define TRNG_VID2_ERA_MASK                       (0xFF000000U)
#define TRNG_VID2_ERA_SHIFT                      (24U)
/*! ERA
 *  0b00000000..COMPILE_OPT for TRNG.
 */
#define TRNG_VID2_ERA(x)                         (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group TRNG_Register_Masks */


/* TRNG - Peripheral instance base addresses */
/** Peripheral TRNG0 base address */
#define TRNG0_BASE                               (0x40138000u)
/** Peripheral TRNG0 base pointer */
#define TRNG0                                    ((TRNG_Type *)TRNG0_BASE)
/** Array initializer of TRNG peripheral base addresses */
#define TRNG_BASE_ADDRS                          { TRNG0_BASE }
/** Array initializer of TRNG peripheral base pointers */
#define TRNG_BASE_PTRS                           { TRNG0 }


/*!
 * @}
 */ /* end of group TRNG_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USART Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
 * @{
 */

/** USART - Register Layout Typedef */
typedef struct {
  __IO uint32_t CFG;                               /**< USART Configuration, offset: 0x0 */
  __IO uint32_t CTL;                               /**< USART Control, offset: 0x4 */
  __IO uint32_t STAT;                              /**< USART Status, offset: 0x8 */
  __IO uint32_t INTENSET;                          /**< Interrupt Enable Read and Set for USART (not FIFO) Status, offset: 0xC */
  __O  uint32_t INTENCLR;                          /**< Interrupt Enable Clear, offset: 0x10 */
       uint8_t RESERVED_0[12];
  __IO uint32_t BRG;                               /**< Baud Rate Generator, offset: 0x20 */
  __I  uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x24 */
  __IO uint32_t OSR;                               /**< Oversample Selection Register for Asynchronous Communication, offset: 0x28 */
  __IO uint32_t ADDR;                              /**< Address Register for Automatic Address Matching, offset: 0x2C */
       uint8_t RESERVED_1[3536];
  __IO uint32_t FIFOCFG;                           /**< FIFO Configuration, offset: 0xE00 */
  __IO uint32_t FIFOSTAT;                          /**< FIFO Status, offset: 0xE04 */
  __IO uint32_t FIFOTRIG;                          /**< FIFO Trigger Settings for Interrupt and DMA Request, offset: 0xE08 */
       uint8_t RESERVED_2[4];
  __IO uint32_t FIFOINTENSET;                      /**< FIFO Interrupt Enable, offset: 0xE10 */
  __IO uint32_t FIFOINTENCLR;                      /**< FIFO Interrupt Enable Clear, offset: 0xE14 */
  __I  uint32_t FIFOINTSTAT;                       /**< FIFO Interrupt Status, offset: 0xE18 */
       uint8_t RESERVED_3[4];
  __O  uint32_t FIFOWR;                            /**< FIFO Write Data, offset: 0xE20 */
       uint8_t RESERVED_4[12];
  __I  uint32_t FIFORD;                            /**< FIFO Read Data, offset: 0xE30 */
       uint8_t RESERVED_5[12];
  __I  uint32_t FIFORDNOPOP;                       /**< FIFO Data Read with No FIFO Pop, offset: 0xE40 */
       uint8_t RESERVED_6[4];
  __I  uint32_t FIFOSIZE;                          /**< FIFO Size, offset: 0xE48 */
       uint8_t RESERVED_7[432];
  __I  uint32_t ID;                                /**< Peripheral Identification, offset: 0xFFC */
} USART_Type;

/* ----------------------------------------------------------------------------
   -- USART Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USART_Register_Masks USART Register Masks
 * @{
 */

/*! @name CFG - USART Configuration */
/*! @{ */
#define USART_CFG_ENABLE_MASK                    (0x1U)
#define USART_CFG_ENABLE_SHIFT                   (0U)
/*! ENABLE - USART Enable
 *  0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While ENABLE = 0,
 *       all USART interrupts and DMA transfers are disabled. When ENABLE is set again, CFG and most other control
 *       bits remain unchanged. When re-enabled, the USART is immediately ready to transmit because the transmitter
 *       has been reset and is therefore available.
 *  0b1..Enabled. The USART is enabled for operation.
 */
#define USART_CFG_ENABLE(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
#define USART_CFG_DATALEN_MASK                   (0xCU)
#define USART_CFG_DATALEN_SHIFT                  (2U)
/*! DATALEN
 *  0b00..7 bit data length
 *  0b01..8 bit data length
 *  0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET[CTL].
 *  0b11..Reserved
 */
#define USART_CFG_DATALEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
#define USART_CFG_PARITYSEL_MASK                 (0x30U)
#define USART_CFG_PARITYSEL_SHIFT                (4U)
/*! PARITYSEL
 *  0b00..No parity
 *  0b01..Reserved
 *  0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even,
 *        and the number of 1s in a received character is expected to be even.
 *  0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd,
 *        and the number of 1s in a received character is expected to be odd.
 */
#define USART_CFG_PARITYSEL(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
#define USART_CFG_STOPLEN_MASK                   (0x40U)
#define USART_CFG_STOPLEN_SHIFT                  (6U)
/*! STOPLEN
 *  0b0..1 stop bit
 *  0b1..2 stop bits. This setting should be used only for asynchronous communication.
 */
#define USART_CFG_STOPLEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
#define USART_CFG_MODE32K_MASK                   (0x80U)
#define USART_CFG_MODE32K_SHIFT                  (7U)
/*! MODE32K - Mode 32 kHz
 *  0b0..Disabled. USART uses standard clocking.
 *  0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.
 */
#define USART_CFG_MODE32K(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
#define USART_CFG_LINMODE_MASK                   (0x100U)
#define USART_CFG_LINMODE_SHIFT                  (8U)
/*! LINMODE - LIN Break Mode Enable
 *  0b0..Disabled. Break detect and generate is configured for normal operation.
 *  0b1..Enabled. Break detect and generate is configured for LIN bus operation.
 */
#define USART_CFG_LINMODE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
#define USART_CFG_CTSEN_MASK                     (0x200U)
#define USART_CFG_CTSEN_SHIFT                    (9U)
/*! CTSEN - CTS Enable
 *  0b0..No flow control. The transmitter does not receive any automatic flow control signal.
 *  0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.
 */
#define USART_CFG_CTSEN(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
#define USART_CFG_SYNCEN_MASK                    (0x800U)
#define USART_CFG_SYNCEN_SHIFT                   (11U)
/*! SYNCEN
 *  0b0..Asynchronous mode
 *  0b1..Synchronous mode
 */
#define USART_CFG_SYNCEN(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
#define USART_CFG_CLKPOL_MASK                    (0x1000U)
#define USART_CFG_CLKPOL_SHIFT                   (12U)
/*! CLKPOL - Clock Polarity
 *  0b0..Falling edge. RXD is sampled on the falling edge of SCLK.
 *  0b1..Rising edge. RXD is sampled on the rising edge of SCLK.
 */
#define USART_CFG_CLKPOL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
#define USART_CFG_SYNCMST_MASK                   (0x4000U)
#define USART_CFG_SYNCMST_SHIFT                  (14U)
/*! SYNCMST - Synchronous mode Master Select
 *  0b0..Slave. When synchronous mode is enabled, the USART is a slave.
 *  0b1..Master. When synchronous mode is enabled, the USART is a master.
 */
#define USART_CFG_SYNCMST(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
#define USART_CFG_LOOP_MASK                      (0x8000U)
#define USART_CFG_LOOP_SHIFT                     (15U)
/*! LOOP - Loopback Mode
 *  0b0..Normal operation
 *  0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial
 *       data from the transmitter (TXD) is connected internally to serial input of the receiver (RXD). TXD and RTS
 *       activity also appear on external pins if these functions are configured to appear on device pins. The
 *       receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.
 */
#define USART_CFG_LOOP(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
#define USART_CFG_OETA_MASK                      (0x40000U)
#define USART_CFG_OETA_SHIFT                     (18U)
/*! OETA
 *  0b0..Disabled. If selected by OESEL, the Output Enable signal is deasserted at the end of the last stop bit of a transmission.
 *  0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the
 *       end of the last stop bit of a transmission. The Output Enable signal also remains asserted if another
 *       transmit begins before Output Enable is deasserted.
 */
#define USART_CFG_OETA(x)                        (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
#define USART_CFG_AUTOADDR_MASK                  (0x80000U)
#define USART_CFG_AUTOADDR_SHIFT                 (19U)
/*! AUTOADDR - Automatic Address Matching Enable
 *  0b0..Disabled. When addressing is enabled by CTL[ADDRDET], address matching is done by software. This provides
 *       the possibility of versatile addressing (e.g. respond to more than one address).
 *  0b1..Enabled. When addressing is enabled by CTL[ADDRDET], address matching is done by hardware, using the
 *       value in the ADDR register as the address to match.
 */
#define USART_CFG_AUTOADDR(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
#define USART_CFG_OESEL_MASK                     (0x100000U)
#define USART_CFG_OESEL_SHIFT                    (20U)
/*! OESEL - Output Enable Select
 *  0b0..Standard. The RTS signal is used as the standard flow control function.
 *  0b1..RS-485. The RTS signal is configured to provide an output enable signal to control an RS-485 transceiver.
 */
#define USART_CFG_OESEL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
#define USART_CFG_OEPOL_MASK                     (0x200000U)
#define USART_CFG_OEPOL_SHIFT                    (21U)
/*! OEPOL - Output Enable Polarity
 *  0b0..Low. If selected by OESEL, the output enable is active low.
 *  0b1..High. If selected by OESEL, the output enable is active high.
 */
#define USART_CFG_OEPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
#define USART_CFG_RXPOL_MASK                     (0x400000U)
#define USART_CFG_RXPOL_SHIFT                    (22U)
/*! RXPOL - Receive Data Polarity
 *  0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start
 *       bit is 0, data is not inverted, and the stop bit is 1.
 *  0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is
 *       0, start bit is 1, data is inverted, and the stop bit is 0.
 */
#define USART_CFG_RXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
#define USART_CFG_TXPOL_MASK                     (0x800000U)
#define USART_CFG_TXPOL_SHIFT                    (23U)
/*! TXPOL - Transmit data polarity
 *  0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, the start bit
 *       is 0, data is not inverted, and the stop bit is 1.
 *  0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value
 *       is 0, start bit is 1, data is inverted, and the stop bit is 0.
 */
#define USART_CFG_TXPOL(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
/*! @} */

/*! @name CTL - USART Control */
/*! @{ */
#define USART_CTL_TXBRKEN_MASK                   (0x2U)
#define USART_CTL_TXBRKEN_SHIFT                  (1U)
/*! TXBRKEN - Break Enable
 *  0b0..Normal operation
 *  0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit
 *       is cleared. A break may be sent without danger of corrupting any currently transmitting character if the
 *       transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled
 *       (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.
 */
#define USART_CTL_TXBRKEN(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
#define USART_CTL_ADDRDET_MASK                   (0x4U)
#define USART_CTL_ADDRDET_SHIFT                  (2U)
/*! ADDRDET - Enable Address Detect Mode
 *  0b0..Disabled. The USART presents all incoming data.
 *  0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit (msb) of
 *       the data (typically the 9th bit) = 1. When the data msb = 1, the receiver treats the incoming data normally,
 *       generating a received data interrupt. Software can then check the data to see if this is an address that
 *       should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled
 *       normally.
 */
#define USART_CTL_ADDRDET(x)                     (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
#define USART_CTL_TXDIS_MASK                     (0x40U)
#define USART_CTL_TXDIS_SHIFT                    (6U)
/*! TXDIS - Transmit Disable
 *  0b0..Not disabled. USART transmitter is not disabled.
 *  0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This
 *       feature can be used to facilitate software flow control.
 */
#define USART_CTL_TXDIS(x)                       (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
#define USART_CTL_CC_MASK                        (0x100U)
#define USART_CTL_CC_SHIFT                       (8U)
/*! CC - Continuous Clock Generation
 *  0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on TXD or to
 *       complete a character that is being received.
 *  0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on RxD
 *       independently from transmission on TXD).
 */
#define USART_CTL_CC(x)                          (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
#define USART_CTL_CLRCCONRX_MASK                 (0x200U)
#define USART_CTL_CLRCCONRX_SHIFT                (9U)
/*! CLRCCONRX - Clear Continuous Clock
 *  0b0..No effect. No effect on the CC bit.
 *  0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.
 */
#define USART_CTL_CLRCCONRX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
#define USART_CTL_AUTOBAUD_MASK                  (0x10000U)
#define USART_CTL_AUTOBAUD_SHIFT                 (16U)
/*! AUTOBAUD - Autobaud Enable
 *  0b0..Disabled. USART is in normal operating mode.
 *  0b1..Enabled. USART is in autobaud mode. AUTOBAUD should only be set when the USART receiver is idle. The
 *       first start bit of RX is measured and used to update the BRG register to match the received data rate.
 *       AUTOBAUD is cleared once this process is complete, or if there is an AERR.
 */
#define USART_CTL_AUTOBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
/*! @} */

/*! @name STAT - USART Status */
/*! @{ */
#define USART_STAT_RXIDLE_MASK                   (0x2U)
#define USART_STAT_RXIDLE_SHIFT                  (1U)
/*! RXIDLE - Receiver Idle
 *  0b0..The receiver is currently receiving data.
 *  0b1..The receiver is not currently receiving data.
 */
#define USART_STAT_RXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
#define USART_STAT_TXIDLE_MASK                   (0x8U)
#define USART_STAT_TXIDLE_SHIFT                  (3U)
/*! TXIDLE - Transmitter Idle
 *  0b0..The transmitter is currently sending data.
 *  0b1..The transmitter is not currently sending data.
 */
#define USART_STAT_TXIDLE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
#define USART_STAT_CTS_MASK                      (0x10U)
#define USART_STAT_CTS_SHIFT                     (4U)
/*! CTS - CTS value
 */
#define USART_STAT_CTS(x)                        (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
#define USART_STAT_DELTACTS_MASK                 (0x20U)
#define USART_STAT_DELTACTS_SHIFT                (5U)
/*! DELTACTS - Delta CTS
 */
#define USART_STAT_DELTACTS(x)                   (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
#define USART_STAT_TXDISSTAT_MASK                (0x40U)
#define USART_STAT_TXDISSTAT_SHIFT               (6U)
/*! TXDISSTAT - Transmitter Disabled Status Flag
 *  0b0..NOT IDLE. Indicates that the USART transmitter is NOT fully idle after being disabled.
 *  0b1..IDLE. Indicates that the USART transmitter is fully idle after being disabled (CTL[TXDIS] = 1).
 */
#define USART_STAT_TXDISSTAT(x)                  (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
#define USART_STAT_RXBRK_MASK                    (0x400U)
#define USART_STAT_RXBRK_SHIFT                   (10U)
/*! RXBRK - Received Break
 */
#define USART_STAT_RXBRK(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
#define USART_STAT_DELTARXBRK_MASK               (0x800U)
#define USART_STAT_DELTARXBRK_SHIFT              (11U)
/*! DELTARXBRK - Delta Received Break
 */
#define USART_STAT_DELTARXBRK(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
#define USART_STAT_START_MASK                    (0x1000U)
#define USART_STAT_START_SHIFT                   (12U)
/*! START - Start
 */
#define USART_STAT_START(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
#define USART_STAT_FRAMERRINT_MASK               (0x2000U)
#define USART_STAT_FRAMERRINT_SHIFT              (13U)
/*! FRAMERRINT - Framing Error Interrupt Flag
 */
#define USART_STAT_FRAMERRINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
#define USART_STAT_PARITYERRINT_MASK             (0x4000U)
#define USART_STAT_PARITYERRINT_SHIFT            (14U)
/*! PARITYERRINT - Parity Error Interrupt Flag
 */
#define USART_STAT_PARITYERRINT(x)               (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
#define USART_STAT_RXNOISEINT_MASK               (0x8000U)
#define USART_STAT_RXNOISEINT_SHIFT              (15U)
/*! RXNOISEINT - Received Noise Interrupt Flag
 */
#define USART_STAT_RXNOISEINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
#define USART_STAT_ABERR_MASK                    (0x10000U)
#define USART_STAT_ABERR_SHIFT                   (16U)
/*! ABERR - Auto Baud Error
 */
#define USART_STAT_ABERR(x)                      (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
/*! @} */

/*! @name INTENSET - Interrupt Enable Read and Set for USART (not FIFO) Status */
/*! @{ */
#define USART_INTENSET_TXIDLEEN_MASK             (0x8U)
#define USART_INTENSET_TXIDLEEN_SHIFT            (3U)
/*! TXIDLEEN - Transmit Idle Flag
 *  0b1..Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1).
 */
#define USART_INTENSET_TXIDLEEN(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
#define USART_INTENSET_DELTACTSEN_MASK           (0x20U)
#define USART_INTENSET_DELTACTSEN_SHIFT          (5U)
/*! DELTACTSEN - Delta CTS Input Flag
 *  0b1..Enables an interrupt when there is a change in the state of the CTS input.
 */
#define USART_INTENSET_DELTACTSEN(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
#define USART_INTENSET_TXDISEN_MASK              (0x40U)
#define USART_INTENSET_TXDISEN_SHIFT             (6U)
/*! TXDISEN - Transmit Disabled Flag
 *  0b1..Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[TXDISINT] flag. See
 *       the description of the STAT[TXDISINT] flag.
 */
#define USART_INTENSET_TXDISEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
#define USART_INTENSET_DELTARXBRKEN_MASK         (0x800U)
#define USART_INTENSET_DELTARXBRKEN_SHIFT        (11U)
/*! DELTARXBRKEN - Delta Receive Break Enable
 *  0b1..Enables an interrupt when a change of state has occurred in the detection of a received break condition
 *       (break condition asserted or deasserted).
 */
#define USART_INTENSET_DELTARXBRKEN(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
#define USART_INTENSET_STARTEN_MASK              (0x1000U)
#define USART_INTENSET_STARTEN_SHIFT             (12U)
/*! STARTEN - Start Enable
 *  0b1..Enables an interrupt when a received start bit has been detected.
 */
#define USART_INTENSET_STARTEN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
#define USART_INTENSET_FRAMERREN_MASK            (0x2000U)
#define USART_INTENSET_FRAMERREN_SHIFT           (13U)
/*! FRAMERREN - Frame Error Enable
 *  0b1..Enables an interrupt when a framing error has been detected.
 */
#define USART_INTENSET_FRAMERREN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
#define USART_INTENSET_PARITYERREN_MASK          (0x4000U)
#define USART_INTENSET_PARITYERREN_SHIFT         (14U)
/*! PARITYERREN - Parity Error Enble
 *  0b1..Enables an interrupt when a parity error has been detected.
 */
#define USART_INTENSET_PARITYERREN(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
#define USART_INTENSET_RXNOISEEN_MASK            (0x8000U)
#define USART_INTENSET_RXNOISEEN_SHIFT           (15U)
/*! RXNOISEEN - Receive Noise Enable
 *  0b1..Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEINT] bit.
 */
#define USART_INTENSET_RXNOISEEN(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
#define USART_INTENSET_ABERREN_MASK              (0x10000U)
#define USART_INTENSET_ABERREN_SHIFT             (16U)
/*! ABERREN - Auto Baud Error Enable
 *  0b1..Enables an interrupt when an auto baud error occurs.
 */
#define USART_INTENSET_ABERREN(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
/*! @} */

/*! @name INTENCLR - Interrupt Enable Clear */
/*! @{ */
#define USART_INTENCLR_TXIDLECLR_MASK            (0x8U)
#define USART_INTENCLR_TXIDLECLR_SHIFT           (3U)
/*! TXIDLECLR - Transmit Idle Clear
 */
#define USART_INTENCLR_TXIDLECLR(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
#define USART_INTENCLR_DELTACTSCLR_MASK          (0x20U)
#define USART_INTENCLR_DELTACTSCLR_SHIFT         (5U)
/*! DELTACTSCLR - Delta CTS Clear
 */
#define USART_INTENCLR_DELTACTSCLR(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
#define USART_INTENCLR_TXDISCLR_MASK             (0x40U)
#define USART_INTENCLR_TXDISCLR_SHIFT            (6U)
/*! TXDISCLR - Transmit Disable Clear
 */
#define USART_INTENCLR_TXDISCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
#define USART_INTENCLR_DELTARXBRKCLR_MASK        (0x800U)
#define USART_INTENCLR_DELTARXBRKCLR_SHIFT       (11U)
/*! DELTARXBRKCLR - Delta Receive Break Clear
 */
#define USART_INTENCLR_DELTARXBRKCLR(x)          (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
#define USART_INTENCLR_STARTCLR_MASK             (0x1000U)
#define USART_INTENCLR_STARTCLR_SHIFT            (12U)
/*! STARTCLR - Start Clear
 */
#define USART_INTENCLR_STARTCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
#define USART_INTENCLR_FRAMERRCLR_MASK           (0x2000U)
#define USART_INTENCLR_FRAMERRCLR_SHIFT          (13U)
/*! FRAMERRCLR - Frame Error Clear
 */
#define USART_INTENCLR_FRAMERRCLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
#define USART_INTENCLR_PARITYERRCLR_MASK         (0x4000U)
#define USART_INTENCLR_PARITYERRCLR_SHIFT        (14U)
/*! PARITYERRCLR - Parity Error Clear
 */
#define USART_INTENCLR_PARITYERRCLR(x)           (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
#define USART_INTENCLR_RXNOISECLR_MASK           (0x8000U)
#define USART_INTENCLR_RXNOISECLR_SHIFT          (15U)
/*! RXNOISECLR - Receive Noise Clear
 */
#define USART_INTENCLR_RXNOISECLR(x)             (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
#define USART_INTENCLR_ABERRCLR_MASK             (0x10000U)
#define USART_INTENCLR_ABERRCLR_SHIFT            (16U)
/*! ABERRCLR - Auto Baud Error Clear
 */
#define USART_INTENCLR_ABERRCLR(x)               (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
/*! @} */

/*! @name BRG - Baud Rate Generator */
/*! @{ */
#define USART_BRG_BRGVAL_MASK                    (0xFFFFU)
#define USART_BRG_BRGVAL_SHIFT                   (0U)
/*! BRGVAL - Baud Rate Generator Value
 *  0b0000000000000000..FCLK is used directly by the USART function.
 *  0b0000000000000001..FCLK is divided by 2 before use by the USART function.
 *  0b0000000000000010..FCLK is divided by 3 before use by the USART function.
 *  0b1111111111111111..FCLK is divided by 65,536 before use by the USART function.
 */
#define USART_BRG_BRGVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
/*! @} */

/*! @name INTSTAT - Interrupt Status */
/*! @{ */
#define USART_INTSTAT_TXIDLE_MASK                (0x8U)
#define USART_INTSTAT_TXIDLE_SHIFT               (3U)
/*! TXIDLE - Transmitter Idle Flag
 */
#define USART_INTSTAT_TXIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
#define USART_INTSTAT_DELTACTS_MASK              (0x20U)
#define USART_INTSTAT_DELTACTS_SHIFT             (5U)
/*! DELTACTS - Delta CTS Change Flag
 */
#define USART_INTSTAT_DELTACTS(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
#define USART_INTSTAT_TXDISINT_MASK              (0x40U)
#define USART_INTSTAT_TXDISINT_SHIFT             (6U)
/*! TXDISINT - Transmitter Disabled Interrupt Flag
 */
#define USART_INTSTAT_TXDISINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
#define USART_INTSTAT_DELTARXBRK_MASK            (0x800U)
#define USART_INTSTAT_DELTARXBRK_SHIFT           (11U)
/*! DELTARXBRK - Delta Receiver Break Change Flag
 */
#define USART_INTSTAT_DELTARXBRK(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
#define USART_INTSTAT_START_MASK                 (0x1000U)
#define USART_INTSTAT_START_SHIFT                (12U)
/*! START - Start Detected on Receiver Flag
 */
#define USART_INTSTAT_START(x)                   (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
#define USART_INTSTAT_FRAMERRINT_MASK            (0x2000U)
#define USART_INTSTAT_FRAMERRINT_SHIFT           (13U)
/*! FRAMERRINT - Framing Error Interrupt Flag
 */
#define USART_INTSTAT_FRAMERRINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
#define USART_INTSTAT_PARITYERRINT_MASK          (0x4000U)
#define USART_INTSTAT_PARITYERRINT_SHIFT         (14U)
/*! PARITYERRINT - Parity Error Interrupt Flag
 */
#define USART_INTSTAT_PARITYERRINT(x)            (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
#define USART_INTSTAT_RXNOISEINT_MASK            (0x8000U)
#define USART_INTSTAT_RXNOISEINT_SHIFT           (15U)
/*! RXNOISEINT - Received Noise Interrupt Flag
 */
#define USART_INTSTAT_RXNOISEINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
#define USART_INTSTAT_ABERRINT_MASK              (0x10000U)
#define USART_INTSTAT_ABERRINT_SHIFT             (16U)
/*! ABERRINT - Auto Baud Error Interrupt Flag
 */
#define USART_INTSTAT_ABERRINT(x)                (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
/*! @} */

/*! @name OSR - Oversample Selection Register for Asynchronous Communication */
/*! @{ */
#define USART_OSR_OSRVAL_MASK                    (0xFU)
#define USART_OSR_OSRVAL_SHIFT                   (0U)
/*! OSRVAL - Oversample Selection Value
 *  0b0000..Not supported
 *  0b0001..Not supported
 *  0b0010..Not supported
 *  0b0011..Not supported
 *  0b0100..5 function clocks are used to transmit and receive each data bit.
 *  0b0101..6 function clocks are used to transmit and receive each data bit.
 *  0b1111..16 function clocks are used to transmit and receive each data bit.
 */
#define USART_OSR_OSRVAL(x)                      (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
/*! @} */

/*! @name ADDR - Address Register for Automatic Address Matching */
/*! @{ */
#define USART_ADDR_ADDRESS_MASK                  (0xFFU)
#define USART_ADDR_ADDRESS_SHIFT                 (0U)
/*! ADDRESS - Address
 */
#define USART_ADDR_ADDRESS(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
/*! @} */

/*! @name FIFOCFG - FIFO Configuration */
/*! @{ */
#define USART_FIFOCFG_ENABLETX_MASK              (0x1U)
#define USART_FIFOCFG_ENABLETX_SHIFT             (0U)
/*! ENABLETX - Enable the Transmit FIFO.
 *  0b0..The transmit FIFO is not enabled.
 *  0b1..The transmit FIFO is enabled.
 */
#define USART_FIFOCFG_ENABLETX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
#define USART_FIFOCFG_ENABLERX_MASK              (0x2U)
#define USART_FIFOCFG_ENABLERX_SHIFT             (1U)
/*! ENABLERX - Enable the Receive FIFO
 *  0b0..The receive FIFO is not enabled.
 *  0b1..The receive FIFO is enabled.
 */
#define USART_FIFOCFG_ENABLERX(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
#define USART_FIFOCFG_SIZE_MASK                  (0x30U)
#define USART_FIFOCFG_SIZE_SHIFT                 (4U)
/*! SIZE - FIFO Size Configuration
 *  0b00..FIFO is configured as 16 entries of 8 bits.
 *  0b01..Not used
 *  0b10..Not used
 *  0b11..Not used
 */
#define USART_FIFOCFG_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
#define USART_FIFOCFG_DMATX_MASK                 (0x1000U)
#define USART_FIFOCFG_DMATX_SHIFT                (12U)
/*! DMATX - DMA Configuration for Transmit
 *  0b0..DMA is not used for the transmit function.
 *  0b1..Triggers DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define USART_FIFOCFG_DMATX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
#define USART_FIFOCFG_DMARX_MASK                 (0x2000U)
#define USART_FIFOCFG_DMARX_SHIFT                (13U)
/*! DMARX - DMA Configuration for Receive
 *  0b0..DMA is not used for the receive function.
 *  0b1..Triggers DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.
 */
#define USART_FIFOCFG_DMARX(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
#define USART_FIFOCFG_WAKETX_MASK                (0x4000U)
#define USART_FIFOCFG_WAKETX_SHIFT               (14U)
/*! WAKETX - Wake-up for Transmit FIFO Level
 *  0b0..Only enabled interrupts will wake up the device from low power modes.
 *  0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by
 *       FIFOTRIG[TXLVL], even when the TXLVL interrupt is not enabled.
 */
#define USART_FIFOCFG_WAKETX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
#define USART_FIFOCFG_WAKERX_MASK                (0x8000U)
#define USART_FIFOCFG_WAKERX_SHIFT               (15U)
/*! WAKERX - Wake-up for Receive FIFO Level
 *  0b0..Only enabled interrupts will wake up the device from low power modes.
 *  0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by
 *       FIFOTRIG[RXLVL], even when the RXLVL interrupt is not enabled.
 */
#define USART_FIFOCFG_WAKERX(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
#define USART_FIFOCFG_EMPTYTX_MASK               (0x10000U)
#define USART_FIFOCFG_EMPTYTX_SHIFT              (16U)
/*! EMPTYTX - Empty Command for the Transmit FIFO
 *  0b0..No effect
 *  0b1..The TX FIFO is emptied.
 */
#define USART_FIFOCFG_EMPTYTX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
#define USART_FIFOCFG_EMPTYRX_MASK               (0x20000U)
#define USART_FIFOCFG_EMPTYRX_SHIFT              (17U)
/*! EMPTYRX - Empty Command for the Receive FIFO
 *  0b0..No effect
 *  0b1..The RX FIFO is emptied.
 */
#define USART_FIFOCFG_EMPTYRX(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
#define USART_FIFOCFG_POPDBG_MASK                (0x40000U)
#define USART_FIFOCFG_POPDBG_SHIFT               (18U)
/*! POPDBG - Pop FIFO for Debug Reads
 *  0b0..Debug reads of the FIFO do not pop the FIFO.
 *  0b1..A debug read will cause the FIFO to pop.
 */
#define USART_FIFOCFG_POPDBG(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
/*! @} */

/*! @name FIFOSTAT - FIFO Status */
/*! @{ */
#define USART_FIFOSTAT_TXERR_MASK                (0x1U)
#define USART_FIFOSTAT_TXERR_SHIFT               (0U)
/*! TXERR - TX FIFO Error
 *  0b0..A transmit FIFO error has not occurred.
 *  0b1..A transmit FIFO error has occurred. This error could be an overflow caused by pushing data into a full
 *       FIFO, or by an underflow if the FIFO is empty when data is needed.
 */
#define USART_FIFOSTAT_TXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
#define USART_FIFOSTAT_RXERR_MASK                (0x2U)
#define USART_FIFOSTAT_RXERR_SHIFT               (1U)
/*! RXERR - RX FIFO Error
 *  0b0..A receive FIFO overflow has not occurred
 *  0b1..A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO fast enough
 */
#define USART_FIFOSTAT_RXERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
#define USART_FIFOSTAT_PERINT_MASK               (0x8U)
#define USART_FIFOSTAT_PERINT_SHIFT              (3U)
/*! PERINT - Peripheral Interrupt
 *  0b0..The peripheral function has not asserted an interrupt.
 *  0b1..Indicates that the peripheral function has asserted an interrupt. More information can be found by
 *       reading the peripheral's status register (STAT).
 */
#define USART_FIFOSTAT_PERINT(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
#define USART_FIFOSTAT_TXEMPTY_MASK              (0x10U)
#define USART_FIFOSTAT_TXEMPTY_SHIFT             (4U)
/*! TXEMPTY - Transmit FIFO Empty
 *  0b0..The transmit FIFO is not empty.
 *  0b1..The transmit FIFO is empty, although the peripheral may still be processing the last piece of data.
 */
#define USART_FIFOSTAT_TXEMPTY(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
#define USART_FIFOSTAT_TXNOTFULL_MASK            (0x20U)
#define USART_FIFOSTAT_TXNOTFULL_SHIFT           (5U)
/*! TXNOTFULL - Transmit FIFO is Not Full
 *  0b0..The transmit FIFO is full and another write would cause it to overflow.
 *  0b1..The transmit FIFO is not full, so more data can be written.
 */
#define USART_FIFOSTAT_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
#define USART_FIFOSTAT_RXNOTEMPTY_MASK           (0x40U)
#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT          (6U)
/*! RXNOTEMPTY - Receive FIFO is Not Empty
 *  0b0..The receive FIFO is empty.
 *  0b1..The receive FIFO is not empty, so data can be read.
 */
#define USART_FIFOSTAT_RXNOTEMPTY(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
#define USART_FIFOSTAT_RXFULL_MASK               (0x80U)
#define USART_FIFOSTAT_RXFULL_SHIFT              (7U)
/*! RXFULL - Receive FIFO is Full
 *  0b0..The receive FIFO is not full.
 *  0b1..The receive FIFO is full. To prevent the peripheral from causing an overflow, data should be read out.
 */
#define USART_FIFOSTAT_RXFULL(x)                 (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
#define USART_FIFOSTAT_TXLVL_MASK                (0x1F00U)
#define USART_FIFOSTAT_TXLVL_SHIFT               (8U)
/*! TXLVL - Transmit FIFO Current Level
 */
#define USART_FIFOSTAT_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
#define USART_FIFOSTAT_RXLVL_MASK                (0x1F0000U)
#define USART_FIFOSTAT_RXLVL_SHIFT               (16U)
/*! RXLVL - Receive FIFO Current Level
 */
#define USART_FIFOSTAT_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
/*! @} */

/*! @name FIFOTRIG - FIFO Trigger Settings for Interrupt and DMA Request */
/*! @{ */
#define USART_FIFOTRIG_TXLVLENA_MASK             (0x1U)
#define USART_FIFOTRIG_TXLVLENA_SHIFT            (0U)
/*! TXLVLENA - Transmit FIFO Level Trigger Enable.
 *  0b0..Transmit FIFO level does not generate a FIFO level trigger.
 *  0b1..A trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field.
 */
#define USART_FIFOTRIG_TXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
#define USART_FIFOTRIG_RXLVLENA_MASK             (0x2U)
#define USART_FIFOTRIG_RXLVLENA_SHIFT            (1U)
/*! RXLVLENA - Receive FIFO Level Trigger Enable
 *  0b0..Receive FIFO level does not generate a FIFO level trigger.
 *  0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field.
 */
#define USART_FIFOTRIG_RXLVLENA(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
#define USART_FIFOTRIG_TXLVL_MASK                (0xF00U)
#define USART_FIFOTRIG_TXLVL_SHIFT               (8U)
/*! TXLVL - Transmit FIFO Level Trigger Point
 *  0b0000..Trigger when the TX FIFO becomes empty
 *  0b0001..Trigger when the TX FIFO level decreases to 1 entry
 *  0b1111..Trigger when the TX FIFO level decreases to 15 entries (is no longer full)
 */
#define USART_FIFOTRIG_TXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
#define USART_FIFOTRIG_RXLVL_MASK                (0xF0000U)
#define USART_FIFOTRIG_RXLVL_SHIFT               (16U)
/*! RXLVL - Receive FIFO Level Trigger Point
 *  0b0000..Trigger when the RX FIFO has received 1 entry (is no longer empty)
 *  0b0001..Trigger when the RX FIFO has received 2 entries
 *  0b1111..Trigger when the RX FIFO has received 16 entries (has become full)
 */
#define USART_FIFOTRIG_RXLVL(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENSET - FIFO Interrupt Enable */
/*! @{ */
#define USART_FIFOINTENSET_TXERR_MASK            (0x1U)
#define USART_FIFOINTENSET_TXERR_SHIFT           (0U)
/*! TXERR - Transmit Error Interrupt Enable
 *  0b0..No interrupt will be generated for a transmit error.
 *  0b1..An interrupt will be generated when a transmit error occurs.
 */
#define USART_FIFOINTENSET_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
#define USART_FIFOINTENSET_RXERR_MASK            (0x2U)
#define USART_FIFOINTENSET_RXERR_SHIFT           (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No interrupt will be generated for a receive error.
 *  0b1..An interrupt will be generated when a receive error occurs.
 */
#define USART_FIFOINTENSET_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
#define USART_FIFOINTENSET_TXLVL_MASK            (0x4U)
#define USART_FIFOINTENSET_TXLVL_SHIFT           (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the TX FIFO level.
 *  0b1..If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level decreases to the level specified by FIFOTRIG[TXLVL]
 */
#define USART_FIFOINTENSET_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
#define USART_FIFOINTENSET_RXLVL_MASK            (0x8U)
#define USART_FIFOINTENSET_RXLVL_SHIFT           (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No interrupt will be generated based on the RX FIFO level.
 *  0b1..If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO level increases to
 *       the level specified by FIFOTRIG[RXLVL].
 */
#define USART_FIFOINTENSET_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTENCLR - FIFO Interrupt Enable Clear */
/*! @{ */
#define USART_FIFOINTENCLR_TXERR_MASK            (0x1U)
#define USART_FIFOINTENCLR_TXERR_SHIFT           (0U)
/*! TXERR - Transmit Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_TXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
#define USART_FIFOINTENCLR_RXERR_MASK            (0x2U)
#define USART_FIFOINTENCLR_RXERR_SHIFT           (1U)
/*! RXERR - Receive Error Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_RXERR(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
#define USART_FIFOINTENCLR_TXLVL_MASK            (0x4U)
#define USART_FIFOINTENCLR_TXLVL_SHIFT           (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_TXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
#define USART_FIFOINTENCLR_RXLVL_MASK            (0x8U)
#define USART_FIFOINTENCLR_RXLVL_SHIFT           (3U)
/*! RXLVL - Receive FIFO Level Interrupt Enable
 *  0b0..No effect
 *  0b1..Clear the interrupt
 */
#define USART_FIFOINTENCLR_RXLVL(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
/*! @} */

/*! @name FIFOINTSTAT - FIFO Interrupt Status */
/*! @{ */
#define USART_FIFOINTSTAT_TXERR_MASK             (0x1U)
#define USART_FIFOINTSTAT_TXERR_SHIFT            (0U)
/*! TXERR - TX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_TXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
#define USART_FIFOINTSTAT_RXERR_MASK             (0x2U)
#define USART_FIFOINTSTAT_RXERR_SHIFT            (1U)
/*! RXERR - RX FIFO Error Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_RXERR(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
#define USART_FIFOINTSTAT_TXLVL_MASK             (0x4U)
#define USART_FIFOINTSTAT_TXLVL_SHIFT            (2U)
/*! TXLVL - Transmit FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_TXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
#define USART_FIFOINTSTAT_RXLVL_MASK             (0x8U)
#define USART_FIFOINTSTAT_RXLVL_SHIFT            (3U)
/*! RXLVL - Receive FIFO Level Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_RXLVL(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
#define USART_FIFOINTSTAT_PERINT_MASK            (0x10U)
#define USART_FIFOINTSTAT_PERINT_SHIFT           (4U)
/*! PERINT - Peripheral Interrupt Status
 *  0b0..Not pending
 *  0b1..Pending
 */
#define USART_FIFOINTSTAT_PERINT(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
/*! @} */

/*! @name FIFOWR - FIFO Write Data */
/*! @{ */
#define USART_FIFOWR_TXDATA_MASK                 (0x1FFU)
#define USART_FIFOWR_TXDATA_SHIFT                (0U)
/*! TXDATA - Transmit data to the FIFO
 */
#define USART_FIFOWR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
/*! @} */

/*! @name FIFORD - FIFO Read Data */
/*! @{ */
#define USART_FIFORD_RXDATA_MASK                 (0x1FFU)
#define USART_FIFORD_RXDATA_SHIFT                (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define USART_FIFORD_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
#define USART_FIFORD_FRAMERR_MASK                (0x2000U)
#define USART_FIFORD_FRAMERR_SHIFT               (13U)
/*! FRAMERR - Framing Error Status Flag
 */
#define USART_FIFORD_FRAMERR(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
#define USART_FIFORD_PARITYERR_MASK              (0x4000U)
#define USART_FIFORD_PARITYERR_SHIFT             (14U)
/*! PARITYERR - Parity Error Status Flag
 */
#define USART_FIFORD_PARITYERR(x)                (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
#define USART_FIFORD_RXNOISE_MASK                (0x8000U)
#define USART_FIFORD_RXNOISE_SHIFT               (15U)
/*! RXNOISE - Received Noise Flag
 */
#define USART_FIFORD_RXNOISE(x)                  (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
/*! @} */

/*! @name FIFORDNOPOP - FIFO Data Read with No FIFO Pop */
/*! @{ */
#define USART_FIFORDNOPOP_RXDATA_MASK            (0x1FFU)
#define USART_FIFORDNOPOP_RXDATA_SHIFT           (0U)
/*! RXDATA - Received Data from the FIFO
 */
#define USART_FIFORDNOPOP_RXDATA(x)              (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
#define USART_FIFORDNOPOP_FRAMERR_MASK           (0x2000U)
#define USART_FIFORDNOPOP_FRAMERR_SHIFT          (13U)
/*! FRAMERR - Framing Error Status Flag
 */
#define USART_FIFORDNOPOP_FRAMERR(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
#define USART_FIFORDNOPOP_PARITYERR_MASK         (0x4000U)
#define USART_FIFORDNOPOP_PARITYERR_SHIFT        (14U)
/*! PARITYERR - Parity Error Status Flag
 */
#define USART_FIFORDNOPOP_PARITYERR(x)           (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
#define USART_FIFORDNOPOP_RXNOISE_MASK           (0x8000U)
#define USART_FIFORDNOPOP_RXNOISE_SHIFT          (15U)
/*! RXNOISE - Received Noise Flag
 */
#define USART_FIFORDNOPOP_RXNOISE(x)             (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
/*! @} */

/*! @name FIFOSIZE - FIFO Size */
/*! @{ */
#define USART_FIFOSIZE_FIFOSIZE_MASK             (0x1FU)
#define USART_FIFOSIZE_FIFOSIZE_SHIFT            (0U)
/*! FIFOSIZE - FIFO Size
 */
#define USART_FIFOSIZE_FIFOSIZE(x)               (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK)
/*! @} */

/*! @name ID - Peripheral Identification */
/*! @{ */
#define USART_ID_APERTURE_MASK                   (0xFFU)
#define USART_ID_APERTURE_SHIFT                  (0U)
/*! APERTURE - Aperture
 */
#define USART_ID_APERTURE(x)                     (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
#define USART_ID_MINOR_REV_MASK                  (0xF00U)
#define USART_ID_MINOR_REV_SHIFT                 (8U)
/*! MINOR_REV - Minor revision of module implementation
 */
#define USART_ID_MINOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
#define USART_ID_MAJOR_REV_MASK                  (0xF000U)
#define USART_ID_MAJOR_REV_SHIFT                 (12U)
/*! MAJOR_REV - Major revision of module implementation
 */
#define USART_ID_MAJOR_REV(x)                    (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
#define USART_ID_ID_MASK                         (0xFFFF0000U)
#define USART_ID_ID_SHIFT                        (16U)
/*! ID - Module identifier for the selected function
 */
#define USART_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USART_Register_Masks */


/* USART - Peripheral instance base addresses */
/** Peripheral USART0 base address */
#define USART0_BASE                              (0x40106000u)
/** Peripheral USART0 base pointer */
#define USART0                                   ((USART_Type *)USART0_BASE)
/** Peripheral USART1 base address */
#define USART1_BASE                              (0x40107000u)
/** Peripheral USART1 base pointer */
#define USART1                                   ((USART_Type *)USART1_BASE)
/** Peripheral USART2 base address */
#define USART2_BASE                              (0x40108000u)
/** Peripheral USART2 base pointer */
#define USART2                                   ((USART_Type *)USART2_BASE)
/** Peripheral USART3 base address */
#define USART3_BASE                              (0x40109000u)
/** Peripheral USART3 base pointer */
#define USART3                                   ((USART_Type *)USART3_BASE)
/** Peripheral USART4 base address */
#define USART4_BASE                              (0x40122000u)
/** Peripheral USART4 base pointer */
#define USART4                                   ((USART_Type *)USART4_BASE)
/** Peripheral USART5 base address */
#define USART5_BASE                              (0x40123000u)
/** Peripheral USART5 base pointer */
#define USART5                                   ((USART_Type *)USART5_BASE)
/** Peripheral USART6 base address */
#define USART6_BASE                              (0x40124000u)
/** Peripheral USART6 base pointer */
#define USART6                                   ((USART_Type *)USART6_BASE)
/** Peripheral USART7 base address */
#define USART7_BASE                              (0x40125000u)
/** Peripheral USART7 base pointer */
#define USART7                                   ((USART_Type *)USART7_BASE)
/** Peripheral USART8 base address */
#define USART8_BASE                              (0x40209000u)
/** Peripheral USART8 base pointer */
#define USART8                                   ((USART_Type *)USART8_BASE)
/** Peripheral USART9 base address */
#define USART9_BASE                              (0x4020A000u)
/** Peripheral USART9 base pointer */
#define USART9                                   ((USART_Type *)USART9_BASE)
/** Peripheral USART10 base address */
#define USART10_BASE                             (0x4020B000u)
/** Peripheral USART10 base pointer */
#define USART10                                  ((USART_Type *)USART10_BASE)
/** Peripheral USART11 base address */
#define USART11_BASE                             (0x4020C000u)
/** Peripheral USART11 base pointer */
#define USART11                                  ((USART_Type *)USART11_BASE)
/** Peripheral USART12 base address */
#define USART12_BASE                             (0x4020D000u)
/** Peripheral USART12 base pointer */
#define USART12                                  ((USART_Type *)USART12_BASE)
/** Peripheral USART13 base address */
#define USART13_BASE                             (0x4020E000u)
/** Peripheral USART13 base pointer */
#define USART13                                  ((USART_Type *)USART13_BASE)
/** Array initializer of USART peripheral base addresses */
#define USART_BASE_ADDRS                         { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE, USART10_BASE, USART11_BASE, USART12_BASE, USART13_BASE }
/** Array initializer of USART peripheral base pointers */
#define USART_BASE_PTRS                          { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9, USART10, USART11, USART12, USART13 }
/** Interrupt vectors for the USART peripheral type */
#define USART_IRQS                               { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }

/*!
 * @}
 */ /* end of group USART_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USBHSDCD Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
 * @{
 */

/** USBHSDCD - Register Layout Typedef */
typedef struct {
  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
  __IO uint32_t STATUS;                            /**< Status register, offset: 0x8 */
  __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
  union {                                          /* offset: 0x18 */
    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
  };
} USBHSDCD_Type;

/* ----------------------------------------------------------------------------
   -- USBHSDCD Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
 * @{
 */

/*! @name CONTROL - Control register */
/*! @{ */
#define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
#define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
/*! IACK - Interrupt Acknowledge
 *  0b0..Do not clear the interrupt.
 *  0b1..Clear the IF bit (interrupt flag).
 */
#define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
#define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
#define USBHSDCD_CONTROL_IF_SHIFT                (8U)
/*! IF - Interrupt Flag
 *  0b0..No interrupt is pending.
 *  0b1..An interrupt is pending.
 */
#define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
#define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
#define USBHSDCD_CONTROL_IE_SHIFT                (16U)
/*! IE - Interrupt Enable
 *  0b0..Disable interrupts to the system.
 *  0b1..Enable interrupts to the system.
 */
#define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
#define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
#define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
/*! BC12 - BC12
 *  0b0..Compatible with BC1.1 (default)
 *  0b1..Compatible with BC1.2
 */
#define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
#define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
#define USBHSDCD_CONTROL_START_SHIFT             (24U)
/*! START - Start Change Detection Sequence
 *  0b0..Do not start the sequence. Writes of this value have no effect.
 *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
 */
#define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
#define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
#define USBHSDCD_CONTROL_SR_SHIFT                (25U)
/*! SR - Software Reset
 *  0b0..Do not perform a software reset.
 *  0b1..Perform a software reset.
 */
#define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
/*! @} */

/*! @name CLOCK - Clock register */
/*! @{ */
#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
 *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
 *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
 */
#define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary
 */
#define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
/*! @} */

/*! @name STATUS - Status register */
/*! @{ */
#define USBHSDCD_STATUS_DP_STATE_MACHINE_MASK    (0xFU)
#define USBHSDCD_STATUS_DP_STATE_MACHINE_SHIFT   (0U)
/*! DP_STATE_MACHINE - Data Pin State Machine
 *  0b0000..IDLE
 *  0b0001..CHECK_DP_LOW
 *  0b0010..DEBOUNCE_DP
 *  0b0011..WAIT_FOR_ONE_MS
 *  0b0100..Not used
 *  0b0101..CHECK_CP
 *  0b0110..CHECK_DM (BC 1.1) or WAIT_AFTER_PRD (BC 1.2)
 *  0b0111..TIMER_DONE_SM (BC 1.1) or CHECK_TYPE (BC 1.2)
 *  0b1000..WAIT_FOR_PULLUP (BC 1.1) or Not used (BC 1.2)
 *  0b1001..WAIT_FOR_CLOCKS (BC 1.1) or Not used (BC 1.2)
 *  0b1010..Not used
 *  0b1110..Not used
 *  0b1111..DONE
 */
#define USBHSDCD_STATUS_DP_STATE_MACHINE(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_DP_STATE_MACHINE_SHIFT)) & USBHSDCD_STATUS_DP_STATE_MACHINE_MASK)
#define USBHSDCD_STATUS_TIM_ACT_MASK             (0x3F00U)
#define USBHSDCD_STATUS_TIM_ACT_SHIFT            (8U)
/*! TIM_ACT - Current Timer Enables Active
 */
#define USBHSDCD_STATUS_TIM_ACT(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TIM_ACT_SHIFT)) & USBHSDCD_STATUS_TIM_ACT_MASK)
#define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
#define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
/*! SEQ_RES - Charger Detection Sequence Results
 *  0b00..No results to report.
 *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
 *  0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
 *        DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
 *        detection has completed.)
 *  0b11..Attached to a DCP.
 */
#define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
#define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
#define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
/*! SEQ_STAT - Charger Detection Sequence Status
 *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
 *  0b01..Data pin contact detection is complete.
 *  0b10..Charging port detection is complete.
 *  0b11..Charger type detection is complete.
 */
#define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
#define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
#define USBHSDCD_STATUS_ERR_SHIFT                (20U)
/*! ERR - Error Flag
 *  0b0..No sequence errors.
 *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
 */
#define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
#define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
#define USBHSDCD_STATUS_TO_SHIFT                 (21U)
/*! TO - Timeout Flag
 *  0b0..The detection sequence has not been running for over 1 s.
 *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
 */
#define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
#define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
#define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
/*! ACTIVE - Active Status Indicator
 *  0b0..The sequence is not running.
 *  0b1..The sequence is running.
 */
#define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
/*! @} */

/*! @name SIGNAL_OVERRIDE - Signal Override Register */
/*! @{ */
#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
/*! PS - Phase Selection
 *  0b00..No overrides. Same behavior as functional mode.
 *  0b01..Signals usbdcd_en and usbdcd_data_cont_det_en to analog block are forced high. Enables IDP_SRC and RDM_DWN.
 *  0b10..Signals usbdcd_en and usbdcd_chg_det_en to analog block are forced high. Enables VDP_SRC and IDM_SINK.
 *  0b11..For USB Battery Charging Specification, Revision 1.2 parameters. Signals usbdcd_en and usbdcd_dcp_det_en
 *        to analog block are forced high. Enables VDM_SRC and IDP_SINK.
 */
#define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
#define USBHSDCD_SIGNAL_OVERRIDE_DMIR_MASK       (0x100U)
#define USBHSDCD_SIGNAL_OVERRIDE_DMIR_SHIFT      (8U)
/*! DMIR - usbdcd_dm_in_range (DMIR) status in selected phase
 *  0b0..D- voltage is not within the defined range.
 *  0b1..D- voltage is within the defined range.
 */
#define USBHSDCD_SIGNAL_OVERRIDE_DMIR(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_DMIR_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_DMIR_MASK)
#define USBHSDCD_SIGNAL_OVERRIDE_DPIR_MASK       (0x200U)
#define USBHSDCD_SIGNAL_OVERRIDE_DPIR_SHIFT      (9U)
/*! DPIR - usbdcd_dp_in_range (DPIR) status in selected phase
 *  0b0..D+ voltage is not within the defined range.
 *  0b1..D+ voltage is within the defined range.
 */
#define USBHSDCD_SIGNAL_OVERRIDE_DPIR(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_DPIR_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_DPIR_MASK)
/*! @} */

/*! @name TIMER0 - TIMER0 register */
/*! @{ */
#define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
#define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
/*! TUNITCON - Unit Connection Timer Elapse (in ms)
 */
#define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
#define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
/*! TSEQ_INIT - Sequence Initiation Time
 */
#define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
/*! @} */

/*! @name TIMER1 - TIMER1 register */
/*! @{ */
#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
/*! TVDPSRC_ON - Time Period Comparator Enabled
 */
#define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
#define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
/*! TDCD_DBNC - Time Period to Debounce D+ Signal
 */
#define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
/*! @} */

/*! @name TIMER2_BC11 - TIMER2_BC11 register */
/*! @{ */
#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
/*! CHECK_DM - Time Before Check of D- Line
 */
#define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
 */
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
/*! @} */

/*! @name TIMER2_BC12 - TIMER2_BC12 register */
/*! @{ */
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
/*! TVDMSRC_ON - TVDMSRC_ON
 */
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
 */
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USBHSDCD_Register_Masks */


/* USBHSDCD - Peripheral instance base addresses */
/** Peripheral USBHSDCD base address */
#define USBHSDCD_BASE                            (0x4013B800u)
/** Peripheral USBHSDCD base pointer */
#define USBHSDCD                                 ((USBHSDCD_Type *)USBHSDCD_BASE)
/** Array initializer of USBHSDCD peripheral base addresses */
#define USBHSDCD_BASE_ADDRS                      { USBHSDCD_BASE }
/** Array initializer of USBHSDCD peripheral base pointers */
#define USBHSDCD_BASE_PTRS                       { USBHSDCD }

/*!
 * @}
 */ /* end of group USBHSDCD_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- USDHC Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
 * @{
 */

/** USDHC - Register Layout Typedef */
typedef struct {
  __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
  __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
  __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
  __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
  __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
  __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
  __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
  __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
  __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
  __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
  __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
  __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
  __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
  __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
  __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
  __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
  __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
  __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
  __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
       uint8_t RESERVED_0[4];
  __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
  __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
  __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
       uint8_t RESERVED_1[4];
  __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
  __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
  __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
       uint8_t RESERVED_2[4];
  __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
  __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
       uint8_t RESERVED_3[72];
  __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
  __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
  __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
  __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
       uint8_t RESERVED_4[44];
  __I  uint32_t HOST_CTRL_VER;                     /**< Host controller version, offset: 0xFC */
       uint32_t CQE;                               /**< Command Queue, offset: 0x100 */
} USDHC_Type;

/* ----------------------------------------------------------------------------
   -- USDHC Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup USDHC_Register_Masks USDHC Register Masks
 * @{
 */

/*! @name DS_ADDR - DMA System Address */
/*! @{ */
#define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
/*! DS_ADDR - System address
 */
#define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */

/*! @name BLK_ATT - Block Attributes */
/*! @{ */
#define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
/*! BLKSIZE - Transfer block size
 *  0b1000000000000..4096 bytes
 *  0b0100000000000..2048 bytes
 *  0b0001000000000..512 bytes
 *  0b0000111111111..511 bytes
 *  0b0000000000100..4 bytes
 *  0b0000000000011..3 bytes
 *  0b0000000000010..2 bytes
 *  0b0000000000001..1 byte
 *  0b0000000000000..No data transfer
 */
#define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
/*! BLKCNT - Blocks count for current transfer
 *  0b1111111111111111..65535 blocks
 *  0b0000000000000010..2 blocks
 *  0b0000000000000001..1 block
 *  0b0000000000000000..Stop count
 */
#define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */

/*! @name CMD_ARG - Command Argument */
/*! @{ */
#define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
/*! CMDARG - Command argument
 */
#define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */

/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */
#define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
/*! RSPTYP - Response type select
 *  0b00..No response
 *  0b01..Response length 136
 *  0b10..Response length 48
 *  0b11..Response length 48, check busy after response
 */
#define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
/*! CCCEN - Command CRC check enable
 *  0b1..Enables command CRC check
 *  0b0..Disables command CRC check
 */
#define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
/*! CICEN - Command index check enable
 *  0b1..Enables command index check
 *  0b0..Disable command index check
 */
#define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
/*! DPSEL - Data present select
 *  0b1..Data present
 *  0b0..No data present
 */
#define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
/*! CMDTYP - Command type
 *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
 *  0b10..Resume CMD52 for writing function select in CCCR
 *  0b01..Suspend CMD52 for writing bus suspend in CCCR
 *  0b00..Normal other commands
 */
#define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
/*! CMDINX - Command index
 */
#define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */

/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */
#define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
/*! CMDRSP0 - Command response 0
 */
#define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */

/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */
#define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
/*! CMDRSP1 - Command response 1
 */
#define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */

/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */
#define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
/*! CMDRSP2 - Command response 2
 */
#define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */

/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */
#define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
/*! CMDRSP3 - Command response 3
 */
#define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */

/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
/*! DATCONT - Data content
 */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */

/*! @name PRES_STATE - Present State */
/*! @{ */
#define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
/*! CIHB - Command inhibit (CMD)
 *  0b1..Cannot issue command
 *  0b0..Can issue command using only CMD line
 */
#define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
/*! CDIHB - Command inhibit (DATA)
 *  0b1..Cannot issue command that uses the DATA line
 *  0b0..Can issue command that uses the DATA line
 */
#define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define USDHC_PRES_STATE_DLA_MASK                (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT               (2U)
/*! DLA - Data line active
 *  0b1..DATA line active
 *  0b0..DATA line inactive
 */
#define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
/*! SDSTB - SD clock stable
 *  0b1..Clock is stable.
 *  0b0..Clock is changing frequency and not stable.
 */
#define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
#define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
/*! IPGOFF - Peripheral clock gated off internally
 *  0b1..Peripheral clock is gated off.
 *  0b0..Peripheral clock is active.
 */
#define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
#define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
/*! HCKOFF - HCLK gated off internally
 *  0b1..HCLK is gated off.
 *  0b0..HCLK is active.
 */
#define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
#define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
/*! PEROFF - IPG_PERCLK gated off internally
 *  0b1..IPG_PERCLK is gated off.
 *  0b0..IPG_PERCLK is active.
 */
#define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
#define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
/*! SDOFF - SD clock gated off internally
 *  0b1..SD clock is gated off.
 *  0b0..SD clock is active.
 */
#define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define USDHC_PRES_STATE_WTA_MASK                (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT               (8U)
/*! WTA - Write transfer active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define USDHC_PRES_STATE_RTA_MASK                (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT               (9U)
/*! RTA - Read transfer active
 *  0b1..Transferring data
 *  0b0..No valid data
 */
#define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
/*! BWEN - Buffer write enable
 *  0b1..Write enable
 *  0b0..Write disable
 */
#define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define USDHC_PRES_STATE_BREN_MASK               (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT              (11U)
/*! BREN - Buffer read enable
 *  0b1..Read enable
 *  0b0..Read disable
 */
#define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
#define USDHC_PRES_STATE_RTR_SHIFT               (12U)
/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
 *  0b1..Sampling clock needs re-tuning
 *  0b0..Fixed or well tuned sampling clock
 */
#define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
#define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
#define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
/*! TSCD - Tape select change done
 *  0b1..Delay cell select change is finished.
 *  0b0..Delay cell select change is not finished.
 */
#define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
#define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT             (16U)
/*! CINST - Card inserted
 *  0b1..Card inserted
 *  0b0..Power on reset or no card
 */
#define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
/*! CDPL - Card detect pin level
 *  0b1..Card present (CD_B = 0)
 *  0b0..No card present (CD_B = 1)
 */
#define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
/*! WPSPL - Write protect switch pin level
 *  0b1..Write enabled (WP = 0)
 *  0b0..Write protected (WP = 1)
 */
#define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
/*! CLSL - CMD line signal level
 */
#define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
/*! DLSL - DATA[7:0] line signal level
 *  0b00000111..Data 7 line signal level
 *  0b00000110..Data 6 line signal level
 *  0b00000101..Data 5 line signal level
 *  0b00000100..Data 4 line signal level
 *  0b00000011..Data 3 line signal level
 *  0b00000010..Data 2 line signal level
 *  0b00000001..Data 1 line signal level
 *  0b00000000..Data 0 line signal level
 */
#define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */

/*! @name PROT_CTRL - Protocol Control */
/*! @{ */
#define USDHC_PROT_CTRL_LCTL_MASK                (0x1U)
#define USDHC_PROT_CTRL_LCTL_SHIFT               (0U)
/*! LCTL - LED control
 *  0b1..LED on
 *  0b0..LED off
 */
#define USDHC_PROT_CTRL_LCTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
#define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
/*! DTW - Data transfer width
 *  0b10..8-bit mode
 *  0b01..4-bit mode
 *  0b00..1-bit mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
/*! D3CD - DATA3 as card detection pin
 *  0b1..DATA3 as card detection pin
 *  0b0..DATA3 does not monitor card insertion
 */
#define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
/*! EMODE - Endian mode
 *  0b00..Big endian mode
 *  0b01..Half word big endian mode
 *  0b10..Little endian mode
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
#define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
/*! CDTL - Card detect test level
 *  0b1..Card detect test level is 1, card inserted
 *  0b0..Card detect test level is 0, no card inserted
 */
#define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
#define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
/*! CDSS - Card detect signal selection
 *  0b1..Card detection test level is selected (for test purpose).
 *  0b0..Card detection level is selected (for normal purpose).
 */
#define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
/*! DMASEL - DMA select
 *  0b00..No DMA or simple DMA is selected.
 *  0b01..ADMA1 is selected.
 *  0b10..ADMA2 is selected.
 *  0b11..Reserved
 */
#define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
/*! SABGREQ - Stop at block gap request
 *  0b1..Stop
 *  0b0..Transfer
 */
#define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
/*! CREQ - Continue request
 *  0b1..Restart
 *  0b0..No effect
 */
#define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
/*! RWCTL - Read wait control
 *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
 *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
 */
#define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
/*! IABG - Interrupt at block gap
 *  0b1..Enables interrupt at block gap
 *  0b0..Disables interrupt at block gap
 */
#define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
/*! RD_DONE_NO_8CLK - Read performed number 8 clock
 */
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define USDHC_PROT_CTRL_RD_WAIT_POINT_MASK       (0xE00000U)
#define USDHC_PROT_CTRL_RD_WAIT_POINT_SHIFT      (21U)
/*! RD_WAIT_POINT - Read wait point
 */
#define USDHC_PROT_CTRL_RD_WAIT_POINT(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_WAIT_POINT_SHIFT)) & USDHC_PROT_CTRL_RD_WAIT_POINT_MASK)
#define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
/*! WECINT - Wakeup event enable on card interrupt
 *  0b1..Enables wakeup event enable on card interrupt
 *  0b0..Disables wakeup event enable on card interrupt
 */
#define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
/*! WECINS - Wakeup event enable on SD card insertion
 *  0b1..Enable wakeup event enable on SD card insertion
 *  0b0..Disable wakeup event enable on SD card insertion
 */
#define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
/*! WECRM - Wakeup event enable on SD card removal
 *  0b1..Enables wakeup event enable on SD card removal
 *  0b0..Disables wakeup event enable on SD card removal
 */
#define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK        (0x38000000U)
#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT       (27U)
/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
 *  0bxx1..Burst length is enabled for INCR.
 *  0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16.
 *  0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP.
 */
#define USDHC_PROT_CTRL_BURST_LEN_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
/*! NON_EXACT_BLK_RD - Non-exact block read
 *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
 *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
 */
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
#define USDHC_PROT_CTRL_RD_NO8CLK_EN_MASK        (0x80000000U)
#define USDHC_PROT_CTRL_RD_NO8CLK_EN_SHIFT       (31U)
/*! RD_NO8CLK_EN - Enable the software RD_DONE_NO_8CLK
 *  0b1..the software RD_DONE_NO_8CLK is enabled.
 *  0b0..Disable the software RD_DONE_NO_8CLK, uSHDC determines if 8 clocks are needed automatically.
 */
#define USDHC_PROT_CTRL_RD_NO8CLK_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_NO8CLK_EN_SHIFT)) & USDHC_PROT_CTRL_RD_NO8CLK_EN_MASK)
/*! @} */

/*! @name SYS_CTRL - System Control */
/*! @{ */
#define USDHC_SYS_CTRL_IPGEN_MASK                (0x1U)
#define USDHC_SYS_CTRL_IPGEN_SHIFT               (0U)
/*! IPGEN - IPG clock enable
 */
#define USDHC_SYS_CTRL_IPGEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPGEN_SHIFT)) & USDHC_SYS_CTRL_IPGEN_MASK)
#define USDHC_SYS_CTRL_HCKEN_MASK                (0x2U)
#define USDHC_SYS_CTRL_HCKEN_SHIFT               (1U)
/*! HCKEN - HCLK enable
 */
#define USDHC_SYS_CTRL_HCKEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_HCKEN_SHIFT)) & USDHC_SYS_CTRL_HCKEN_MASK)
#define USDHC_SYS_CTRL_PEREN_MASK                (0x4U)
#define USDHC_SYS_CTRL_PEREN_SHIFT               (2U)
/*! PEREN - Peripheral clock enable
 */
#define USDHC_SYS_CTRL_PEREN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_PEREN_SHIFT)) & USDHC_SYS_CTRL_PEREN_MASK)
#define USDHC_SYS_CTRL_SDCLKEN_MASK              (0x8U)
#define USDHC_SYS_CTRL_SDCLKEN_SHIFT             (3U)
/*! SDCLKEN - SD clock enable
 */
#define USDHC_SYS_CTRL_SDCLKEN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKEN_SHIFT)) & USDHC_SYS_CTRL_SDCLKEN_MASK)
#define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
/*! DVS - Divisor
 *  0b0000..Divide-by-1
 *  0b0001..Divide-by-2
 *  0b1110..Divide-by-15
 *  0b1111..Divide-by-16
 */
#define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
/*! SDCLKFS - SDCLK frequency select
 */
#define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
/*! DTOCV - Data timeout counter value
 *  0b1111..SDCLK x 2 29 + SDCLK x 2 28 + SDCLK x 2 27 + SDCLK x 2 26
 *  0b1110..SDCLK x 2 28
 *  0b1101..SDCLK x 2 27
 *  0b1100..SDCLK x 2 26
 *  0b1011..SDCLK x 2 25
 *  0b1010..SDCLK x 2 24
 *  0b1001..SDCLK x 2 23
 *  0b1000..SDCLK x 2 22
 *  0b0111..SDCLK x 2 21
 *  0b0110..SDCLK x 2 20
 *  0b0101..SDCLK x 2 19
 *  0b0100..SDCLK x 2 18
 *  0b0011..SDCLK x 2 17
 *  0b0010..SDCLK x 2 16
 *  0b0001..SDCLK x 2 15
 *  0b0000..SDCLK x 2 14
 */
#define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define USDHC_SYS_CTRL_RST_STROBE_FIFO_MASK      (0x200000U)
#define USDHC_SYS_CTRL_RST_STROBE_FIFO_SHIFT     (21U)
/*! RST_STROBE_FIFO - Reset the async STROBE FIFO
 */
#define USDHC_SYS_CTRL_RST_STROBE_FIFO(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_STROBE_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_STROBE_FIFO_MASK)
#define USDHC_SYS_CTRL_RST_FIFO_MASK             (0x400000U)
#define USDHC_SYS_CTRL_RST_FIFO_SHIFT            (22U)
/*! RST_FIFO - Reset the async FIFO
 */
#define USDHC_SYS_CTRL_RST_FIFO(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK)
#define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
/*! IPP_RST_N - Hardware reset
 */
#define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
/*! RSTA - Software reset for all
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
/*! RSTC - Software reset for CMD line
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
/*! RSTD - Software reset for data line
 *  0b1..Reset
 *  0b0..No reset
 */
#define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
/*! INITA - Initialization active
 */
#define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
#define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
#define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
/*! RSTT - Reset tuning
 */
#define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
/*! @} */

/*! @name INT_STATUS - Interrupt Status */
/*! @{ */
#define USDHC_INT_STATUS_CC_MASK                 (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT                (0U)
/*! CC - Command complete
 *  0b1..Command complete
 *  0b0..Command not complete
 */
#define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define USDHC_INT_STATUS_TC_MASK                 (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT                (1U)
/*! TC - Transfer complete
 *  0b1..Transfer complete
 *  0b0..Transfer does not complete
 */
#define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define USDHC_INT_STATUS_BGE_MASK                (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT               (2U)
/*! BGE - Block gap event
 *  0b1..Transaction stopped at block gap
 *  0b0..No block gap event
 */
#define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define USDHC_INT_STATUS_DINT_MASK               (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT              (3U)
/*! DINT - DMA interrupt
 *  0b1..DMA interrupt is generated.
 *  0b0..No DMA interrupt
 */
#define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define USDHC_INT_STATUS_BWR_MASK                (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT               (4U)
/*! BWR - Buffer write ready
 *  0b1..Ready to write buffer
 *  0b0..Not ready to write buffer
 */
#define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define USDHC_INT_STATUS_BRR_MASK                (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT               (5U)
/*! BRR - Buffer read ready
 *  0b1..Ready to read buffer
 *  0b0..Not ready to read buffer
 */
#define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define USDHC_INT_STATUS_CINS_MASK               (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT              (6U)
/*! CINS - Card insertion
 *  0b1..Card inserted
 *  0b0..Card state unstable or removed
 */
#define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define USDHC_INT_STATUS_CRM_MASK                (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT               (7U)
/*! CRM - Card removal
 *  0b1..Card removed
 *  0b0..Card state unstable or inserted
 */
#define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define USDHC_INT_STATUS_CINT_MASK               (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT              (8U)
/*! CINT - Card interrupt
 *  0b1..Generate card interrupt
 *  0b0..No card interrupt
 */
#define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
#define USDHC_INT_STATUS_RTE_SHIFT               (12U)
/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
 *  0b1..Re-tuning should be performed.
 *  0b0..Re-tuning is not required.
 */
#define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
#define USDHC_INT_STATUS_TP_MASK                 (0x2000U)
#define USDHC_INT_STATUS_TP_SHIFT                (13U)
/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
 */
#define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
#define USDHC_INT_STATUS_CQI_MASK                (0x4000U)
#define USDHC_INT_STATUS_CQI_SHIFT               (14U)
/*! CQI - Command queuing interrupt
 */
#define USDHC_INT_STATUS_CQI(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)
#define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
/*! CTOE - Command timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT               (17U)
/*! CCE - Command CRC error
 *  0b1..CRC error generated
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
/*! CEBE - Command end bit error
 *  0b1..End bit error generated
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT               (19U)
/*! CIE - Command index error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
/*! DTOE - Data timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT               (21U)
/*! DCE - Data CRC error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
/*! DEBE - Data end bit error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
/*! AC12E - Auto CMD12 error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
#define USDHC_INT_STATUS_TNE_SHIFT               (26U)
/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
 */
#define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
#define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
/*! DMAE - DMA error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */

/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */
#define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
/*! CCSEN - Command complete status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
/*! TCSEN - Transfer complete status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
/*! BGESEN - Block gap event status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
/*! DINTSEN - DMA interrupt status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
/*! BWRSEN - Buffer write ready status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
/*! BRRSEN - Buffer read ready status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
/*! CINSSEN - Card insertion status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
/*! CRMSEN - Card removal status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
/*! CINTSEN - Card interrupt status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
#define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
/*! RTESEN - Re-tuning event status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
#define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x2000U)
#define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (13U)
/*! TPSEN - Tuning pass status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
#define USDHC_INT_STATUS_EN_CQISEN_MASK          (0x4000U)
#define USDHC_INT_STATUS_EN_CQISEN_SHIFT         (14U)
/*! CQISEN - Command queuing status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CQISEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)
#define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
/*! CTOESEN - Command timeout error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
/*! CCESEN - Command CRC error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
/*! CEBESEN - Command end bit error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
/*! CIESEN - Command index error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
/*! DTOESEN - Data timeout error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
/*! DCESEN - Data CRC error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
/*! DEBESEN - Data end bit error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
/*! AC12ESEN - Auto CMD12 error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
/*! TNESEN - Tuning error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
#define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
/*! DMAESEN - DMA error status enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */

/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */
#define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
/*! CCIEN - Command complete interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
/*! TCIEN - Transfer complete interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
/*! BGEIEN - Block gap event interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
/*! DINTIEN - DMA interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
/*! BWRIEN - Buffer write ready interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
/*! BRRIEN - Buffer read ready interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
/*! CINSIEN - Card insertion interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
/*! CRMIEN - Card removal interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
/*! CINTIEN - Card interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
/*! RTEIEN - Re-tuning event interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x2000U)
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (13U)
/*! TPIEN - Tuning pass interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK          (0x4000U)
#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT         (14U)
/*! CQIIEN - Command queuing signal enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CQIIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
/*! CTOEIEN - Command timeout error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
/*! CCEIEN - Command CRC error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
/*! CEBEIEN - Command end bit error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
/*! CIEIEN - Command index error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
/*! DTOEIEN - Data timeout error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
/*! DCEIEN - Data CRC error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
/*! DEBEIEN - Data end bit error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
/*! AC12EIEN - Auto CMD12 error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
/*! TNEIEN - Tuning error interrupt enable
 *  0b1..Enabled
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
/*! DMAEIEN - DMA error interrupt enable
 *  0b1..Enable
 *  0b0..Masked
 */
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */

/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
/*! AC12NE - Auto CMD12 not executed
 *  0b1..Not executed
 *  0b0..Executed
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
/*! AC12TOE - Auto CMD12 / 23 timeout error
 *  0b1..Time out
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
/*! AC12EBE - Auto CMD12 / 23 end bit error
 *  0b1..End bit error generated
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
/*! AC12CE - Auto CMD12 / 23 CRC error
 *  0b1..CRC error met in Auto CMD12/23 response
 *  0b0..No CRC error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
/*! AC12IE - Auto CMD12 / 23 index error
 *  0b1..Error, the CMD index in response is not CMD12/23
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
/*! CNIBAC12E - Command not issued by Auto CMD12 error
 *  0b1..Not issued
 *  0b0..No error
 */
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
/*! EXECUTE_TUNING - Execute tuning
 */
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Sample clock select
 *  0b1..Tuned clock is used to sample data
 *  0b0..Fixed clock is used to sample data
 */
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
/*! @} */

/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
/*! SDR50_SUPPORT - SDR50 support
 */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
/*! SDR104_SUPPORT - SDR104 support
 */
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
/*! DDR50_SUPPORT - DDR50 support
 */
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
/*! TIME_COUNT_RETUNING - Time counter for retuning
 */
#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
/*! USE_TUNING_SDR50 - Use Tuning for SDR50
 *  0b1..SDR50 requires tuning.
 *  0b0..SDR does not require tuning.
 */
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK   (0xC000U)
#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT  (14U)
/*! RETUNING_MODE - Retuning Mode
 *  0b00..Mode 1
 *  0b01..Mode 2
 *  0b10..Mode 3
 *  0b11..Reserved
 */
#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
#define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
/*! MBL - Max block length
 *  0b000..512 bytes
 *  0b001..1024 bytes
 *  0b010..2048 bytes
 *  0b011..4096 bytes
 */
#define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
/*! ADMAS - ADMA support
 *  0b1..Advanced DMA supported
 *  0b0..Advanced DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
/*! HSS - High speed support
 *  0b1..High speed supported
 *  0b0..High speed not supported
 */
#define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
/*! DMAS - DMA support
 *  0b1..DMA supported
 *  0b0..DMA not supported
 */
#define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
/*! SRS - Suspend / resume support
 *  0b1..Supported
 *  0b0..Not supported
 */
#define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
/*! VS33 - Voltage support 3.3 V
 *  0b1..3.3 V supported
 *  0b0..3.3 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
/*! VS30 - Voltage support 3.0 V
 *  0b1..3.0 V supported
 *  0b0..3.0 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
/*! VS18 - Voltage support 1.8 V
 *  0b1..1.8 V supported
 *  0b0..1.8 V not supported
 */
#define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */

/*! @name WTMK_LVL - Watermark Level */
/*! @{ */
#define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
/*! RD_WML - Read watermark level
 */
#define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK          (0x1F00U)
#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT         (8U)
/*! RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16
 */
#define USDHC_WTMK_LVL_RD_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
#define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
/*! WR_WML - Write watermark level
 */
#define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK          (0x1F000000U)
#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT         (24U)
/*! WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16
 */
#define USDHC_WTMK_LVL_WR_BRST_LEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
/*! @} */

/*! @name MIX_CTRL - Mixer Control */
/*! @{ */
#define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
/*! DMAEN - DMA enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
/*! BCEN - Block count enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
/*! AC12EN - Auto CMD12 enable
 *  0b1..Enable
 *  0b0..Disable
 */
#define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
/*! DDR_EN - Dual data rate mode selection
 */
#define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
/*! DTDSEL - Data transfer direction select
 *  0b1..Read (Card to host)
 *  0b0..Write (Host to card)
 */
#define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
/*! MSBSEL - Multi / Single block select
 *  0b1..Multiple blocks
 *  0b0..Single block
 */
#define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
/*! NIBBLE_POS - Nibble position indication
 */
#define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
/*! AC23EN - Auto CMD23 enable
 */
#define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
 *  0b1..Execute tuning
 *  0b0..Not tuned or tuning completed
 */
#define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
/*! SMP_CLK_SEL - Clock selection
 *  0b1..Tuned clock is used to sample data / cmd
 *  0b0..Fixed clock is used to sample data / cmd
 */
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
 *  0b1..Enable auto tuning
 *  0b0..Disable auto tuning
 */
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
#define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
 *  0b1..Feedback clock comes from the ipp_card_clk_out
 *  0b0..Feedback clock comes from the loopback CLK
 */
#define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
#define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
#define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
/*! HS400_MODE - Enable HS400 mode
 */
#define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK        (0x8000000U)
#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT       (27U)
/*! EN_HS400_MODE - Enable enhance HS400 mode
 */
#define USDHC_MIX_CTRL_EN_HS400_MODE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
#define USDHC_MIX_CTRL_AC12_RD_POINT_MASK        (0x20000000U)
#define USDHC_MIX_CTRL_AC12_RD_POINT_SHIFT       (29U)
/*! AC12_RD_POINT - AC12_RD_POINT
 *  0b1..Send Auto CMD12 8 cycles after CRC is checked successfully
 *  0b0..Send Auto CMD12 right after CRC is checked successfully
 */
#define USDHC_MIX_CTRL_AC12_RD_POINT(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12_RD_POINT_SHIFT)) & USDHC_MIX_CTRL_AC12_RD_POINT_MASK)
#define USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_MASK     (0x40000000U)
#define USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_SHIFT    (30U)
/*! CMD_DMY_WAIT_CFG - CMD_DMY_WAIT_CFG
 */
#define USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_SHIFT)) & USDHC_MIX_CTRL_CMD_DMY_WAIT_CFG_MASK)
#define USDHC_MIX_CTRL_CMD_DMY_EN_MASK           (0x80000000U)
#define USDHC_MIX_CTRL_CMD_DMY_EN_SHIFT          (31U)
/*! CMD_DMY_EN - CMD_DMY_EN
 */
#define USDHC_MIX_CTRL_CMD_DMY_EN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_CMD_DMY_EN_SHIFT)) & USDHC_MIX_CTRL_CMD_DMY_EN_MASK)
/*! @} */

/*! @name FORCE_EVENT - Force Event */
/*! @{ */
#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
/*! FEVTAC12NE - Force event auto command 12 not executed
 */
#define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
/*! FEVTAC12TOE - Force event auto command 12 time out error
 */
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
/*! FEVTAC12CE - Force event auto command 12 CRC error
 */
#define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
/*! FEVTAC12EBE - Force event Auto Command 12 end bit error
 */
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
/*! FEVTAC12IE - Force event Auto Command 12 index error
 */
#define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
 */
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
/*! FEVTCTOE - Force event command time out error
 */
#define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
/*! FEVTCCE - Force event command CRC error
 */
#define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
/*! FEVTCEBE - Force event command end bit error
 */
#define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
/*! FEVTCIE - Force event command index error
 */
#define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
/*! FEVTDTOE - Force event data time out error
 */
#define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
/*! FEVTDCE - Force event data CRC error
 */
#define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
/*! FEVTDEBE - Force event data end bit error
 */
#define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
/*! FEVTAC12E - Force event Auto Command 12 error
 */
#define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
/*! FEVTTNE - Force tuning error
 */
#define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
#define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
/*! FEVTDMAE - Force event DMA error
 */
#define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
/*! FEVTCINT - Force event card interrupt
 */
#define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */

/*! @name ADMA_ERR_STATUS - ADMA Error Status */
/*! @{ */
#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
/*! ADMAES - ADMA error state (when ADMA error is occurred)
 */
#define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
/*! ADMALME - ADMA length mismatch error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
/*! ADMADCE - ADMA descriptor error
 *  0b1..Error
 *  0b0..No error
 */
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */

/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
/*! ADS_ADDR - ADMA system address
 */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */

/*! @name DLL_CTRL - DLL (Delay Line) Control */
/*! @{ */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
/*! DLL_CTRL_ENABLE - DLL and delay chain
 */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
/*! DLL_CTRL_RESET - DLL reset
 */
#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! DLL_CTRL_GATE_UPDATE - DLL gate update
 */
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
 */
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
 */
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name DLL_STATUS - DLL Status */
/*! @{ */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
/*! DLL_STS_SLV_LOCK - Slave delay-line lock status
 */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
/*! DLL_STS_REF_LOCK - Reference DLL lock status
 */
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
/*! DLL_STS_SLV_SEL - Slave delay line select status
 */
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
/*! DLL_STS_REF_SEL - Reference delay line select taps
 */
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
/*! @{ */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
/*! NXT_ERR - NXT error
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
/*! TAP_SEL_PRE - TAP_SEL_PRE
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
/*! PRE_ERR - PRE error
 */
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
/*! @} */

/*! @name STROBE_DLL_CTRL - Strobe DLL control */
/*! @{ */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U)
/*! STROBE_DLL_CTRL_GATE_UPDATE_0 - Strobe DLL control gate update
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U)
/*! STROBE_DLL_CTRL_GATE_UPDATE_1 - Strobe DLL control gate update
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
 */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */

/*! @name STROBE_DLL_STATUS - Strobe DLL status */
/*! @{ */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
 */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
 */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
 */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
 */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
/*! @} */

/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */
#define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
/*! VSELECT - Voltage selection
 *  0b1..Change the voltage to low voltage range, around 1.8 V
 *  0b0..Change the voltage to high voltage range, around 3.0 V
 */
#define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
/*! CONFLICT_CHK_EN - Conflict check enable
 *  0b0..Conflict check disable
 *  0b1..Conflict check enable
 */
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
/*! AC12_WR_CHKBUSY_EN - Check busy enable
 *  0b0..Do not check busy after auto CMD12 for write data packet
 *  0b1..Check busy after auto CMD12 for write data packet
 */
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK         (0x10U)
#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT        (4U)
/*! DAT3_CD_POL - DATA3 pin polarity
 *  0b0..Card detected when DATA3 is high.
 *  0b1..Card detected when DATA3 is low.
 */
#define USDHC_VEND_SPEC_DAT3_CD_POL(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK)
#define USDHC_VEND_SPEC_CD_POL_MASK              (0x20U)
#define USDHC_VEND_SPEC_CD_POL_SHIFT             (5U)
/*! CD_POL - CD Polarity
 *  0b0..CD_B pin is low active.
 *  0b1..CD_B pin is high active.
 */
#define USDHC_VEND_SPEC_CD_POL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK)
#define USDHC_VEND_SPEC_WP_POL_MASK              (0x40U)
#define USDHC_VEND_SPEC_WP_POL_SHIFT             (6U)
/*! WP_POL - WP polarity
 *  0b0..WP pin is high active.
 *  0b1..WP pin is low active.
 */
#define USDHC_VEND_SPEC_WP_POL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK)
#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK     (0x80U)
#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT    (7U)
/*! CLKONJ_IN_ABORT - Force CLK output active
 *  0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO
 *       is full (for read) or empty (for write).
 *  0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is
 *       full (for read) or empty (for write).
 */
#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
/*! FRC_SDCLK_ON - Force CLK
 *  0b0..CLK active or inactive is fully controlled by the hardware.
 *  0b1..Force CLK active
 */
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define USDHC_VEND_SPEC_AC12_ISNOT_ABORT_MASK    (0x200U)
#define USDHC_VEND_SPEC_AC12_ISNOT_ABORT_SHIFT   (9U)
/*! AC12_ISNOT_ABORT - Auto CMD12 abort
 *  0b0..Hardware treats the Auto CMD12 as abort command.
 *  0b1..Hardware does not treat the Auto CMD12 as abort command.
 */
#define USDHC_VEND_SPEC_AC12_ISNOT_ABORT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_ISNOT_ABORT_SHIFT)) & USDHC_VEND_SPEC_AC12_ISNOT_ABORT_MASK)
#define USDHC_VEND_SPEC_DDREN_ACT_ATONCE_MASK    (0x400U)
#define USDHC_VEND_SPEC_DDREN_ACT_ATONCE_SHIFT   (10U)
/*! DDREN_ACT_ATONCE - DDR enable
 *  0b0..DDR_EN setting becomes active only when the DATA and CMD line are idle.
 *  0b1..DDR_EN setting becomes active at once no matter what the state of the DATA and CMD line are.
 */
#define USDHC_VEND_SPEC_DDREN_ACT_ATONCE(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DDREN_ACT_ATONCE_SHIFT)) & USDHC_VEND_SPEC_DDREN_ACT_ATONCE_MASK)
#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK     (0x800U)
#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT    (11U)
/*! IPG_CLK_SOFT_EN - Peripheral clock software enable
 *  0b0..Gate off the peripheral clock
 *  0b1..Enable the peripheral clock
 */
#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK        (0x1000U)
#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT       (12U)
/*! HCLK_SOFT_EN - AHB clock software enable
 *  0b0..Gate off the AHB clock.
 *  0b1..Enable the AHB clock.
 */
#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK  (0x2000U)
#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U)
/*! IPG_PERCLK_SOFT_EN - IPG_PERCLK software enable
 *  0b0..Gate off the IPG_PERCLK
 *  0b1..Enable the IPG_PERCLK
 */
#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK    (0x4000U)
#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT   (14U)
/*! CARD_CLK_SOFT_EN - Card clock software enable
 *  0b0..Gate off the sd_clk
 *  0b1..Enable the sd_clk
 */
#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
/*! CRC_CHK_DIS - CRC Check Disable
 *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
 *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
 */
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define USDHC_VEND_SPEC_INT_ST_VAL_MASK          (0xFF0000U)
#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT         (16U)
/*! INT_ST_VAL - Internal State Value
 */
#define USDHC_VEND_SPEC_INT_ST_VAL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK)
#define USDHC_VEND_SPEC_DBG_SEL_MASK             (0xF000000U)
#define USDHC_VEND_SPEC_DBG_SEL_SHIFT            (24U)
/*! DBG_SEL - Debug Select
 */
#define USDHC_VEND_SPEC_DBG_SEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DBG_SEL_SHIFT)) & USDHC_VEND_SPEC_DBG_SEL_MASK)
#define USDHC_VEND_SPEC_CMD_OE_PRE_EN_MASK       (0x10000000U)
#define USDHC_VEND_SPEC_CMD_OE_PRE_EN_SHIFT      (28U)
/*! CMD_OE_PRE_EN - Assert point of CMD_OE signal
 *  0b1..CMD_OE asserts one clock cycle before CMD_O.
 *  0b0..CMD_OE and CMD_O assert at the same time.
 */
#define USDHC_VEND_SPEC_CMD_OE_PRE_EN(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_OE_PRE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_OE_PRE_EN_MASK)
#define USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_MASK  (0x20000000U)
#define USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_SHIFT (29U)
/*! AC12_RD_CHKBUSY_EN - AC12_RD_CHKBUSY_EN
 *  0b1..Auto CMD12 to terminate multi-block read needs to check busy
 *  0b0..Auto CMD12 to terminate multi-block read does not need to check busy
 */
#define USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_RD_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_MASK (0x40000000U)
#define USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_SHIFT (30U)
/*! CARD_DET_IN_IDLE_ENJ - Card detection
 *  0b1..
 */
#define USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_SHIFT)) & USDHC_VEND_SPEC_CARD_DET_IN_IDLE_ENJ_MASK)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
/*! CMD_BYTE_EN - Byte access
 *  0b0..Disable
 *  0b1..Enable
 */
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */

/*! @name MMC_BOOT - MMC Boot */
/*! @{ */
#define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
/*! DTOCV_ACK - Boot ACK time out
 *  0b0000..SDCLK x 2^32
 *  0b0001..SDCLK x 2^33
 *  0b0010..SDCLK x 2^18
 *  0b0011..SDCLK x 2^19
 *  0b0100..SDCLK x 2^20
 *  0b0101..SDCLK x 2^21
 *  0b0110..SDCLK x 2^22
 *  0b0111..SDCLK x 2^23
 *  0b1110..SDCLK x 2^30
 *  0b1111..SDCLK x 2^31
 */
#define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
/*! BOOT_ACK - BOOT ACK
 *  0b0..No ack
 *  0b1..Ack
 */
#define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
/*! BOOT_MODE - Boot mode
 *  0b0..Normal boot
 *  0b1..Alternative boot
 */
#define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
/*! BOOT_EN - Boot enable
 *  0b0..Fast boot disable
 *  0b1..Fast boot enable
 */
#define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
/*! AUTO_SABG_EN - Auto stop at block gap
 */
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
/*! DISABLE_TIME_OUT - Time out
 *  0b0..Enable time out
 *  0b1..Disable time out
 */
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
 */
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */

/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */
#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK  (0x1U)
#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U)
/*! SDR104_TIMING_DIS - Timeout counter test
 *  0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21.
 *  0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15.
 */
#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK)
#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK      (0x2U)
#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT     (1U)
/*! SDR104_OE_DIS - CMD_OE / DATA_OE logic generation test
 *  0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end field
 *  0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end field
 */
#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK)
#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK     (0x4U)
#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT    (2U)
/*! SDR104_NSD_DIS - SDR104_NSD_DIS
 *  0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent.
 *  0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent.
 */
#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
/*! CARD_INT_D3_TEST - Card interrupt detection test
 *  0b0..Check the card interrupt only when DATA3 is high.
 *  0b1..Check the card interrupt by ignoring the status of DATA3.
 */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
/*! TUNING_8bit_EN - Tuning 8bit enable
 */
#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
/*! TUNING_1bit_EN - Tuning 1bit enable
 */
#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
/*! TUNING_CMD_EN - Tuning command enable
 *  0b0..Auto tuning circuit does not check the CMD line.
 *  0b1..Auto tuning circuit checks the CMD line.
 */
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U)
#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U)
/*! CARD_INT_AUTO_CLR_DIS - CARD_INT_AUTO_CLR_DIS
 *  0b0..Card interrupt status field (CINT) can be cleared when Card Interrupt status enable field is 0.
 *  0b1..Card interrupt status field (CINT) can only be cleared by writting a 1 to CINT field.
 */
#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK)
#define USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_MASK (0x100U)
#define USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_SHIFT (8U)
/*! CMD_BUSY_TRAN_CPL_EN - CMD_BUSY_TRAN_CPL_EN
 *  0b0..Disable fix
 *  0b1..Enable fix
 */
#define USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_SHIFT)) & USDHC_VEND_SPEC2_CMD_BUSY_TRAN_CPL_EN_MASK)
#define USDHC_VEND_SPEC2_TEST_SYNC_EN_MASK       (0x200U)
#define USDHC_VEND_SPEC2_TEST_SYNC_EN_SHIFT      (9U)
/*! TEST_SYNC_EN - Test sync enable
 */
#define USDHC_VEND_SPEC2_TEST_SYNC_EN(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TEST_SYNC_EN_SHIFT)) & USDHC_VEND_SPEC2_TEST_SYNC_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
 */
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
 */
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
 *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
 *  0b0..Disable
 */
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK     (0x2000U)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT    (13U)
/*! PART_DLL_DEBUG - Debug for part DLL
 */
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
#define USDHC_VEND_SPEC2_BUS_RST_MASK            (0x4000U)
#define USDHC_VEND_SPEC2_BUS_RST_SHIFT           (14U)
/*! BUS_RST - BUS reset
 */
#define USDHC_VEND_SPEC2_BUS_RST(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK         (0x8000U)
#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT        (15U)
/*! EN_32K_CLK - Enable 32khz clock for card detection
 */
#define USDHC_VEND_SPEC2_EN_32K_CLK(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK      (0xFFFF0000U)
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT     (16U)
/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock
 */
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
/*! @} */

/*! @name TUNING_CTRL - Tuning Control */
/*! @{ */
#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0xFFU)
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
/*! TUNING_START_TAP - Tuning start
 */
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
/*! TUNING_COUNTER - Tuning counter
 */
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
#define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
/*! TUNING_STEP - TUNING_STEP
 */
#define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
/*! TUNING_WINDOW - Data window
 */
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
/*! STD_TUNING_EN - Standard tuning circuit and procedure enable
 */
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
/*! @} */

/*! @name HOST_CTRL_VER - Host controller version */
/*! @{ */
#define USDHC_HOST_CTRL_VER_SVN_MASK             (0xFFU)
#define USDHC_HOST_CTRL_VER_SVN_SHIFT            (0U)
/*! SVN - Specification version number
 *  0b00000000..SD Host specification version 1.0.
 *  0b00000010..SD Host specification version 3.0, supports Test Event Register and ADMA.
 *  0b00000011-0b11111111..Reserved
 */
#define USDHC_HOST_CTRL_VER_SVN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_VER_SVN_SHIFT)) & USDHC_HOST_CTRL_VER_SVN_MASK)
#define USDHC_HOST_CTRL_VER_VVN_MASK             (0xFF00U)
#define USDHC_HOST_CTRL_VER_VVN_SHIFT            (8U)
/*! VVN - Vendor version number
 *  0b00000001..NXP uSDHC version 1.1
 *  0b00000010..NXP uSDHC version 2.0
 *  0b00000011..NXP uSDHC version 3.0
 *  0b00000100..NXP uSDHC version 4.0
 *  0b00000101..NXP uSDHC version 5.0
 */
#define USDHC_HOST_CTRL_VER_VVN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_VER_VVN_SHIFT)) & USDHC_HOST_CTRL_VER_VVN_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group USDHC_Register_Masks */


/* USDHC - Peripheral instance base addresses */
/** Peripheral USDHC0 base address */
#define USDHC0_BASE                              (0x40136000u)
/** Peripheral USDHC0 base pointer */
#define USDHC0                                   ((USDHC_Type *)USDHC0_BASE)
/** Peripheral USDHC1 base address */
#define USDHC1_BASE                              (0x40137000u)
/** Peripheral USDHC1 base pointer */
#define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
/** Array initializer of USDHC peripheral base addresses */
#define USDHC_BASE_ADDRS                         { USDHC0_BASE, USDHC1_BASE }
/** Array initializer of USDHC peripheral base pointers */
#define USDHC_BASE_PTRS                          { USDHC0, USDHC1 }

/*!
 * @}
 */ /* end of group USDHC_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- UTICK Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
 * @{
 */

/** UTICK - Register Layout Typedef */
typedef struct {
  __IO uint32_t CTRL;                              /**< Control, offset: 0x0 */
  __IO uint32_t STAT;                              /**< Status, offset: 0x4 */
  __IO uint32_t CFG;                               /**< Capture Configuration, offset: 0x8 */
  __O  uint32_t CAPCLR;                            /**< Capture Clear, offset: 0xC */
  __I  uint32_t CAP[4];                            /**< Capture, array offset: 0x10, array step: 0x4 */
} UTICK_Type;

/* ----------------------------------------------------------------------------
   -- UTICK Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup UTICK_Register_Masks UTICK Register Masks
 * @{
 */

/*! @name CTRL - Control */
/*! @{ */
#define UTICK_CTRL_DELAYVAL_MASK                 (0x7FFFFFFFU)
#define UTICK_CTRL_DELAYVAL_SHIFT                (0U)
/*! DELAYVAL - Tick interval
 */
#define UTICK_CTRL_DELAYVAL(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
#define UTICK_CTRL_REPEAT_MASK                   (0x80000000U)
#define UTICK_CTRL_REPEAT_SHIFT                  (31U)
/*! REPEAT - Repeat delay
 *  0b0..One-time delay
 *  0b1..Delay repeats continuously
 */
#define UTICK_CTRL_REPEAT(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
/*! @} */

/*! @name STAT - Status */
/*! @{ */
#define UTICK_STAT_INTR_MASK                     (0x1U)
#define UTICK_STAT_INTR_SHIFT                    (0U)
/*! INTR - Interrupt flag
 *  0b0..No interrupt is pending
 *  0b1..An interrupt is pending
 */
#define UTICK_STAT_INTR(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
#define UTICK_STAT_ACTIVE_MASK                   (0x2U)
#define UTICK_STAT_ACTIVE_SHIFT                  (1U)
/*! ACTIVE - Timer active flag
 *  0b0..The Micro-Tick Timer is not active (stopped)
 *  0b1..The Micro-Tick Timer is currently active
 */
#define UTICK_STAT_ACTIVE(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
/*! @} */

/*! @name CFG - Capture Configuration */
/*! @{ */
#define UTICK_CFG_CAPEN0_MASK                    (0x1U)
#define UTICK_CFG_CAPEN0_SHIFT                   (0U)
/*! CAPEN0 - Enable Capture 0
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN0(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
#define UTICK_CFG_CAPEN1_MASK                    (0x2U)
#define UTICK_CFG_CAPEN1_SHIFT                   (1U)
/*! CAPEN1 - Enable Capture 1
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN1(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
#define UTICK_CFG_CAPEN2_MASK                    (0x4U)
#define UTICK_CFG_CAPEN2_SHIFT                   (2U)
/*! CAPEN2 - Enable Capture 2
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN2(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
#define UTICK_CFG_CAPEN3_MASK                    (0x8U)
#define UTICK_CFG_CAPEN3_SHIFT                   (3U)
/*! CAPEN3 - Enable Capture 3
 *  0b0..Disabled
 *  0b1..Enabled
 */
#define UTICK_CFG_CAPEN3(x)                      (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
#define UTICK_CFG_CAPPOL0_MASK                   (0x100U)
#define UTICK_CFG_CAPPOL0_SHIFT                  (8U)
/*! CAPPOL0 - Capture Polarity 0
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL0(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
#define UTICK_CFG_CAPPOL1_MASK                   (0x200U)
#define UTICK_CFG_CAPPOL1_SHIFT                  (9U)
/*! CAPPOL1 - Capture Polarity 1
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL1(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
#define UTICK_CFG_CAPPOL2_MASK                   (0x400U)
#define UTICK_CFG_CAPPOL2_SHIFT                  (10U)
/*! CAPPOL2 - Capture Polarity 2
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL2(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
#define UTICK_CFG_CAPPOL3_MASK                   (0x800U)
#define UTICK_CFG_CAPPOL3_SHIFT                  (11U)
/*! CAPPOL3 - Capture Polarity 3
 *  0b0..Positive edge capture
 *  0b1..Negative edge capture
 */
#define UTICK_CFG_CAPPOL3(x)                     (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
/*! @} */

/*! @name CAPCLR - Capture Clear */
/*! @{ */
#define UTICK_CAPCLR_CAPCLR0_MASK                (0x1U)
#define UTICK_CAPCLR_CAPCLR0_SHIFT               (0U)
/*! CAPCLR0 - Clear capture 0
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP0 register value
 */
#define UTICK_CAPCLR_CAPCLR0(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
#define UTICK_CAPCLR_CAPCLR1_MASK                (0x2U)
#define UTICK_CAPCLR_CAPCLR1_SHIFT               (1U)
/*! CAPCLR1 - Clear capture 1
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP1 register value
 */
#define UTICK_CAPCLR_CAPCLR1(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
#define UTICK_CAPCLR_CAPCLR2_MASK                (0x4U)
#define UTICK_CAPCLR_CAPCLR2_SHIFT               (2U)
/*! CAPCLR2 - Clear capture 2
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP2 register value
 */
#define UTICK_CAPCLR_CAPCLR2(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
#define UTICK_CAPCLR_CAPCLR3_MASK                (0x8U)
#define UTICK_CAPCLR_CAPCLR3_SHIFT               (3U)
/*! CAPCLR3 - Clear capture 3
 *  0b0..Does nothing
 *  0b1..Write 1 to clear the CAP3 register value
 */
#define UTICK_CAPCLR_CAPCLR3(x)                  (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
/*! @} */

/*! @name CAP - Capture */
/*! @{ */
#define UTICK_CAP_CAP_VALUE_MASK                 (0x7FFFFFFFU)
#define UTICK_CAP_CAP_VALUE_SHIFT                (0U)
/*! CAP_VALUE - Captured value for the related capture event
 */
#define UTICK_CAP_CAP_VALUE(x)                   (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
#define UTICK_CAP_VALID_MASK                     (0x80000000U)
#define UTICK_CAP_VALID_SHIFT                    (31U)
/*! VALID - Captured value is valid
 *  0b0..A valid value has been not been captured
 *  0b1..A valid value has been captured, based on a transition of the related UTICK_CAPn pin
 */
#define UTICK_CAP_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
/*! @} */

/* The count of UTICK_CAP */
#define UTICK_CAP_COUNT                          (4U)


/*!
 * @}
 */ /* end of group UTICK_Register_Masks */


/* UTICK - Peripheral instance base addresses */
/** Peripheral UTICK0 base address */
#define UTICK0_BASE                              (0x4000F000u)
/** Peripheral UTICK0 base pointer */
#define UTICK0                                   ((UTICK_Type *)UTICK0_BASE)
/** Array initializer of UTICK peripheral base addresses */
#define UTICK_BASE_ADDRS                         { UTICK0_BASE }
/** Array initializer of UTICK peripheral base pointers */
#define UTICK_BASE_PTRS                          { UTICK0 }
/** Interrupt vectors for the UTICK peripheral type */
#define UTICK_IRQS                               { UTICK0_IRQn }

/*!
 * @}
 */ /* end of group UTICK_Peripheral_Access_Layer */


/* ----------------------------------------------------------------------------
   -- WWDT Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
 * @{
 */

/** WWDT - Register Layout Typedef */
typedef struct {
  __IO uint32_t MOD;                               /**< Mode, offset: 0x0 */
  __IO uint32_t TC;                                /**< Timer Constant, offset: 0x4 */
  __O  uint32_t FEED;                              /**< Feed Sequence, offset: 0x8 */
  __I  uint32_t TV;                                /**< Timer Value, offset: 0xC */
       uint8_t RESERVED_0[4];
  __IO uint32_t WARNINT;                           /**< Warning Interrupt Compare Value, offset: 0x14 */
  __IO uint32_t WINDOW;                            /**< Window Compare Value, offset: 0x18 */
} WWDT_Type;

/* ----------------------------------------------------------------------------
   -- WWDT Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup WWDT_Register_Masks WWDT Register Masks
 * @{
 */

/*! @name MOD - Mode */
/*! @{ */
#define WWDT_MOD_WDEN_MASK                       (0x1U)
#define WWDT_MOD_WDEN_SHIFT                      (0U)
/*! WDEN - Watchdog Enable
 *  0b0..Stop. The Watchdog timer is stopped.
 *  0b1..Run. The Watchdog timer is running.
 */
#define WWDT_MOD_WDEN(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
#define WWDT_MOD_WDRESET_MASK                    (0x2U)
#define WWDT_MOD_WDRESET_SHIFT                   (1U)
/*! WDRESET - Watchdog Reset Enable
 *  0b0..Interrupt. A Watchdog timeout will not cause a chip reset.
 *  0b1..Reset. A Watchdog timeout will cause a chip reset.
 */
#define WWDT_MOD_WDRESET(x)                      (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
#define WWDT_MOD_WDTOF_MASK                      (0x4U)
#define WWDT_MOD_WDTOF_SHIFT                     (2U)
/*! WDTOF - Watchdog Timeout Flag
 *  0b0..Clear.
 *  0b1..Reset. Causes a chip reset if WDRESET = 1.
 */
#define WWDT_MOD_WDTOF(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
#define WWDT_MOD_WDINT_MASK                      (0x8U)
#define WWDT_MOD_WDINT_SHIFT                     (3U)
/*! WDINT - Warning Interrupt Flag
 *  0b0..No flag.
 *  0b1..Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer greater than the value specified by WARNINT.
 */
#define WWDT_MOD_WDINT(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
#define WWDT_MOD_WDPROTECT_MASK                  (0x10U)
#define WWDT_MOD_WDPROTECT_SHIFT                 (4U)
/*! WDPROTECT - Watchdog Update Mode
 *  0b0..Flexible. The Timer Constant (TC) can be changed at any time.
 *  0b1..Threshold. The Timer Constant (TC) can be changed only after the counter is less than the value of
 *       WARNINT and WINDOW. Any attempt to change the value of the Timer Constant register (TC) with a feed sequence
 *       before the Watchdog counter is less than the values of WARNINT and WINDOW causes a Watchdog reset and sets
 *       MOD[WDTOF] = 1.
 */
#define WWDT_MOD_WDPROTECT(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
#define WWDT_MOD_LOCK_MASK                       (0x20U)
#define WWDT_MOD_LOCK_SHIFT                      (5U)
/*! LOCK - Lock
 *  0b0..No Lock
 *  0b1..Lock
 */
#define WWDT_MOD_LOCK(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
/*! @} */

/*! @name TC - Timer Constant */
/*! @{ */
#define WWDT_TC_COUNT_MASK                       (0xFFFFFFU)
#define WWDT_TC_COUNT_SHIFT                      (0U)
/*! COUNT - Watchdog Timeout Value
 */
#define WWDT_TC_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
/*! @} */

/*! @name FEED - Feed Sequence */
/*! @{ */
#define WWDT_FEED_FEED_MASK                      (0xFFU)
#define WWDT_FEED_FEED_SHIFT                     (0U)
/*! FEED - Feed Value
 */
#define WWDT_FEED_FEED(x)                        (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
/*! @} */

/*! @name TV - Timer Value */
/*! @{ */
#define WWDT_TV_COUNT_MASK                       (0xFFFFFFU)
#define WWDT_TV_COUNT_SHIFT                      (0U)
/*! COUNT - Counter Timer Value
 */
#define WWDT_TV_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
/*! @} */

/*! @name WARNINT - Warning Interrupt Compare Value */
/*! @{ */
#define WWDT_WARNINT_WARNINT_MASK                (0x3FFU)
#define WWDT_WARNINT_WARNINT_SHIFT               (0U)
/*! WARNINT - Watchdog Warning Interrupt Compare Value
 */
#define WWDT_WARNINT_WARNINT(x)                  (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
/*! @} */

/*! @name WINDOW - Window Compare Value */
/*! @{ */
#define WWDT_WINDOW_WINDOW_MASK                  (0xFFFFFFU)
#define WWDT_WINDOW_WINDOW_SHIFT                 (0U)
/*! WINDOW - Watchdog Window Value.
 */
#define WWDT_WINDOW_WINDOW(x)                    (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group WWDT_Register_Masks */


/* WWDT - Peripheral instance base addresses */
/** Peripheral WWDT0 base address */
#define WWDT0_BASE                               (0x4000E000u)
/** Peripheral WWDT0 base pointer */
#define WWDT0                                    ((WWDT_Type *)WWDT0_BASE)
/** Peripheral WWDT1 base address */
#define WWDT1_BASE                               (0x4002E000u)
/** Peripheral WWDT1 base pointer */
#define WWDT1                                    ((WWDT_Type *)WWDT1_BASE)
/** Array initializer of WWDT peripheral base addresses */
#define WWDT_BASE_ADDRS                          { WWDT0_BASE, WWDT1_BASE }
/** Array initializer of WWDT peripheral base pointers */
#define WWDT_BASE_PTRS                           { WWDT0, WWDT1 }
/** Interrupt vectors for the WWDT peripheral type */
#define WWDT_IRQS                                { NotAvail_IRQn, WDT1_IRQn }

/*!
 * @}
 */ /* end of group WWDT_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__XCC__)
  /* leave anonymous unions enabled */
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


/* ----------------------------------------------------------------------------
   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
 * @{
 */

/**
 * @brief Mask and left-shift a bit field value for use in a register bit range.
 * @param field Name of the register bit field.
 * @param value Value of the bit field.
 * @return Masked and shifted value.
 */
#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
 * @brief Mask and right-shift a register value to extract a bit field value.
 * @param field Name of the register bit field.
 * @param value Value of the register.
 * @return Masked and shifted bit field value.
 */
#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))

/*!
 * @}
 */ /* end of group Bit_Field_Generic_Macros */


/* ----------------------------------------------------------------------------
   -- SDK Compatibility
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
 * @{
 */

/* No SDK compatibility issues. */

/*!
 * @}
 */ /* end of group SDK_Compatibility_Symbols */


#endif  /* _MIMXRT595S_DSP_H_ */

