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File      : pic32cx1025sg41128_Vectors.s
Purpose   : Exception and interrupt vectors for pic32cx1025sg41128 devices.

Additional information:
  Preprocessor Definitions
    __NO_EXTERNAL_INTERRUPTS
      If defined,
        the vector table will contain only the internal exceptions
        and interrupts.
    __VECTORS_IN_RAM
      If defined,
        an area of RAM, large enough to store the vector table,
        will be reserved.

    __OPTIMIZATION_SMALL
      If defined,
        all weak definitions of interrupt handlers will share the
        same implementation.
      If not defined,
        all weak definitions of interrupt handlers will be defined
        with their own implementation.
*/
        .syntax unified

/*********************************************************************
*
*       Macros
*
**********************************************************************
*/

//
// Directly place a vector (word) in the vector table
//
.macro VECTOR Name=
        .section .vectors, "ax"
        .code 16
        .word \Name
.endm

//
// Declare an exception handler with a weak definition
//
.macro EXC_HANDLER Name=
        //
        // Insert vector in vector table
        //
        .section .vectors, "ax"
        .word \Name
        //
        // Insert dummy handler in init section
        //
        .section .init.\Name, "ax"
        .thumb_func
        .weak \Name
        .balign 2
\Name:
        1: b 1b   // Endless loop
.endm

//
// Declare an interrupt handler with a weak definition
//
.macro ISR_HANDLER Name=
        //
        // Insert vector in vector table
        //
        .section .vectors, "ax"
        .word \Name
        //
        // Insert dummy handler in init section
        //
#if defined(__OPTIMIZATION_SMALL)
        .section .init, "ax"
        .weak \Name
        .thumb_set \Name,Dummy_Handler
#else
        .section .init.\Name, "ax"
        .thumb_func
        .weak \Name
        .balign 2
\Name:
        1: b 1b   // Endless loop
#endif
.endm

//
// Place a reserved vector in vector table
//
.macro ISR_RESERVED
        .section .vectors, "ax"
        .word 0
.endm

//
// Place a reserved vector in vector table
//
.macro ISR_RESERVED_DUMMY
        .section .vectors, "ax"
        .word Dummy_Handler
.endm

/*********************************************************************
*
*       Externals
*
**********************************************************************
*/
        .extern __stack_end__
        .extern Reset_Handler
        .extern HardFault_Handler

/*********************************************************************
*
*       Global functions
*
**********************************************************************
*/

/*********************************************************************
*
*  Setup of the vector table and weak definition of interrupt handlers
*
*/
        .section .vectors, "ax"
        .code 16
        .balign 1024
        .global _vectors
_vectors:
        //
        // Internal exceptions and interrupts
        //
        VECTOR __stack_end__
        VECTOR Reset_Handler
        EXC_HANDLER NMI_Handler
        VECTOR HardFault_Handler
#ifdef __ARM_ARCH_6M__
        ISR_RESERVED
        ISR_RESERVED
        ISR_RESERVED
#else
        EXC_HANDLER MemManage_Handler
        EXC_HANDLER BusFault_Handler
        EXC_HANDLER UsageFault_Handler
#endif
        ISR_RESERVED
        ISR_RESERVED
        ISR_RESERVED
        ISR_RESERVED
        EXC_HANDLER SVC_Handler
#ifdef __ARM_ARCH_6M__
        ISR_RESERVED
#else
        EXC_HANDLER DebugMon_Handler
#endif
        ISR_RESERVED
        EXC_HANDLER PendSV_Handler
        EXC_HANDLER SysTick_Handler
        //
        // External interrupts
        //
#ifndef __NO_EXTERNAL_INTERRUPTS
        ISR_HANDLER PM_IRQHandler
        ISR_HANDLER MCLK_IRQHandler
        ISR_HANDLER OSCCTRL_XOSC0_IRQHandler
        ISR_HANDLER OSCCTRL_XOSC1_IRQHandler
        ISR_HANDLER OSCCTRL_DFLL_IRQHandler
        ISR_HANDLER OSCCTRL_DPLL0_IRQHandler
        ISR_HANDLER OSCCTRL_DPLL1_IRQHandler
        ISR_HANDLER OSC32KCTRL_IRQHandler
        ISR_HANDLER SUPC_OTHER_IRQHandler
        ISR_HANDLER SUPC_BODDET_IRQHandler
        ISR_HANDLER WDT_IRQHandler
        ISR_HANDLER RTC_IRQHandler
        ISR_HANDLER EIC_EXTINT_0_IRQHandler
        ISR_HANDLER EIC_EXTINT_1_IRQHandler
        ISR_HANDLER EIC_EXTINT_2_IRQHandler
        ISR_HANDLER EIC_EXTINT_3_IRQHandler
        ISR_HANDLER EIC_EXTINT_4_IRQHandler
        ISR_HANDLER EIC_EXTINT_5_IRQHandler
        ISR_HANDLER EIC_EXTINT_6_IRQHandler
        ISR_HANDLER EIC_EXTINT_7_IRQHandler
        ISR_HANDLER EIC_EXTINT_8_IRQHandler
        ISR_HANDLER EIC_EXTINT_9_IRQHandler
        ISR_HANDLER EIC_EXTINT_10_IRQHandler
        ISR_HANDLER EIC_EXTINT_11_IRQHandler
        ISR_HANDLER EIC_EXTINT_12_IRQHandler
        ISR_HANDLER EIC_EXTINT_13_IRQHandler
        ISR_HANDLER EIC_EXTINT_14_IRQHandler
        ISR_HANDLER EIC_EXTINT_15_IRQHandler
        ISR_HANDLER FREQM_IRQHandler
        ISR_HANDLER NVMCTRL_0_IRQHandler
        ISR_HANDLER NVMCTRL_1_IRQHandler
        ISR_HANDLER DMAC_0_IRQHandler
        ISR_HANDLER DMAC_1_IRQHandler
        ISR_HANDLER DMAC_2_IRQHandler
        ISR_HANDLER DMAC_3_IRQHandler
        ISR_HANDLER DMAC_OTHER_IRQHandler
        ISR_HANDLER EVSYS_0_IRQHandler
        ISR_HANDLER EVSYS_1_IRQHandler
        ISR_HANDLER EVSYS_2_IRQHandler
        ISR_HANDLER EVSYS_3_IRQHandler
        ISR_HANDLER EVSYS_OTHER_IRQHandler
        ISR_HANDLER PAC_IRQHandler
        ISR_RESERVED
        ISR_RESERVED
        ISR_RESERVED
        ISR_HANDLER RAMECC_IRQHandler
        ISR_HANDLER SERCOM0_0_IRQHandler
        ISR_HANDLER SERCOM0_1_IRQHandler
        ISR_HANDLER SERCOM0_2_IRQHandler
        ISR_HANDLER SERCOM0_OTHER_IRQHandler
        ISR_HANDLER SERCOM1_0_IRQHandler
        ISR_HANDLER SERCOM1_1_IRQHandler
        ISR_HANDLER SERCOM1_2_IRQHandler
        ISR_HANDLER SERCOM1_OTHER_IRQHandler
        ISR_HANDLER SERCOM2_0_IRQHandler
        ISR_HANDLER SERCOM2_1_IRQHandler
        ISR_HANDLER SERCOM2_2_IRQHandler
        ISR_HANDLER SERCOM2_OTHER_IRQHandler
        ISR_HANDLER SERCOM3_0_IRQHandler
        ISR_HANDLER SERCOM3_1_IRQHandler
        ISR_HANDLER SERCOM3_2_IRQHandler
        ISR_HANDLER SERCOM3_OTHER_IRQHandler
        ISR_HANDLER SERCOM4_0_IRQHandler
        ISR_HANDLER SERCOM4_1_IRQHandler
        ISR_HANDLER SERCOM4_2_IRQHandler
        ISR_HANDLER SERCOM4_OTHER_IRQHandler
        ISR_HANDLER SERCOM5_0_IRQHandler
        ISR_HANDLER SERCOM5_1_IRQHandler
        ISR_HANDLER SERCOM5_2_IRQHandler
        ISR_HANDLER SERCOM5_OTHER_IRQHandler
        ISR_HANDLER SERCOM6_0_IRQHandler
        ISR_HANDLER SERCOM6_1_IRQHandler
        ISR_HANDLER SERCOM6_2_IRQHandler
        ISR_HANDLER SERCOM6_OTHER_IRQHandler
        ISR_HANDLER SERCOM7_0_IRQHandler
        ISR_HANDLER SERCOM7_1_IRQHandler
        ISR_HANDLER SERCOM7_2_IRQHandler
        ISR_HANDLER SERCOM7_OTHER_IRQHandler
        ISR_HANDLER CAN0_IRQHandler
        ISR_HANDLER CAN1_IRQHandler
        ISR_HANDLER USB_OTHER_IRQHandler
        ISR_HANDLER USB_SOF_HSOF_IRQHandler
        ISR_HANDLER USB_TRCPT0_IRQHandler
        ISR_HANDLER USB_TRCPT1_IRQHandler
        ISR_HANDLER GMAC_IRQHandler
        ISR_HANDLER TCC0_OTHER_IRQHandler
        ISR_HANDLER TCC0_MC0_IRQHandler
        ISR_HANDLER TCC0_MC1_IRQHandler
        ISR_HANDLER TCC0_MC2_IRQHandler
        ISR_HANDLER TCC0_MC3_IRQHandler
        ISR_HANDLER TCC0_MC4_IRQHandler
        ISR_HANDLER TCC0_MC5_IRQHandler
        ISR_HANDLER TCC1_OTHER_IRQHandler
        ISR_HANDLER TCC1_MC0_IRQHandler
        ISR_HANDLER TCC1_MC1_IRQHandler
        ISR_HANDLER TCC1_MC2_IRQHandler
        ISR_HANDLER TCC1_MC3_IRQHandler
        ISR_HANDLER TCC2_OTHER_IRQHandler
        ISR_HANDLER TCC2_MC0_IRQHandler
        ISR_HANDLER TCC2_MC1_IRQHandler
        ISR_HANDLER TCC2_MC2_IRQHandler
        ISR_HANDLER TCC3_OTHER_IRQHandler
        ISR_HANDLER TCC3_MC0_IRQHandler
        ISR_HANDLER TCC3_MC1_IRQHandler
        ISR_HANDLER TCC4_OTHER_IRQHandler
        ISR_HANDLER TCC4_MC0_IRQHandler
        ISR_HANDLER TCC4_MC1_IRQHandler
        ISR_HANDLER TC0_IRQHandler
        ISR_HANDLER TC1_IRQHandler
        ISR_HANDLER TC2_IRQHandler
        ISR_HANDLER TC3_IRQHandler
        ISR_HANDLER TC4_IRQHandler
        ISR_HANDLER TC5_IRQHandler
        ISR_HANDLER TC6_IRQHandler
        ISR_HANDLER TC7_IRQHandler
        ISR_HANDLER PDEC_OTHER_IRQHandler
        ISR_HANDLER PDEC_MC0_IRQHandler
        ISR_HANDLER PDEC_MC1_IRQHandler
        ISR_HANDLER ADC0_OTHER_IRQHandler
        ISR_HANDLER ADC0_RESRDY_IRQHandler
        ISR_HANDLER ADC1_OTHER_IRQHandler
        ISR_HANDLER ADC1_RESRDY_IRQHandler
        ISR_HANDLER AC_IRQHandler
        ISR_HANDLER DAC_OTHER_IRQHandler
        ISR_HANDLER DAC_EMPTY_0_IRQHandler
        ISR_HANDLER DAC_EMPTY_1_IRQHandler
        ISR_RESERVED
        ISR_RESERVED
        ISR_HANDLER I2S_IRQHandler
        ISR_HANDLER PCC_IRQHandler
        ISR_HANDLER AES_IRQHandler
        ISR_HANDLER TRNG_IRQHandler
        ISR_HANDLER ICM_IRQHandler
        ISR_HANDLER PUKCC_IRQHandler
        ISR_HANDLER QSPI_IRQHandler
        ISR_HANDLER SDHC0_IRQHandler
        ISR_HANDLER SDHC1_IRQHandler
#endif
        //
        .section .vectors, "ax"
_vectors_end:

#ifdef __VECTORS_IN_RAM
        //
        // Reserve space with the size of the vector table
        // in the designated RAM section.
        //
        .section .vectors_ram, "ax"
        .balign 1024
        .global _vectors_ram

_vectors_ram:
        .space _vectors_end - _vectors, 0
#endif

/*********************************************************************
*
*  Dummy handler to be used for reserved interrupt vectors
*  and weak implementation of interrupts.
*
*/
        .section .init.Dummy_Handler, "ax"
        .thumb_func
        .weak Dummy_Handler
        .balign 2
Dummy_Handler:
        1: b 1b   // Endless loop


/*************************** End of file ****************************/
