Infineon CYT4BF
The Infineon CYT4BF devices are a subfamily of Infineon Traveo T2G microcontrollers containing dual Arm Cortex-M7F cores and an Arm Cortex-M0+ CPU.
Supported devices
Refer to the supported device list for a full list of all supported CYT4BF family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| SWD |  |
|
| JTAG | |
|
Flash banks
!!!For Flasher device support the Loader name has to be specified as "Default"'!!!
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code flash | 0x10000000 | |
|
Default | Up to 8384 KB |
| Work flash | 0x14000000 | |
|
Default | Up to 256 KB |
| Supervisory flash | 0x17000800 | |
|
Default | Up to 6656 Bytes |
For information regarding Supervisory Flash (SFlash), please refer to the Infineon Traveo T2G article.
Watchdog handling
The device has a watchdog which is disabled during flash programming.
Multi-core support
Before proceeding with this article, please refer to the generic article regarding multi-core debugging here.
The CYT4BF family comes with a variety of multi-core options.
The recommended multi-core setup is the following:
First connect to the main CM7 cores, during the connect the CM0+ core is enabled if necessary.
Then connect to the CM0+. This instance connects to the processor using a simple attach.
| Core | J-Link support |
|---|---|
| CM7_0 |
|
| CM7_1 |
|
| CM0+ |
|
The debug-related multi-core behavior of J-Link is described below for each core:
CM7_0/CM7_1 (main core)
Init/Setup
- Enables Cortex-M0+ if necessary:
- Enables power if the core is powered down
- Sets up the CPUSS_CTL register for debug use:
- Releases CPU wait
- Enables initialization of TCM after reset
- Enables RMW of TCM
Reset
- A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.
Attach
- Attach is supported / desired.
CM0+ (secondary core)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable-debug sequence.
- The core needs to be powered and released from reset prior to connect. This can be done either by the customer's application or by connecting to the CM7 first.
Reset
- The device uses normal Cortex-M reset. No special handling is necessary, as described here.
Attach
- Attach is supported / desired.
Instruction trace
For more information regarding instruction tracing for this device, see Tracing on Infineon Traveo II (CYT4BF).