The Infineon PSC3M5/PSC3P5 are Cortex-M33-based microcontrollers suitable for a wide range of secure applications.
Flash Banks
PSC3xxE, PSC3xxE_tm
| Flash bank |
Base address |
J-Link support |
Flasher support |
Loader
|
| Name |
Bank size
|
| FLASH_NS
|
0x22000000 |
 |
|
Default |
256 KB
|
| FLASH_S
|
0x32000000 |
|
|
Default |
256 KB
|
| FLASH_DBM1_NS
|
0x22800000 |
|
|
Default |
128 KB
|
| FLASH_DBM1_S
|
0x32800000 |
|
|
Default |
128 KB
|
PSC3xxF, PSC3xxF_tm
| Flash bank |
Base address |
J-Link support |
Flasher support |
Loader
|
| Name |
Bank size
|
| FLASH_NS
|
0x22000000 |
|
|
Default |
512 KB
|
| FLASH_S
|
0x32000000 |
|
|
Default |
512 KB
|
| FLASH_DBM1_NS
|
0x22800000 |
|
|
Default |
256 KB
|
| FLASH_DBM1_S
|
0x32800000 |
|
|
Default |
256 KB
|
Dual Bank Mode
- The devices can be configured to operate in either single-bank or dual-bank mode.
- For PSC3xxE devices, the 256 KB flash memory is split into two 128 KB banks in dual-bank mode.
- For PSC3xxF devices, the 512 KB flash memory is split into two 256 KB banks in dual-bank mode.
- When dual-bank mode is enabled, make sure to also enable the corresponding
FLASH_DBM1_NS or FLASH_DBM1_S FlashBank.
- The alternate bank is accessible at
0x22800000 through the non-secure alias and at 0x32800000 through the secure alias.
PSC3xxE Flash Layout
| Mode
|
Start address
|
Size
|
Description
|
| Dual-bank mode
|
0x22000000
|
128 KB
|
Main bank
|
| 0x22800000
|
128 KB
|
Alternate bank
|
| Single-bank mode
|
0x22000000
|
256 KB
|
Single bank
|
PSC3xxF Flash Layout
| Mode
|
Start address
|
Size
|
Description
|
| Dual-bank mode
|
0x22000000
|
256 KB
|
Main bank
|
| 0x22800000
|
256 KB
|
Alternate bank
|
| Single-bank mode
|
0x22000000
|
512 KB
|
Single bank
|
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog reset is disabled when the debugger is connected.
Device Specific Handling
Connect
- PSC3xxF_tm/PSC3xxE_tm: If a normal connect attempt fails, J-Link connects using Test Mode Acquisition sequence, see Test Mode Acquisition
Reset
- The device uses custom reset: Hardware pin reset, RESET(15) must be connected to function.
Attach
Test Mode Acquisition
Test mode acquisition is implemented for the PSC3xxF_tm/PSC3xxE_tm device names.
If DAP is not accessible, it is possible that the users firmware reconfigured the debug pins to be used as GPIO or disabled the debug port. In this case, J-Link tries to connect to the device in Test mode (TM).
Evaluation Boards
Example Application