Infineon PSoC Edge E8
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The Infineon PSoC Edge E8 is a family of microcontrollers (MCUs) designed for edge-AI and machine-learning-enhanced sensing applications.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| RRAM_NS [1] | 0x22011000 | 
|
default | Up to 356 KB |
| RRAM_S [1] | 0x32011000 |
|
default | Up to 356 KB |
| SMIF0_NS [2] | 0x60000000 |
|
default | 64 MB |
| SMIF0_S [2] | 0x70000000 |
|
default | 64 MB |
- ↑ 1.0 1.1 RRAM is divided into multiple regions, not all of which can be programmed. See RRAM limitations for details.
- ↑ 2.0 2.1
QSPI flash programming requires special handling compared to internal flash. For more information, see the QSPI Flash Programming Support article.
Watchdog Handling
- The device includes two watchdogs: the Free-Running Watchdog Timer (WDT) and the Multi-Counter Watchdog.
- Both watchdogs are serviced during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The PSoC Edge E8 family comes with a variety of multi-core options.
The devices from this family feature the APPCPU which is disabled after reset / by default.
| Core | J-Link Support |
|---|---|
| SYSCPU (CM33) |
|
| APPCPU (CM55) |
|
Below, the debug related multi-core behavior of the J-Link is described for each core:
SYSCPU
Init/Setup
- Enables debugging
Reset
- Resets the core via a AIRCR.SYSRESETREQ and halts execution after the bootloader when a valid VTOR is detected.
- Skips the reset and sets the PC to a debug loop in the SRAM when no valid VTOR is detected.
Attach
- Attach is supported
APPCPU
Init/Setup
- The core is powered up and enabled via the SYSCPU.
Reset
- Resets the core via a system reset and halts execution after the bootloader when a valid VTOR is detected.
- Skips the reset and sets the PC to a debug loop in the CM55_ITCM when no valid VTOR is detected.
Attach
- Attach is supported with the J-Link Command String "ForceAttachTarget" option.
Limitations
Flash programming
- Flash programming is supported only via the SYSCPU, as the APPCPU does not have access to the peripheral registers.
RRAM
- RRAM is divided into multiple regions. Not all regions are programmable. Unsupported sectors must be deselected by the user, as they are device- and configuration-specific.