J-Link NEORV32

The NEORV32 is an free and open-source RV32 based RISC-V CPU that is supported by J-Link. In addition to this article, the generic RISC-V specifics apply. See separate knowledge base article

Eval board

NEORV32 is an open-source implementation and therefore mainly distributed on FPGA as softcore. There is currently (June 2026) no out-of-the-box evaluation board available with this core.

However, the community provides some resources and tutorials to get NEORV32 running on FPGA hardware:

• FPGA maker board (Terasic DE0-NANO) and a good tutorial (2022) from emb4fun: Tutorial

JTAG speed

• The JTAG speed used must not exceed 1/5 of the current CPU speed of the NEORV32.
• Up to version 1.6.3.11 (22nd November 2021) the JTAG interface of the NEORV32 was not JTAG compliant and changed the data on the wrong edge of TCK.
  This could cause problems when using JTAG speeds of 4 MHz and higher.

RTT support

Unfortunately, the NEORV32 does not support system bus access and therefore does not have RTT support.

Debug Support

J-Link natively supports debugging on NEORV32 since V9.54.

See also RISC-V Debugging for more information about general RISC-V debugging and supported features.