NXP 8MPLUSLPD4 EVK

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This article describes specifics for the NXP 8MPLUSLPD4-EVK evaluation board. It can be used to test & verify NXP iMX 8M Plus device support.

Minimum requirements

J-Link software V7.94 or later
The board should have a bootloader(U-Boot) image on one of the available boot device

Preparing for J-Link

Connect the J-Link to JTAG connector (J24).
Connect the onboard USB-UART debug interface to host computer (J23).
Open a serial interface communication via terminal application(PuTTY).
Power the board via USB Type-C Power connector (J5).
Turn on the power switch (SW3).
Wait until the bootloader is started and interrupt the loading of the operating system(Linux Kernel). The output should look as follows:

Verify the Connection with e.g. J-Link Commander. The output should look as follows:

Example Project

The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the NXP 8MPLUSLPD4-EVK.
It is a simple Hello World sample linked into the internal flash.

SETUP

J-Link software: V7.94
Embedded Studio: V8.10
Hardware: NXP 8MPLUSLPD4-EVK
Link: File:NXP 8MPLUSLPD4 EVK M7 TestProject ES 8V10.zip

Tracing on NXP iMX8MPlus

This section describes how to get started with trace on the NXP iMX8MPlus MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Minimum requirements

In order to use trace on the NXP iMX8MPlus MCU devices, the following minimum requirements have to be met:

J-Link software version V9.62 or later
Ozone V3.40j or later (if streaming trace and / or the sample project from below shall be used)

J-Link Plus V12 or later for buffer (on-chip) trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.28. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Cortex-A53_0

The project below has been tested with the minimum requirements mentioned above and a i.MX_8M Plus EVK.

Example project: NXP_IMX8MPlus_A53_0_TraceExample.zip

Trace buffer

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Cortex-A53_1

The project below has been tested with the minimum requirements mentioned above and a i.MX_8M Plus EVK.

Example project: NXP_IMX8MPlus_A53_1_TraceExample.zip

Trace buffer

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Cortex-A53_2

The project below has been tested with the minimum requirements mentioned above and a i.MX_8M Plus EVK.

Example project: NXP_IMX8MPlus_A53_2_TraceExample.zip

Trace buffer

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Cortex-A53_3

The project below has been tested with the minimum requirements mentioned above and a i.MX_8M Plus EVK.

Example project: NXP_IMX8MPlus_A53_3_TraceExample.zip

Trace buffer

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Cortex-M7

The project below has been tested with the minimum requirements mentioned above and a i.MX_8M Plus EVK.

Example project: NXP_IMX8MPlus_M7_TraceExample.zip

Trace buffer

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Running the Examples

Before running the examples, a few initialization steps need to be performed to ensure that debugging with buffer trace is possible for all four Cortex-A53 cores and the Cortex-M7 core. Each core which should be traced needs to be powered up and released before launching a debug session. The easiest way to achieve this, is using the U-Boot cpu command, which can control individual cores. As this command is not included in the U-Boot build shipped with the default NXP Linux image, the Real-Time Edge Software for NXP MCIMX93-EVK should be flashed either to the EMMV or to the SD-Card.

Insert an SD-Card into the SD Card slot of the EVK.
Set the board to serial downloader boot mode (SW4: 0b0001).
Connect a USB cable to USB PORT1
Install uuu and run following command:

uuu.exe -b sd_all ./Real-time_Edge_v3.4_IMX8MP-LPDDR4-EVK/real-time-edge/nxp-image-real-time-edge-imx8mp-lpddr4-evk.rootfs.wic.zst

Wait for uuu to flash SD card.
Set board to SD Card boot mode (SW4: 0b0011).
Connect a USB cable to the USB DEBUG port.
Open a serial terminal and connect to the EVK UART interface.
Wait for U-Boot to boot and interrupt the Linux boot flow by pressing a key when prompted to do so:

BuildInfo:
  - ELE firmware version 0.0.10-af252062

switch to partitions #0, OK
mmc1 is current device
flash target is MMC:1
Net:   eth0: ethernet@42890000, eth1: ethernet@428a0000 [PRIME]
Fastboot: Normal
Normal Boot
Hit any key to stop autoboot:  0 
u-boot=>

Check if the cpu command is implemented. The output should look as follows:

u-boot=> cpu
cpu - Multiprocessor CPU boot manipulation and release

Usage:
cpu <num> reset                 - Reset cpu <num>
cpu status                      - Status of all cpus
cpu <num> status                - Status of cpu <num>
cpu <num> disable               - Disable cpu <num>
cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]
u-boot=>

Add environment variables for releasing each of the A53 cores and for disabling the I-cache and D-cache:

u-boot=> setenv boot_a53_1 "mw 0xA0000000 14000000; cpu 1 release 0xA0000000"
u-boot=> setenv boot_a53_2 "mw 0xA0000000 14000000; cpu 2 release 0xA0000000"
u-boot=> setenv boot_a53_3 "mw 0xA0000000 14000000; cpu 3 release 0xA0000000"
u-boot=> setenv disable_caches "dcache off; icache off"
u-boot=> saveenv
Saving Environment to MMC... Writing to MMC(1)... OK
u-boot=>

Set the U-Boot boot command to disable the caches and release all secondary cores instead of booting Linux:

u-boot=> setenv bootcmd "disable_caches; run boot_a53_1; run boot_a53_2; run boot_a53_3"
u-boot=> saveenv
Saving Environment to MMC... Writing to MMC(1)... OK
u-boot=>

Reboot the board and wait for U-Boot to finish the boot process. After this, you should be able to debug and trace all fours Cortex-A53 cores and the Cortex-M7 core after each power-up without any further initialization steps.

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