NXP S32G2
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The NXP S32G2 device family consists of high-performance vehicle network processors.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| QSPI Flash[1] | 0x00000000 | 
|
Default | up to 512 MB |
- ↑
QSPI flash programming requires special handling compared to internal flash. For more information, please refer to the QSPI Flash Programming Support article.
Watchdog Handling
- The watchdog is disabled on connect.
Multi-Core Support
Before proceeding with this article, please refer to the generic article on multi-core debugging: here.
The S32G2 family features three Cortex-M7 cores and four Cortex-A53 cores.
| Core | J-Link Support |
|---|---|
| Cortex-M7 CPU0 | 
|
| Cortex-M7 CPU1 |
|
| Cortex-M7 CPU2 |
|
| Cortex-A53 Cluster 0 CPU 0 |
|
| Cortex-A53 Cluster 0 CPU 1 |
|
| Cortex-A53 Cluster 1 CPU 0 |
|
| Cortex-A53 Cluster 1 CPU 1 |
|
Below, the debug-related multi-core behavior of the J-Link is described for each core:
Cortex-M7
Init/Setup
- The core power-on sequence is executed if the core is powered down.
Reset
- The device uses a custom reset:
- System destructive reset
Attach
- Attach is supported
Cortex-A53
Init/Setup
- Watchdogs are disabled.
- SRAM is initialized if necessary.
- A debug loop is written to SRAM.
- The partition and core power-on sequence is executed if the core is powered down.
Reset
- The device uses a custom reset:
- System destructive reset
Attach
- Attach is supported