Signal Integrity
Introduction
The integrity of electrical signals on connection lines between probe / programmer and target is crucial to guarantee a stable and successful connection for operations like debugging or flash programming.
Insufficient signal integrity could lead to an instable or erroneous target communication, or even reduced flash retention times, in the case of flash programming operations.
There are different effects to be aware of, that can negatively affect signal integrity.
Overshoot / Undershoot
Overshoot is an electrical effect that occurs when a signal briefly exceeds its intended voltage level during a transition, typically when switching between low and high states at high speed.
Undershoot is an electrical effect that occurs when a signal briefly drops below its intended voltage level during a transition.
While small amounts of overshoot or undershoot are often harmless, excessive overshoot or undershoot can lead to unreliable communication, intermittent flashing or debugging failures, and in severe cases may stress or damage input pins on the target device.
More detailed information on overshoot: Wikipedia - Overshoot (signal).
Overshoot or undershoot are commonly caused by:
- Long or poorly terminated cables
- High signal edge rates
- Impedance mismatches between probe / programmer, target board, and wiring
- Inadequate grounding or PCB layout issues
The following measures can be taken to reduce overshoot / undershoot:
- Shorten debug cables
- Lower interface clock speed
- Improve grounding connections
- Add series termination resistors when appropriate
- Follow recommended PCB routing practices for debug interfaces
- Evaluation boards from the target chip vendor may serve as a working reference
- Adjust driver strength
- Signal smoothing adapter
Target specifications
Most MCU and peripheral datasheets specify absolute maximum ratings and often allow limited overshoot or undershoot beyond the supply rails for a short time.
Whether these limits are met depends primarily on the target hardware design rather than the software controlling the interface. The only influence the software has is drive strength / slew rate configuration, which is configurable, in many cases.
Software such as flash loaders or debugging tools only configure the MCU peripherals and IO pin settings. The resulting signal waveform is determined by the electrical behavior of the target hardware.
Adjusting driver strength
Many MCUs provide configurable parameters for IO pins, such as:
- Drive strength
- Slew rate
- Output speed configuration
Adjusting these settings can help reduce overshoot or undershoot on a specific hardware platform. In general, higher drive strength and higher slew rates lead to more overshoot / undershoot, hence low drive strength are more desirable. It is recommended to bring drive strength and slew rates as high as necessary and check the resulting signal quality before using a flash loader in production. If required, such configuration can be modified before running an application or flash loader. For example, settings can be applied using a script file.
Ringing
Ringing is an electrical effect where a signal oscillates above and below its intended voltage level for a short period after a transition, usually following an event of overshoot or undershoot. In some cases, an overshoot or undershoot event by itself may not have caused noticeable issues, but the follow-up ringing can.
Most MCU and peripheral datasheets specify I/O input low level voltage (e.g. VIL) and I/O input high level voltage (e.g. VIH) that describe the voltage thresholds at which the target recognizes a signal as high level (HI / 1) or low level (LO / 0).
In extreme cases, a signal ringing after an edge could cause the voltage level to cross that threshold, which can cause the target chip to recognize an additional edge.
In case of clock signals, like SWCLK in case of SWD, such an additional edge causes the communication protocol to get out-of-sync.
The same measures that reduce overshoot or undershoot also reduce the follow-up ringing.
Crosstalk
Crosstalk is an electrical effect where signals on one wire or trace unintentionally interfere with nearby signals.
The impact of crosstalk increases with increasing proximity of multiple signals, as well as with increasing frequency of multiple signals.
Crosstalk is commonly caused by:
- Closely spaced PCB traces or cables
- Long parallel signal runs
- Fast signal edge rates
- Inadequate grounding or shielding
- Poor PCB layout practices
Ways to reduce crosstalk include:
- Increasing spacing between signal traces
- Reducing parallel routing distances
- Improving grounding and shielding
- Lowering interface speeds where appropriate
- Following signal integrity best practices during PCB layout
- Evaluation boards from the target chip vendor may serve as a working reference
Probe loading
Connecting an oscilloscope probe to a circuit is not electrically neutral. It can influence the very signal being measured.
This is known as probe loading, and it can affect signal integrity, especially in high-speed or sensitive digital systems such as debug interfaces and flash programming lines.
Even a standard probe adds capacitance, resistance, and inductance to the circuit. This additional load can slightly slow down signal edges, increase overshoot or ringing, or in some cases distort the signal enough to affect measurement accuracy or even system behavior. The effect becomes more pronounced as signal speeds increase and edge transitions become faster.
Key factors to consider when probing signals include:
- The probe’s input capacitance and resistance
- Ground lead length (long ground leads can significantly worsen ringing and distortion)
- Signal speed and edge rate
- Whether the circuit is high-impedance or weakly driven
- Proper grounding close to the measurement point
- Passive vs Active Probes
Passive probes are the most common type and typically use a resistor-capacitor network to attenuate and measure signals. While versatile and inexpensive, they usually have higher input capacitance, which can place a heavier load on fast or sensitive signals, making them more likely to affect signal integrity.
Active probes, on the other hand, use built-in electronic buffering very close to the probe tip. This results in much lower input capacitance and higher bandwidth, meaning they disturb the circuit significantly less. They are better suited for high-speed digital signals, but are more expensive and require power.
In general, passive probes are sufficient for slower or less sensitive signals, while active probes are preferred when measuring high-speed debug lines or when preserving signal integrity is critical.
The oscilloscope screenshots on the right demonstrate how just attaching a passive probe to a signal leads to a noticeably smoother voltage curve.
Examples
QSPI flash interface
High-speed flash interfaces such as QSPI are particularly sensitive to signal integrity effects due to their higher clock frequencies.
For example, QSPI flash datasheets often allow limited overshoot or undershoot beyond the supply rails for a short duration (e.g. VCC ±2 V for up to ~20 ns, depending on the device).
If excessive ringing or overshoot occurs on a particular hardware platform, mitigation options include:
- Adjusting MCU IO drive strength or slew rate
- Reducing interface clock frequency
- Adding series resistors for signal damping
- Reviewing PCB routing and termination
See also: QSPI Flash Programming and Debugging Support
SWD clock
When communicating with a STM32WB55RG on P-NUCLEO-WB55 via SWD with a Flasher Compact, establishing the target connection fails with an error.
Further investigations show that the error no longer occurs under the following circumstances:
- Inserting a Measurement+Patch adapter into the connection between programmer and target,
or - Attaching an oscilloscope's passive probe to the SWCLK signal
(1) and (2) both indicate that a slightly smoother signal, caused by additional capacitance (probe loading), or increased wire length / resistance, is sufficient to make the target communication succeed again.
These, in turn, are indicators that the signal integrity of the SWCLK line is insufficient.
(2) indicates that the clock signal is responsible for the communication error.
The SWCLK signal voltage curve measurements done by an oscilloscope's active probe show that, following a rising edge (LO → HI), the signal overshoots the destination voltage (VDD = 3.3V).
After overshooting, the signal is subject to ringing, causing the voltage to drop significantly before stabilizing on the desired target voltage, VDD.
Due to the drop, the voltage fell below the target's I/O input low level voltage (VIL = ca. 1.227V), which can cause the target to recognize the drop in voltage as a falling edge.
The following rise in voltage exceeds the target's I/O input high level voltage (VIH = ca. 1.877V) would then be recognized as another rising edge.
This leads to the target seeing two pairs of rising and falling edges, instead of just one, bringing the whole target communication out-of-sync.
Solution: After inserting a Signal Smoothing Adapter, the voltage curves are smoother, overshooting and ringing is flattened and communication succeeds.
Responsibility for electrical compliance
Tools provided by SEGGER configure and use MCU peripherals according to the available documentation and reference hardware.
However, SEGGER cannot guarantee that signal levels on a given target board remain within the electrical limits specified in MCU or peripheral datasheets. This depends on the electrical characteristics of the customer's hardware design.
Ensuring that signal levels comply with the relevant specifications is therefore the responsibility of the target hardware design and system integration.
Recommendations
If signal integrity issues are suspected, the following steps are recommended:
- Verify signal levels using an oscilloscope
- Consider the effects of probe loading
- Compare the measured values against the limits specified in the device datasheets.
- Adjust I/O drive strength or slew rate, if supported by the target.
- Consider target hardware-level mitigation such as series resistors or layout improvements.
- Consider using a Signal Smoothing Adapter