TI MSPM33
The TI MSPM33 family is based on the ARM Cortex-M33 core.
Flash Banks
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | Up to 1024 KB | 
|
| Data Flash | 0x80000000 | 32 KB |
|
| NONMAIN Bank 0 | 0x80101800 | 2 KB |
|
| NONMAIN Bank 1 | 0x80103800 | 2 KB |
|
| FACTORY | 0x80110000 | 8 KB | 
|
ECC flash
The flash is ECC protected.
- When programming code with J-Link, the device flash controller is set to automatically program the correct ECC values.
- Manual ECC programming is currently not supported by J-Link.
ECC RAM
The device has SRAM with ECC that is initialized on connect.
Watchdog Handling
The device has two watchdogs:
- IWDT is turned off during flash programming and turned back on afterwards if enabled.
- WWDT is fed during flash programming but there is one restriction: As the watchdog counter cannot be read directly, flash programming is only supported for devices where WWDT is not running in window mode.
Device Specific Handling
Connect
Some device specific debug bits are set which prevents the device to enter sleep mode and allows debugging of applications which make use of low power modes.
Reset
A device specific reset is performed for this device because the peripherals are not reset when executing the Cortex-M default reset. A SYSRST is executed via the device specific SYSCTL register instead. The bootloader runs first and execution is halted when jumping to the application.
NONMAIN Flash Programming
NONMAIN flash memory stores the device’s BCR and BSL configurations. Each configuration includes a CRC32 checksum at the end of its memory range. To prevent potential device lockups, the NONMAIN flashloader calculates the CRC32 checksum of each configuration’s data in the input file and compares it with the checksum provided in the same file at ADDR_END - 4, where ADDR_END is the exclusive end address of the configuration range. If either checksum does not match, the erase and program operations are aborted. The NONMAIN flashloader does not support standalone erase operations. Memory is erased only after both CRC32 checksums have been successfully verified and immediately before programming.