TI AM62xx
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The TI AM62xx are low-cost processors featuring scalable Arm Cortex-A53 performance, dual-display and 3D graphics support, rich connectivity, real-time I/O capabilities, and advanced power and security features—ideal for industrial and automotive applications.
Watchdog Handling
- The device has a watchdog, which is enabled after power on and will reset the device if the next boot stage is not complete within three minutes.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The AM62x family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| Up to 4x ARM Cortex-A53 | 
|
| 1x ARM Cortex-R5 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
ARM Cortex-R5 core
Init/Setup
- It is the main core responsible for chip boot process. It is available for debug from the board power on.
Reset
- The device uses Cortex-R reset, no special handling necessary, like described here.
Attach
- Attach is supported.
ARM Cortex-A53 core
Init/Setup
- Cortex-A53 core cluster is not available for debug, until it is enabled by bootloader (SPL/U-Boot).
Reset
- Reset is not implemented, as device uses bootloader and can restrinct access to system resources.
Attach
- Attach is supported.